i
TABLE OF CONTENTS
LCD SEGMENT / COMMON DRIVER WITH CONTROLLER ..................................................................... 1
FEATURES ................................................................................................................................................... 1
ORDERING INFORMATION ........................................................................................................................ 2
BLOCK DIAGRAM ...................................................................................................................................... 3
DIE PAD ARRANGEMENT .......................................................................................................................... 3
DIE PAD ARRANGEMENT .......................................................................................................................... 4
PIN DESCRIPTION....................................................................................................................................... 7
FUNCTIONAL BLOCK DESCRIPTIONS................................................................................................... 12
COMMAND TABLE .................................................................................................................................... 19
COMMAND TABLE .................................................................................................................................... 20
DC CHARACTERISTICS............................................................................................................................ 32
AC CHARACTERISTICS............................................................................................................................ 34
APPLICATION EXAMPLES ....................................................................................................................... 38
INITIALIZATION ROUTINE ........................................................................................................................ 40
APPENDIX 1 TAB DRAWING................................................................................................................. 41
SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
This document contains information on a new product. Specifications and information herein are subject to change without
notice.
http://www.solomon-systech.com
SSD1818A
Rev 1.1
P 1/43
Oct 2003
Copyright
2003 Solomon Systech Limited
SSD1818A
Advance Information
CMOS
LCD Segment / Common Driver with Controller
SSD1818A is a single-chip CMOS LCD driver with controllers for dot-matrix graphic liquid crystal
display system. It consists of 169 high-voltage driving outputs for driving maximum 104 Segments, 64
Commons and 1 icon line.
SSD1818A consists of 104 x 65 bits Graphic Display Data RAM (GDDRAM). Data/Commands are sent
from common MCU through 8-bit Parallel or 4-wire Serial Interface. 6800-series, 8080-series compatible
Parallel Interface and Serial Peripheral Interface can be selected by hardware configuration.
SSD1818A embeds DC-DC Converter with booster capacitors, On-Chip Oscillator and Bias Divider so as
to reduce the number of external components. With the advanced design for low power consumption,
stable LCD operating voltage and flexible die layout, SSD1818A is suitable for any portable battery-driven
applications requiring long operation period with compact size.
FEATURES
Maximum display size: 104 x 64 + 1 Icon Line
Single Supply Operation, 2.4 V - 3.5V
Minimum -12.0V LCD Driving Output Voltage
Low Current Sleep Mode
On-Chip Voltage Generator or External LCD Driving Power Supply Selectable
2X / 3X / 4X/ 5X On-Chip DC-DC Converter
On-Chip Oscillator
On-Chip Bias Divider
Programmable bias ratio [1/4-1/9]
8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface and Serial Peripheral Interface
On-Chip 104 X 65 Graphic Display Data RAM
Row Re-mapping and Column Re-mapping
Vertical Scrolling
Display Offset Control
64 Level Internal Contrast & External Contrast Control
Programmable LCD Driving Voltage Temperature Coefficients
Programmable MUX ratio [2-64 MUX] (Partial display mode)
Available in Gold Bump Die
Solomon Systech
Oct 2003
P 2/43
Rev 1.1
SSD1818A
ORDERING INFORMATION
Table 1 - Ordering Information
Ordering Part
Number
SEG
COM
Default Bias
Package Form
Reference
SSD1818AZ
104
64 + 1
1/9, 1/7
Gold Bump Die
SSD1818ATR1 96
54
1/8.4,
1/6
TAB
SSD1818A
Rev 1.1
P 3/43
Oct 2003
Solomon Systech
BLOCK DIAGRAM
ICONS
ROW0 ~
ROW63
SEG0 ~SEG103
HV Buffer Cell Level Shifter
Display Data Latch
GDDRAM
104 X 65 Bits
Display
Timing
Generator
Oscillator
Level
Selector
LCD Driving
Voltage
Generator
2X/ 3X/ 4X/ 5X
DC/ DC Converter,
Voltage Regulator,
Contrast Control,
Bias Divider
Temperature
Compensation
Command Decoder
Parallel / Serial
Interface
Command Interface
MSTAT
M
DOF
M/S
CL
CLS
V
SS
V
DD
C
0
C
1
V
L6
V
L5
V
L4
V
L3
V
L2
V
DD
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
[SCK]
[SDA]
V
EE
V
SS1
C
4N
C
3N
C
1P
C
1N
C
2N
C
2P
IRS
SPI
1
CS CS2 RES D/ C R/
W
E C68/ 80 P/ S
(
WR
) (
RD )
V
F
Solomon Systech
Oct 2003
P 4/43
Rev 1.1
SSD1818A
DIE PAD ARRANGEMENT
Figure 2 SSD1818A Pin Assignment
Gold Bump Alignment Mark
This alignment mark contains gold bump
for IC bumping process alignment and IC
identifications. No conductive tracks
should be laid underneath this mark to
avoid short circuit.
Note:
1. The gold bumps face up in this
diagram
2. All dimensions in m and (0,0)
is the center of the chip
Die Size:
8.66 mm X 1.48 mm
Die Thickness: 550 +/- 25 um
Bump Pitch:
60 um [Min]
Bump Height: Nominal 18 um
Tolerance:
< 3 um within die
PIN #1
(-3878.7, 237.475)
X
35
8.75
26.
25 26.
25 26.
25
X
Center (-3876.1625, 323.6625)
26.25 26.25 26.25
26.
25 52.
5
X
Center (2751.9625, 323.6625)
26.25 26.25 26.25
12.
6
Center (3875.55, 149.275)
16.8 13.65 12.6
73.
5
73.5
16.
8 13.
65
X
8.75
(2755.725, 237.475)
35
T2
T1
T0
/SPI
VSS
IRS
VDD
C1
VSS
C0
VDD
P/S
C68/80
VSS
CLS
M/S
VDD
VF
VL6
VL6
VL6
VL5
VL5
VL5
VL4
VL4
VL4
VEE
VL3
VL3
VL3
VL2
VL2
VL2
VEE
C4N
C4N
C4N
C2P
C2P
C2P
C2N
C2N
C2N
VEE
C1N
C1N
C1N
C1P
C1P
C1P
C3N
C3N
C3N
TEST2
VEE
VEE
VEE
VEE
VEE
VEE
VSS1
VSS1
VSS1
VSS1
VSS1
VSS
VSS
VSS
TEST1
TEST0
VDD
VDD
VDD
VDD
VDD
VDD
VDD
D7
D6
D5
D4
D3
D2
D1
D0
VDD
E/RD
R/W
VSS
D/C
VEE
VEE
/RES
VDD
CS2
/CS1
VSS
/DOF
CL
M
MSTAT
NC
RO
W
11
RO
W
12
RO
W
13
RO
W
14
RO
W
15
RO
W
16
RO
W
17
RO
W
18
RO
W
19
RO
W
20
RO
W
21
RO
W
22
RO
W
23
RO
W
24
RO
W
25
RO
W
26
RO
W
27
RO
W
28
RO
W
29
RO
W
30
RO
W
31
NC
ROW10
ROW9
ROW8
ROW7
ROW6
ROW5
ROW4
ROW3
ROW2
ROW1
ROW0
ICONS
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
ROW32
ROW33
ROW34
ROW35
ROW36
ROW37
ROW38
ROW39
ROW40
ROW41
ROW42
ROW43
NC
RO
W
4
4
RO
W
4
5
RO
W
4
6
RO
W
4
7
RO
W
4
8
RO
W
4
9
RO
W
5
0
RO
W
5
1
RO
W
5
2
RO
W
5
3
RO
W
5
4
RO
W
5
5
RO
W
5
6
RO
W
5
7
RO
W
5
8
RO
W
5
9
RO
W
6
0
RO
W
6
1
RO
W
6
2
RO
W
6
2
I
C
ONS
NC
254 255
1
C
e
nter
: 2751.
9625,
323.
6625
C
e
nter
: -
3876.
1625,
323.
6625
C
e
nter
: -
3875.
55,
149.
275
Size:
88.
2
x
88.
2
277
276
126
125
104 103
(-3878.7, 237.475)
(2755.725, 237.475)
SSD1818A
Rev 1.1
P 5/43
Oct 2003
Solomon Systech
Table 2 - SSD1818A Series Bump Die Pad Coordinates (Bump center)
Pad
# Signal X-pos Y-pos Pad
# Signal X-pos Y-pos Pad
# Signal X-pos Y-pos
1
MSTAT -3873.80 -581.35
51
C3N
-27.48 -581.35
101
T1
3799.95 -581.35
2 M
-3797.50
-581.35
52
C1P
48.83
-581.35
102
T2
3876.25
-581.35
3
CL -3721.20
-581.35 53 C1P 125.13
-581.35 103 NC 4178.48
-655.03
4
DOF
-3644.90 -581.35
54
C1P
201.43 -581.35
104 ROW31 4178.48 -594.83
5 VSS
-3568.60
-581.35
55 C1N
277.73
-581.35
105
ROW30
4178.48
-534.63
6
CS
-3492.30 -581.35
56
C1N
354.03 -581.35
106 ROW29 4178.48 -474.43
7 CS2
-3416.00
-581.35
57 C1N
430.33
-581.35
107
ROW28
4178.48
-414.23
8 VDD
-3339.70
-581.35
58 VEE
506.63
-581.35
108
ROW27
4178.48
-354.03
9
RES
-3263.40 -581.35
59
C2N
582.93 -581.35
109 ROW26 4178.48 -293.83
10 VEE
-3178.35
-581.35
60 C2N
659.23
-581.35
110
ROW25
4178.48
-233.63
11 VEE
-3102.05
-581.35
61 C2N
735.53
-581.35
111
ROW24
4178.48
-173.43
12
D/
C
-3017.00 -581.35
62
C2P
811.83 -581.35
112 ROW23 4178.48 -113.23
13 VSS
-2940.70
-581.35
63 C2P
888.13
-581.35
113
ROW22
4178.48
-53.03
14
R/
W
-2864.40 -581.35
64
C2P
964.43 -581.35
114 ROW21 4178.48 7.18
15
E/
RD
-2788.10 -581.35
65
C4N 1040.73 -581.35
115 ROW20 4178.48 67.38
16 VDD
-2711.80
-581.35
66 C4N
1117.03
-581.35
116
ROW19
4178.48
127.58
17 D0
-2635.50
-581.35
67 C4N
1193.33
-581.35
117
ROW18
4178.48
187.78
18 D1
-2557.63
-581.35
68 VEE
1269.63
-581.35
118
ROW17
4178.48
247.98
19 D2
-2481.33
-581.35
69 VL2
1345.93
-581.35
119
ROW16
4178.48
308.18
20 D3
-2403.10
-581.35
70 VL2
1422.23
-581.35
120
ROW15
4178.48
368.38
21 D4
-2325.23
-581.35
71 VL2
1498.53
-581.35
121
ROW14
4178.48
428.58
22 D5
-2248.93
-581.35
72 VL3
1574.83
-581.35
122
ROW13
4178.48
488.78
23 D6
-2172.63
-581.35
73 VL3
1651.13
-581.35
123
ROW12
4178.48
548.98
24 D7
-2096.33
-581.35
74 VL3
1727.43
-581.35
124
ROW11
4178.48
609.18
25 VDD -2020.03
-581.35 75 VEE 1803.73
-581.35 125 NC 4178.48
663.25
26 VDD
-1943.73
-581.35
76 VL4
1880.03
-581.35
126
ROW10
3834.60
587.83
27 VDD
-1867.43
-581.35
77 VL4
1956.33
-581.35
127
ROW9
3774.40
587.83
28 VDD
-1791.13
-581.35
78 VL4
2032.63
-581.35
128
ROW8
3714.20
587.83
29 VDD
-1714.83
-581.35
79 VL5
2108.93
-581.35
129
ROW7
3654.00
587.83
30 VDD
-1638.53
-581.35
80 VL5
2185.23
-581.35
130
ROW6
3593.80
587.83
31 VDD
-1562.23
-581.35
81 VL5
2261.53
-581.35
131
ROW5
3533.60
587.83
32 TEST0
-1485.93
-581.35 82 VL6
2337.83
-581.35 132 ROW4
3473.40
587.83
33 TEST1
-1409.63
-581.35 83 VL6
2414.13
-581.35 133 ROW3
3413.20
587.83
34 VSS
-1333.33
-581.35
84 VL6
2490.60
-581.35
134
ROW2
3353.00
587.83
35 VSS
-1257.03
-581.35
85 VF
2566.73
-581.35
135
ROW1
3292.80
587.83
36 VSS
-1180.73
-581.35
86 VDD
2651.78
-581.35
136
ROW0
3232.60
587.83
37 VSS1
-1095.68
-581.35 87 M/
S
2728.08 -581.35 137 ICONS 3172.40 587.83
38 VSS1
-1019.38
-581.35 88 CLS
2804.38
-581.35
138 SEG0
3112.20
587.83
39 VSS1
-943.08
-581.35 89 VSS
2880.68
-581.35
139 SEG1
3052.00
587.83
40 VSS1
-866.78
-581.35 90 C68/
80
2956.98 -581.35 140
SEG2 2991.80 587.83
41 VSS1
-790.48
-581.35 91 P/
S
3033.28 -581.35 141
SEG3 2931.60 587.83
42 VEE
-714.18
-581.35
92 VDD
3109.58
-581.35
142
SEG4
2871.40
587.83
43 VEE
-637.88
-581.35
93 C0
3185.88
-581.35
143
SEG5
2811.20
587.83
44 VEE
-561.58
-581.35
94 VSS
3262.18
-581.35
144
SEG6
2751.00
587.83
45 VEE
-485.28
-581.35
95 C1
3338.48
-581.35
145
SEG7
2690.80
587.83
46 VEE
-408.98
-581.35
96 VDD
3414.78
-581.35
146
SEG8
2630.60
587.83
47 VEE
-332.68
-581.35
97 IRS
3491.08
-581.35
147
SEG9
2570.40
587.83
48 TEST2
-256.38
-581.35 98 VSS
3567.38
-581.35 148 SEG10
2510.20
587.83
49 C3N
-180.08
-581.35
99
SPI
3643.68 -581.35 149 SEG11 2450.00 587.83
50 C3N
-103.78
-581.35
100 T0
3723.65
-581.35
150
SEG12
2389.80
587.83
Solomon Systech
Oct 2003
P 6/43
Rev 1.1
SSD1818A
Pad #
Signal X-pos
Y-pos
Pad #
Signal X-pos
Y-pos
Pad #
Signal
X-pos
Y-pos
151 SEG13
2329.60
587.83 201 SEG63 -680.40 587.83
251 ROW41
-3690.40 587.83
152 SEG14
2269.40
587.83 202 SEG64 -740.60 587.83
252 ROW42
-3750.60 587.83
153 SEG15
2209.20
587.83 203 SEG65 -800.80 587.83
253 ROW43
-3810.80 587.83
154 SEG16
2149.00
587.83 204 SEG66 -861.00 587.83
254 NC -4178.48 663.25
155 SEG17
2088.80
587.83 205 SEG67 -921.20 587.83
255 ROW44
-4178.48 609.18
156 SEG18
2028.60
587.83 206 SEG68 -981.40 587.83
256 ROW45
-4178.48 548.98
157 SEG19
1968.40
587.83 207 SEG69 -1041.60 587.83
257 ROW46
-4178.48 488.78
158 SEG20
1908.20
587.83 208 SEG70 -1101.80 587.83
258 ROW47
-4178.48 428.58
159 SEG21
1848.00
587.83 209 SEG71 -1162.00 587.83
259 ROW48
-4178.48 368.38
160 SEG22
1787.80
587.83 210 SEG72 -1222.20 587.83
260 ROW49
-4178.48 308.18
161 SEG23
1727.60
587.83 211 SEG73 -1282.40 587.83
261 ROW50
-4178.48 247.98
162 SEG24
1667.40
587.83 212 SEG74 -1342.60 587.83
262 ROW51
-4178.48 187.78
163 SEG25
1607.20
587.83 213 SEG75 -1402.80 587.83
263 ROW52
-4178.48 127.58
164 SEG26
1547.00
587.83 214 SEG76 -1463.00 587.83
264 ROW53
-4178.48 67.38
165 SEG27
1486.80
587.83 215 SEG77 -1523.20 587.83
265 ROW54
-4178.48
7.18
166 SEG28
1426.60
587.83 216 SEG78 -1583.40 587.83
266 ROW55
-4178.48 -53.03
167 SEG29
1366.40
587.83 217 SEG79 -1643.60 587.83
267 ROW56
-4178.48 -113.23
168 SEG30
1306.20
587.83 218 SEG80 -1703.80 587.83
268 ROW57
-4178.48 -173.43
169 SEG31
1246.00
587.83 219 SEG81 -1764.00 587.83
269 ROW58
-4178.48 -233.63
170 SEG32
1185.80
587.83 220 SEG82 -1824.20 587.83
270 ROW59
-4178.48 -293.83
171 SEG33
1125.60
587.83 221 SEG83 -1884.40 587.83
271 ROW60
-4178.48 -354.03
172 SEG34
1065.40
587.83 222 SEG84 -1944.60 587.83
272 ROW61
-4178.48 -414.23
173 SEG35
1005.20
587.83 223 SEG85 -2004.80 587.83
273 ROW62
-4178.48 -474.43
174 SEG36
945.00
587.83 224 SEG86 -2065.00 587.83
274 ROW63
-4178.48 -534.63
175 SEG37
884.80
587.83 225 SEG87 -2125.20 587.83
275 ICONS
-4178.48 -594.83
176 SEG38
824.60
587.83 226 SEG88 -2185.40 587.83
276 NC -4178.48 -655.03
177 SEG39
764.40
587.83 227 SEG89 -2245.60 587.83
277 NC -3875.55 149.28
178 SEG40
704.20 587.83 228 SEG90 -2305.80 587.83
179 SEG41
644.00
587.83 229 SEG91 -2366.00 587.83
180 SEG42
583.80
587.83 230 SEG92 -2426.20 587.83
181 SEG43
523.60
587.83 231 SEG93 -2486.40 587.83
182 SEG44
463.40
587.83 232 SEG94 -2546.60 587.83
183 SEG45
403.20
587.83 233 SEG95 -2606.80 587.83
184 SEG46
343.00
587.83 234 SEG96 -2667.00 587.83 Bump Size
185 SEG47
282.80
587.83 235 SEG97 -2727.20 587.83 PAD#
X [um] Y [um]
186 SEG48
222.60
587.83 236 SEG98 -2787.40 587.83 1 102
50.05
50.05
187 SEG49
162.40
587.83 237 SEG99 -2847.60 587.83 103 124
66.675 40.95
188 SEG50
102.20
587.83 238 SEG100 -2907.80 587.83 125
66.675 28.7
189 SEG51 42.00 587.83 239 SEG101 -2968.00 587.83 126 253
40.95
66.675
190 SEG52
-18.20 587.83 240 SEG102 -3028.20 587.83 254
66.675 28.7
191 SEG53
-78.40 587.83 241 SEG103 -3088.40 587.83 255 276
66.675 40.95
192 SEG54
-138.60
587.83 242 ROW32 -3148.60 587.83 277
88.2
88.2
193 SEG55
-198.80
587.83 243 ROW33 -3208.80 587.83
194 SEG56
-259.00
587.83 244 ROW34 -3269.00 587.83
195 SEG57
-319.20
587.83 245 ROW35 -3329.20 587.83
196 SEG58
-379.40
587.83 246 ROW36 -3389.40 587.83
197 SEG59
-439.60
587.83 247 ROW37 -3449.60 587.83
198 SEG60
-499.80
587.83 248 ROW38 -3509.80 587.83
199 SEG61
-560.00
587.83 249 ROW39 -3570.00 587.83
200 SEG62
-620.20
587.83 250 ROW40 -3630.20 587.83
SSD1818A
Rev 1.1
P 7/43
Oct 2003
Solomon Systech
PIN DESCRIPTION
MSTAT
This pin is the static indicator driving output. It is only active in master operation. The frame signal output
pin, M, should be used as the back plane signal for the static indicator. The duration of overlapping can
be programmable. This pin, MSTAT, becomes high impedance if the chip is operating in slave mode.
Please see the Extended Command Table for reference.
M
This pin is the frame signal input/output. In master mode, the pin supplies frame signal to slave devices.
In slave mode, the pin receives frame signal from the master device.
CL
This pin is the system clock input/output. When the internal oscillator is enabled (CLS pin pulled high),
and the master mode is enabled (M/
S pin pulled high), this pin supplies system clock signal to the slave
device. When internal oscillator is disabled and the slave mode is enabled, the pin receives system clock
signal from the master device or external clock source.
DOF
This pin is the display blanking signal control pin. In master mode, this pin supplies "display on" or
"display off" signal (blanking signal) to slave devices. In slave mode, this pin receives "display on" or
"display off" signal from the master device.
1
CS
, CS2
These pins are the chip select inputs. The chip is enabled for MCU communication only when
1
CS
is
pulled low and CS2 is pulled high.
RES
This pin is the reset signal input. Initialization of the chip is started once this pin is pulled low. Minimum
pulse width for completing the reset procedure is 5 - 10us.
D/
C
This pin is Data/Command control pin. When the pin is pulled high, the input at D
7
-D
0
is treated as display
data. When the pin is pulled low, the input at D
7
-D
0
will be transferred to the command register. For
detailed relationship with other MCU interface signals, please refer to the Timing Characteristics
Diagrams.
R/ W ( WR )
This pin is MCU interface input. When 6800 interface mode is selected, this pin will be used as
Read/Write (R/ W ) selection input. Read mode will be carried out when this pin is pulled high and write
mode when this pin is pulled low.
When 8080 interface mode is selected, this pin will be the Write ( WR ) input. Data write operation is
initiated when this pin is pulled low and the chip is selected.
E( RD )
This pin is MCU interface input. When 6800 interface mode is selected, this pin will be used as the
Enable (E) signal. Read/ write operation is initiated when this pin is pulled high and the chip is selected.
When 8080 interface mode is selected, this pin receives the Read ( RD ) signal. Data read operation is
initiated when this pin is pulled low and the chip is selected.
Solomon Systech
Oct 2003
P 8/43
Rev 1.1
SSD1818A
D
7
-D
0
These pins are the 8-bit bi-directional data bus in parallel interface mode. D
7
is the MSB while D
0
is the
LSB. When serial mode is selected, D
7
is the serial data input (SDA) and D
6
is the serial clock input (SCK).
V
DD
These pins are the Chip's Power Supply pins. These pins are also act as the reference for the DC-DC
Converter output and the LCD driving voltages.
V
SS
These pins are the grounding of the chip. They are also act as the reference for the logic pins.
V
SS1
These pins are the inputs for internal DC-DC converter. The voltage of generated, V
EE
, equals to the
multiple factors times the potential different between these pins, V
SS1
, and V
DD
. The multiple factors, 2X,
3X, 4X or 5X are selected by different connections of the external capacitors. All voltage levels are
referenced to V
DD
.
Note: the potential of Vss
1
at this input pin must lower than or equal to V
SS
.
V
EE
This is the most negative voltage supply pin of the chip. It can be supplied externally or generated by the
internal DC-DC converter. The internal DC-DC converter is turned on when the internal voltage booster
option is enabled. Please refer to the Set Power Control Register command for detail description.
When using internal DC-DC converter as voltage generator, voltage at this pin is used for internal
referencing only. It CANNOT be used for driving external circuitry.
C
1P
, C
1N
, C
2N
, C
2P
C
3N
and C
4N
When internal DC-DC voltage converter is used, external capacitor(s) is/are connected between these
pins. Different connections result in different DC-DC converter multiple factors, for example, 2X, 3X, 4X or
5X. For detailed connections, please refer to the voltage converter section in the functional block
description.
V
L2
, V
L3
, V
L4
and V
L5
These pins are outputs with voltage levels equal to the LCD driving voltage. All these voltage levels are
referenced to V
DD
. The voltage levels can be supplied externally or generated by the internal bias divider.
The bias divider is turned on when the output op-amp buffers are enabled. Please refer to the Set Power
Control Register command for detail description.
The voltage potential relationship of these pins are given as:
V
DD
> V
L2
> V
L3
> V
L4
> V
L5
> V
L6
In addition, assume the bias factor is known as a,
VL2 - VDD = 1/a * (VL6 - VDD)
VL3 - VDD = 2/a * (VL6 - VDD)
VL4 - VDD = (a-2)/a * (VL6 - VDD)
VL5 - VDD = (a-1)/a * (VL6 - VDD)
V
L6
This pin outputs the most negative LCD driving voltage level. The V
L6
can be supplied externally or
generated by the internal regulator. Please refer to the Set Power Control Register command for detail
description.
SSD1818A
Rev 1.1
P 9/43
Oct 2003
Solomon Systech
M/ S
This pin is the master/slave mode selection input. When this pin is pulled high, master mode is selected.
CL, M, MSTAT and DOF signals will be the output pins for slave devices.
When this pin is pulled low, slave mode is selected. CL, M, DOF are input pins getting signal from master
device. The state of MSTAT will be high impedance.
V
F
This pin is the input of the built-in voltage regulator for generating V
L6
. When external resistor network is
selected (IRS pulled low) to generate the LCD driving level, V
L6
, two external resistors should be added.
R
1
should be connected between V
DD
and V
F
. R
2
should be connected between V
F
and V
L6.
CLS
This pin is the internal clock enable pin. When this pin is pulled high, internal clock is enabled.
The internal clock will be disabled when CLS is pulled low. Under such circumstances, an external clock
source must be fed into the CL pin.
C68/
80
This pin is the MCU parallel interface selection input. When the pin is pulled high, 6800 series interface is
selected. When the pin is pulled low, 8080 series interface is selected.
If Serial Interface is selected (P/ S pulled low), the setting of this pin is ignored. The C68
/
80
pin must be
connected to a known logic state (either high or low).
P/ S
This pin is the serial/parallel interface selection input. When this pin is pulled high, parallel interface mode
is selected. When this pin is pulled low, serial interface will be selected.
Note1: For serial mode, D0, D1, D2, D3, D4, D5, R/ W ( WR ), E/(
RD
) are recommended to connect to
Vss.
Note2: Read back operation is only available in parallel mode.
C1, C0
These pins are the Chip Mode Selection input. The chip mode is determined by multiplex ratio. Altogether
there are four chip modes. Please see the following list for reference.
C1 C0 Chip
Mode
0
0
48 MUX Mode
0
1
54 MUX Mode
1
0
32 MUX Mode
1
1
64 MUX Mode
IRS
This is the input pin to enable the internal resistors network for the voltage regulator. When this pin is
pulled high, the internal feedback resistors of the internal regulator for generating V
L6
will be enabled.
When it is pulled low, external resistors, R
1
should be connected to V
DD
and V
F
. R
2
should be connected
between V
F
and V
L6
, respectively.
SPI
This is the input pin to enable the circuitry for providing serial interface. This pin must be connected to low
at any circumstances. When the SPI pin and the P/ S , selection input are both pulled low, the serial
Solomon Systech
Oct 2003
P 10/43 Rev 1.1
SSD1818A
interface is enabled. When the SPI pin is pulled low and the P/ S selection input is pulled high, the
parallel interface is enabled.
NC/TEST0 TEST2/T0 T2
These are the No Connection pins. These pins should be left open individually.
Remarks: These pins should not be connected together.
ROW0 - ROW63
These pins provide the Common driving signals to the LCD panel. Please refer to the Table 3 on Page 11
for the COM signal mapping.
SEG0 - SEG103
These pins provide the LCD segment driving signals. The output voltage level of these pins is V
DD
during
sleep mode or standby mode.
ICONS
There are two ICONS pins (pin137 and 275) on the chip. Both pins output exactly the same signal. The
reason for duplicating these pins is to enhance the flexibility of the LCD layout.
SSD1818A
Rev 1.1
P 11/43 Oct 2003
Solomon Systech
Table 3 Example of ROW pin assignment for programmable MUX of SSD1818A
48 MUX Mode
54 MUX Mode
32 MUX Mode
64 MUX Mode
ROW0
COM0 COM0 COM0 COM0
ROW1 COM1 COM1 COM1 COM1
ROW2 COM2 COM2 COM2 COM2
ROW3 COM3 COM3 COM3 COM3
ROW4 COM4 COM4 COM4 COM4
ROW5 COM5 COM5 COM5 COM5
ROW6 COM6 COM6 COM6 COM6
ROW7 COM7 COM7 COM7 COM7
ROW8 COM8 COM8 COM8 COM8
ROW9 COM9 COM9 COM9 COM9
ROW10 COM10 COM10 COM10 COM10
ROW11 COM11 COM11 COM11 COM11
ROW12 COM12 COM12 COM12 COM12
ROW13 COM13 COM13 COM13 COM13
ROW14 COM14 COM14 COM14 COM14
ROW15 COM15 COM15 COM15 COM15
ROW16
COM16
COM16 NC COM16
ROW17
COM17
COM17 NC COM17
ROW18
COM18
COM18 NC COM18
ROW19
COM19
COM19 NC COM19
ROW20
COM20
COM20 NC COM20
ROW21
COM21
COM21 NC COM21
ROW22
COM22
COM22 NC COM22
ROW23
COM23
COM23 NC COM23
ROW24 NC COM24 NC COM24
ROW25 NC COM25 NC COM25
ROW26 NC COM26 NC COM26
ROW27
NC NC NC
COM27
ROW28
NC NC NC
COM28
ROW29
NC NC NC
COM29
ROW30
NC NC NC
COM30
ROW31
NC NC NC
COM31
ROW32 COM24 COM27 COM16 COM32
ROW33 COM25 COM28 COM17 COM33
ROW34 COM26 COM29 COM18 COM34
ROW35 COM27 COM30 COM19 COM35
ROW36 COM28 COM31 COM20 COM36
ROW37 COM29 COM32 COM21 COM37
ROW38 COM30 COM33 COM22 COM38
ROW39 COM31 COM34 COM23 COM39
ROW40 COM32 COM35 COM24 COM40
ROW41 COM33 COM36 COM25 COM41
ROW42 COM34 COM37 COM26 COM42
ROW43 COM35 COM38 COM27 COM43
ROW44 COM36 COM39 COM28 COM44
ROW45 COM37 COM40 COM29 COM45
ROW46 COM38 COM41 COM30 COM46
ROW47 COM39 COM42 COM31 COM47
ROW48
COM40
COM43 NC COM48
ROW49
COM41
COM44 NC COM49
ROW50
COM42
COM45 NC COM50
ROW51
COM43
COM46 NC COM51
ROW52
COM44
COM47 NC COM52
ROW53
COM45
COM48 NC COM53
ROW54
COM46
COM49 NC COM54
ROW55
COM47
COM50 NC COM55
ROW56 NC COM51 NC COM56
ROW57 NC COM52 NC COM57
ROW58 NC COM53 NC COM58
ROW59
NC NC NC
COM59
ROW60
NC NC NC
COM60
ROW61
NC NC NC
COM61
ROW62
NC NC NC
COM62
ROW63
NC NC NC
COM63
Note: X-Row pin will output non-selected COM signal
Solomon Systech
Oct 2003
P 12/43 Rev 1.1
SSD1818A
FUNCTIONAL BLOCK DESCRIPTIONS
Command Decoder and Command Interface
This module determines whether the input signal is interpreted as data or command. Input is directed to
this module based on the input of the D/ C pin.
If the D/
C
pin is high, input is written to Graphic Display Data RAM (GDDRAM). If it is low, the input at
D
7
-D
0
is interpreted as a Command. It will be decoded and written to the corresponding command register.
MPU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins (D
7
-D
0
), R/ W ( WR ), D/ C , E/(
RD
),
1
CS and
CS2.
Read cycle
R/ W ( WR ) input high indicates a read operation from the Graphic Display Data RAM (GDDRAM) or the
status register. In order to match the operating frequency of the GDDRAM with that of the MCU, pipeline
processing is internally performed which requires the insertion of a dummy read before the first actual
display data read. This is shown in Figure 3.
Figure 3 - Display Data Read Back Procedure - Insertion of Dummy Read
Write cycle
R/ W ( WR ) input Low indicates a write operation to Display Data RAM or Internal Command Registers
depending on the
D/
C
input. The E( RD ) input serves as data latch signal (clock) when high, provided that
1
CS is pulled low and the CS2 is pulled high respectively.
Please refer to Figure 9 on Page 34 for Parallel Interface Timing Diagram of 6800-series microprocessors.
MPU Parallel 8080-series interface
The parallel interface consists of 8 bi-directional data pins (D
7
-D
0
), E/(
RD
), R/ W ( WR ), D/ C ,
1
CS and
CS2.
R/W
(WR)
E(RD)
data bus
write column address
dummy read
data read1
data read 2
data read 3
N
n
n+1
n+2
SSD1818A
Rev 1.1
P 13/43 Oct 2003
Solomon Systech
Read cycle
E( RD ) input serves as data read latch signal (clock) when low, provided that
1
CS is pulled low and the
CS2 is pulled high respectively. The D
/
C
signal determines whether the receiving signal is a display data
read or a status register read signal. Similar to 6800-series interface, a dummy read is also required
before the first actual display data read.
Write cycle
R/ W ( WR ) input serves as data write latch signal (clock) when high, provided that
1
CS and CS2 are low
and high respectively. The D
/
C
signal determines whether the receiving signal is a display data write or a
command register write signal.
Please refer to Figure 10 on Page 35 for Parallel Interface Timing Diagram of 8080-series microprocessor.
MPU Serial interface
The serial interface consists of serial clock SCK (D
6
), serial data SDA (D
7
), D
/
C
,
1
CS and CS2. Input to
SDA is shifted into a 8-bit shift register on every rising edge of SCK in the order of D
7
, D
6
,... D
0
. D
/
C
is
sampled on every eighth clock to determine whether the data byte in the shift register is written to the
Display Data RAM or command register at the same clock.
Oscillator Circuit
This module is an On-Chip low power RC oscillator circuitry (Figure 4). The oscillator generates the clock
for the DC-DC voltage converter. This clock is also used in the Display Timing Generator.
enable
Oscillation Circuit
enable
Buffer
Internal resistor
OSC2
OSC1
Oscillator
enable
(CL)
Figure 4 - Oscillator
LCD Driving Voltage Generator and Regulator
This module generates the LCD voltage required for display driving output. With reference to V
DD
, it takes
a single supply input, V
SS
, and generates necessary voltage levels. This block consists of:
1. 2X, 3X, 4X and 5X DC-DC voltage converter
The built-in DC-DC voltage converter is used to generate the negative voltage with reference to VDD from
the voltage input (VSS1). For SSD1818A, it is possible to produce 2X, 3X, 4X or 5X boosting from the
potential different between V
SS1
- V
DD
. Detailed configurations of the DC-DC converter for different
boosting multiples are given in Figure 5.
Solomon Systech
Oct 2003
P 14/43 Rev 1.1
SSD1818A
Figure 5 - DC-DC Converter Configurations
2. Voltage Regulator (Voltages referenced to V
DD
)
Internal (IRS pin = H) feedback gain can control the LCD driving contrast curves.
If internal resistor network is enabled, eight settings can be selected through software command.
If external control is selected, external resistors are connected between V
DD
and V
F
(R1), and between V
F
and V
L6
(R2).
3. Contrast Control (Voltage referenced to V
DD
)
Software control of the 64-contrast voltage levels at each voltage regulator feedback gain. The
equation of calculating the LCD driving voltage is given as:
V
L6
V
DD
= Gain * [1 + (18 +
)] * V
ref
81
stands for the contrast set (0 to 63)
SSD1818A
5X Boosting Configuration
V
SS1
V
EE
C
3N
C
1P
C
1N
C
2N
C
2P
C
4N
C1
+
+
+
C1
C1
C1
+
+
C1
4X Boosting Configuration
V
SS1
V
EE
C
3N
C
1P
C
1N
C
2N
C
2P
C
4N
C1
+
+
+ C1
C1 +
SSD1818A
3X Boosting Configuration
V
SS1
V
EE
C
3N
C
1P
C
1N
C
2N
C
2P
C
4N
C1
+
+
C1
C1
+
SSD1818A
2X Boosting Configuration
V
SS1
V
EE
C
3N
C
1P
C
1N
C
2N
C
2P
C
4N
C1
+
+
C1
SSD1818A
Remarks:
1. C1= 0.47 4.7uF
2. Boosting input from V
SS1
3. V
SS1
should be lower potential than or equal to V
SS
4. All voltages are referenced to V
DD
C1
SSD1818A
Rev 1.1
P 15/43 Oct 2003
Solomon Systech
Gain = (1 + Rb/Ra), the reference value is shown in table 5.
Register ratio
D2 D1 D0
Thermal Gradient
= -0.07 %/
o
C
0 0 0
2.92
0 0 1
3.40
0 1 0
3.89
0 1 1
4.37
1 0 0
4.85
1 0 1
5.23
1 1 0
5.72
1 1 1
6.19
Gain value at different register ratio and thermal gradient settings
V
ref
is a fixed ICinternal voltage supply and its voltage at room temperature (25
o
C) is shown in table 6 for
reference.
Type Thermal
Gradient
V
ref
TC 0
-0.07 %/
o
C -1.08V
TC 2
-0.13 %/
o
C -1.12V
TC 4
-0.26 %/
o
C -1.09V
TC 7
-0.29 %/
o
C -1.10V
External resistor
gain mode [Gain =
5.00] @ TC0
-0.07 %/
o
C -1.08V
V
ref
values at different thermal gradient settings
The voltage regulator output for different gain/contrast settings is shown in figure 6.
Figure 6 Voltage Regulator Output for different Gain/Contrast Settings
Solomon Systech
Oct 2003
P 16/43 Rev 1.1
SSD1818A
SSD1815B
V
DD
V
L2
V
L3
V
L4
V
L5
V
L6
R3
R1
R2
R4
+
V
DD
C5
+ C4
+ C3
+ C2
+ C1
Remark: 1. C1 ~ C5 = 0.01 ~ 0. 47uF
2. R1 ~ R4 = 100k~ 1M
SSD1818A
4. Bias Ratio Selection circuitry
The bias ratios can be software selected from 1/4, 1/5, 1/6, 1/7, 1/8 and 1/9.
Since there will be slightly different in command pattern for different MUX, please refer to Command
Descriptions section of this data sheet. If the output op-amp buffer option in Set Power Control Register
command is enabled, this circuit block will divide the regulator output (V
L6
) to give the LCD driving levels
(V
L2
~ V
L5
). A low power consumption circuit design in this bias divider saves most of the display current
comparing to the traditional design. Stabilizing Capacitors (0.1uF ~ 0.47uF) are required to be connected
between these voltage level pins (V
L2
~ V
L5
) and (V
DD
). If the LCD panel loading is heavy, four additional
resistors are suggested to add to the application circuit as follows:
5. Self adjust temperature compensation circuitry
This block provides 4 different compensation settings to satisfy various liquid crystal temperature grades
by software control. Default temperature coefficient (TC) setting is TC0.
Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is
104 x 65 = 6760 bits. Table 4 on Page 17 is a description of the GDDRAM address map.
For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by
software.
For vertical scrolling of the display, an internal register storing display start line can be set to control the
portion of the RAM data to be mapped to the display. Table 4 on Page 17 shows the case in which the
display start line register is set to 38h.
For those GDDRAM out of the display common range, they could still be accessed, for either preparation
of vertical scrolling data or even for the system usage.
Remark: 1. C1 ~ C5 = 0.1uF ~ 0.47uF
2. R1 ~ R4 = 100k ~1M
SSD1818A
Rev 1.1
P 17/43 Oct 2003
Solomon Systech
Normal
00h
01h
02h
03h
64h
65h
66h
67h
Remapped
67h
66h
65h
64h
03h
02h
01h
00h
00h
D0 (LSB)
8
39
8
45
8
23
8
55
01h
D1
9
38
9
44
9
22
9
54
02h
D2
10
37
10
43
10
21
10
53
03h
D3
11
36
11
42
11
20
11
52
04h
D4
12
35
12
41
12
19
12
51
05h
D5
13
34
13
40
13
18
13
50
06h
D6
14
33
14
39
14
17
14
49
07h
D7 (MSB)
15
32
15
38
15
16
15
48
08h
D0 (LSB)
16
31
16
37
16
15
16
47
09h
D1
17
30
17
36
17
14
17
46
0Ah
D2
18
29
18
35
18
13
18
45
0Bh
D3
19
28
19
34
19
12
19
44
0Ch
D4
20
27
20
33
20
11
20
43
0Dh
D5
21
26
21
32
21
10
21
42
0Eh
D6
22
25
22
31
22
9
22
41
0Fh
D7 (MSB)
23
24
23
30
23
8
23
40
10h
D0 (LSB)
24
23
24
29
24
7
24
39
11h
D1
25
22
25
28
25
6
25
38
12h
D2
26
21
26
27
26
5
26
37
13h
D3
27
20
27
26
27
4
27
36
14h
D4
28
19
28
25
28
3
28
35
15h
D5
29
18
29
24
29
2
29
34
16h
D6
30
17
30
23
30
1
30
33
17h
D7 (MSB)
31
16
31
22
31
0
31
32
18h
D0 (LSB)
32
15
32
21
X
X
32
31
19h
D1
33
14
33
20
X
X
33
30
1Ah
D2
34
13
34
19
X
X
34
29
1Bh
D3
35
12
35
18
X
X
35
28
1Ch
D4
36
11
36
17
X
X
36
27
1Dh
D5
37
10
37
16
X
X
37
26
1Eh
D6
38
9
38
15
X
X
38
25
1Fh
D7 (MSB)
39
8
39
14
X
X
39
24
20h
D0 (LSB)
40
7
40
13
X
X
40
23
21h
D1
41
6
41
12
X
X
41
22
22h
D2
42
5
42
11
X
X
42
21
23h
D3
43
4
43
10
X
X
43
20
24h
D4
44
3
44
9
X
X
44
19
25h
D5
45
2
45
8
X
X
45
18
26h
D6
46
1
46
7
X
X
46
17
27h
D7 (MSB)
47
0
47
6
X
X
47
16
28h
D0 (LSB)
X
X
48
5
X
X
48
15
29h
D1
X
X
49
4
X
X
49
14
2Ah
D2
X
X
50
3
X
X
50
13
2Bh
D3
X
X
51
2
X
X
51
12
2Ch
D4
X
X
52
1
X
X
52
11
2Dh
D5
X
X
53
0
X
X
53
10
2Eh
D6
X
X
X
X
X
X
54
9
2Fh
D7 (MSB)
X
X
X
X
X
X
55
8
30h
D0 (LSB)
X
X
X
X
X
X
56
7
31h
D1
X
X
X
X
X
X
57
6
32h
D2
X
X
X
X
X
X
58
5
33h
D3
X
X
X
X
X
X
59
4
34h
D4
X
X
X
X
X
X
60
3
35h
D5
X
X
X
X
X
X
61
2
36h
D6
X
X
X
X
X
X
62
1
37h
D7 (MSB)
X
X
X
X
X
X
63
0
38h
D0 (LSB)
0
47
0
53
0
31
0
63
39h
D1
1
46
1
52
1
30
1
62
3Ah
D2
2
45
2
51
2
29
2
61
3Bh
D3
3
44
3
50
3
28
3
60
3Ch
D4
4
43
4
49
4
27
4
59
3Dh
D5
5
42
5
48
5
26
5
58
3Eh
D6
6
41
6
47
6
25
6
57
3Fh
D7 (MSB)
7
40
7
46
7
24
7
56
Page 8
D0 (LSB)
ICONS
ICONS
ICONS
ICONS
ICONS
ICONS
ICONS
ICONS
Segment Pins
0
1
2
3
100
101
102
103
Page 6
Page 7
Normal
Remapped
Page 2
Page 3
Page 4
Page 5
Page 0
Page 1
Normal
Remapped
Normal
Remapped
RAM
Row
RAM
Column
Normal
Remapped
Common Pins
48 MUX Mode
54 MUX Mode
32 MUX Mode
64 MUX Mode
Remarks : DB0 DB7 represent the data bit of the GDDRAM
Table 4 - Graphic Display Data RAM (GDDRAM) Address Map with Display Start Line set to 38h
Solomon Systech
Oct 2003
P 18/43 Rev 1.1
SSD1818A
Reset Circuit
This block includes Power On Reset (POR) circuitry and the hardware reset pin,
RES
. The POR and
Hardware reset performs the same reset function. Once
RES
receives a reset pulse, all internal circuitry
will start to initialize. Minimum pulse width the reset sequence is 5 - 10us. Status of the chip after reset is
given by:
Display is turned OFF
Default Display Mode: 104 x 64 + 1 Icon Line
Normal segment and display data column address mapping (Seg0 mapped to Row address 00h)
Read-modify-write mode is OFF
Power control register is set to 000b
Shift register data clear in serial interface
Bias ratio is set to default: 1/9
Static indicator is turned OFF
Display start line is set to GDDRAM column 0
Column address counter is set to 00h
Page address is set to 0
Normal scan direction of the COM outputs
Contrast control register is set to 20h
Test mode is turned OFF
Temperature Coefficient is set to TC0
Note: Please find more explanation in the Applications Note attached at the back of the specification.
Display Data Latch
This block is a series of latches carrying the display signal information. These latches hold the data,
which will be fed to the HV Buffer Cell and Level Selector to output the required voltage level.
64 MUX: 104 + 65 = 169
HV Buffer Cell (Level Shifter)
HV Buffer Cell works as a level shifter which translates the low voltage output signal to the required
driving voltage. The output is shifted out with reference an internal FRM clock which comes from the
Display Timing Generator. The level selector, which is synchronized with the internal M signal, gives the
voltage levels.
Level Selector
Level Selector is a control of the display synchronization. Display voltage levels can be separated into two
sets and used with different cycles. Synchronization is important since it selects the required LCD voltage
level to the HV Buffer Cell, which in turn outputs the COM or SEG LCD waveform.
SSD1818A
Rev 1.1
P 19/43 Oct 2003
Solomon Systech
LCD Panel Driving Waveform
Figure 7 is an example of how the Common and Segment drivers may be connected to a LCD panel. The
waveforms illustrate the desired multiplex scheme.
COM1
COM2
COM3
COM4
COM5
COM6
COM7
E
G
1
E
G
2
E
G
3
E
G
4
COM0
E
G
0
TIME SLOT
COM0
COM1
SEG0
SEG1
M
V
DD
V
L2
V
L3
V
L4
V
L5
V
L6
V
DD
V
L2
V
L3
V
L4
V
L5
V
L6
V
DD
V
L2
V
L3
V
L4
V
L5
V
L6
V
DD
V
L2
V
L3
V
L4
V
L5
V
L6
* Note 1: N+1 is the number of multiplex ratio including Icon.
1
2
3
4
5
6
7
8
9
. . .
N+1
*
1
2
3
4
5
6
7 8 9 . . . N+1
*
1 2 3 4 5 6 7 8 9 . .
N+1
*
1 2 3 4 5 6 7 8
9
. . .
N+1
*
Figure 7 - LCD Driving Waveform for Displaying "0"
Solomon Systech
Oct 2003
P 20/43 Rev 1.1
SSD1818A
COMMAND TABLE
Bit Pattern
Command
Description
0000X
3
X
2
X
1
X
0
Set Lower Column Address
Set the lower nibble of the column address register
using X
3
X
2
X
1
X
0
as data bits. The lower nibble of
column address is reset to 0000b after POR
0001X
3
X
2
X
1
X
0
Set Higher Column Address
Set the higher nibble of the column address register
using X
3
X
2
X
1
X
0
as data bits. The higher nibble of
column address is reset to 0000b after POR.
00100X
2
X
1
X
0
Set Internal Regulator Resistor
Ratio
Feedback gain of the internal regulator generating
VL6 increases as X
2
X
1
X
0
increased from 000b to
111b. After POR, X
2
X
1
X
0
= 100b
00101X
2
X
1
X
0
Set Power Control Register
X
0
=0: turns off the output op-amp buffer (POR)
X
0
=1: turns on the output op-amp buffer
X
1
=0: turns off the internal regulator (POR)
X
1
=1: turns on the internal regulator
X
2
=0: turns off the internal voltage booster (POR)
X
2
=1: turns on the internal voltage booster
01X
5
X
4
X
3
X
2
X
1
X
0
Set Display Start Line
Set GDDRAM display start line register from 0-63
using X
5
X
4
X
3
X
2
X
1
X
0
.
Display start line register is reset to 000000 after
POR.
10000001
* * X
5
X
4
X
3
X
2
X
1
X
0
Set Contrast Control Register
Select contrast level from 64 contrast steps.
Contrast increases (VL6 decreases) as
X
5
X
4
X
3
X
2
X
1
X
0
is increased from 000000b to
111111b. X
5
X
4
X
3
X
2
X
1
X
0
= 100000b after POR
1010000X
0
Set Segment Re-map
X
0
=0: column address 00h is mapped to SEG0
(POR)
X
0
=1: column address 67h is mapped to SEG0
Refer to Table 4 on page 17 for example.
1010001X
0
Set LCD Bias
X
0
=0: POR default bias
48 MUX Mode: 1/8
54 MUX Mode: 1/8.4
32 MUX Mode: 1/6
64 MUX Mode: 1/9
X
0
=1: alternate bias
48 MUX Mode: 1/6
54 MUX Mode: 1/6
32 MUX Mode: 1/5
64 MUX Mode: 1/7
For other bias ratio settings, see "Set 1/4 Bias Ratio"
and "Set Bias Ratio" in Extended Command Set.
1010010X
0
Set Entire Display On/Off
X
0
=0: normal display (POR)
X
0
=1: entire display on
1010011X
0
Set Normal/Reverse Display
X
0
=0: normal display (POR)
X
0
=1: reverse display
1010111X
0
Set Display On/Off
X
0
=0: turns off LCD panel (POR)
X
0
=1: turns on LCD panel
1011X
3
X
2
X
1
X
0
Set Page Address
Set GDDRAM Page Address (0-8) for read/write
using X
3
X
2
X
1
X
0
1100X
3
* * *
Set COM Output Scan Direction
X
3
=0: normal mode (POR)
X
3
=1: remapped mode,
COM0 to COM [N-1] becomes COM [N-1] to COM0
when Multiplex ratio is equal to N.
See Table 4 on page 17 for detail mapping.
11100000
Set Read-Modify-Write Mode
Read-Modify-Write mode will be entered in which
the column address will not be increased during
display data read. After POR, Read-modify-write
mode is turned OFF.
11100010
Software Reset
Initialize internal status registers
SSD1818A
Rev 1.1
P 21/43 Oct 2003
Solomon Systech
11101110
Set End of Read-Modify-Write
Mode
Exit Read-Modify-Write mode. RAM Column
address before entering the mode will be restored.
After POR, Read-modify-write mode is OFF.
1010110X
0
* * * * * * X
1
X
0
Set Indicator On/Off
Indicator Display Mode
This second byte command is required ONLY when
"Set Indicator On" command is sent.
X
0
= 0: indicator off (POR, second command byte is
not required)
X
0
= 1: indicator on (second command byte
required)
X
1
X
0
= 00: indicator off
X
1
X
0
= 01: indicator on and blinking at ~1 second
interval
X
1
X
0
= 10: indicator on and blinking at ~1/2 second
interval
X
1
X
0
= 11: indicator on constantly
11100011
NOP
Command result in No Operation
11110000
Test Mode Reset
Reserved for IC testing. Do NOT use
1111 * * * *
Set Test Mode
Reserved for IC testing. Do NOT use.
10101110
10100101
Set Power Save Mode
(Standby or Sleep) Standby or sleep mode will be
entered using compound commands.
Issue compound commands "Set Display Off"
followed by "Set Entire Display On".
Table 5 - Write Command Table (
D/ C
=0, R/ W ( WR )=0,
E( RD )
=1)
Note: " * " stands for don't care bit
Solomon Systech
Oct 2003
P 22/43 Rev 1.1
SSD1818A
Bit Pattern
Command
Description
10101000
00X
5
X
4
X
3
X
2
X
1
X
0
Set Multiplex Ratio
To select multiplex ratio N from 2 to the maximum
multiplex ratio (POR value) for each member
(including icon line).
Max. MUX ratio:
64 MUX: 65
N = X
5
X
4
X
3
X
2
X
1
X
0
+ 2,
e.g. N = 001111b + 2 = 17
10101001
X
7
X
6
X
5
X
4
X
3
X
2
X
1
X
0
Set Bias Ratio (X
1
X
0
)
Set TC Value (X
4
X
3
X
2
)
Modify Osc. Freq. (X
7
X
6
X
5
)
For 64 MUX Mode
X
1
X
0
=
00(POR) 01 10 11
1/9 or 1/7 1/5 1/6 1/8
For 54 MUX Mode
X
1
X
0
=
00(POR) 01 10 11
1/8.4 or 1/6 1/5 1/6 1/8
For 48 MUX Mode
X
1
X
0
=
00(POR) 01 10 11
1/8 or 1/6 1/5 1/6 1/8
For 32 MUX Mode
X
1
X
0
=
00(POR) 01 10 11
1/6 or 1/5 1/5 1/6 1/8
X
4
X
3
X
2
= 000: (TC0) Typ. 0.07
X
4
X
3
X
2
= 010: (TC2) Typ. 0.13
X
4
X
3
X
2
= 100: (TC4) Typ. 0.26
X
4
X
3
X
2
= 111: (TC7) Typ. 0.29
X
4
X
3
X
2
= 001, 011, 101, 110: Reserved
Increase the value of X
7
X
6
X
5
will increase the
oscillator frequency and vice versa.
Default Mode:
X
7
X
6
X
5
= 011
(POR for 48 MUX Mode, 54 MUX Mode) :
Typ. 31.5kHz
X
7
X
6
X
5
= 011
(POR for 32 MUX Mode, 64 MUX Mode) :
Typ. 18.7Hz
Remarks: By software program the multiplex ratio,
the typical oscillator frequency is listed above.
1010101X
0
Set 1/4 Bias Ratio
X
0
= 0: use normal setting (POR)
X
0
= 1: fixed at 1/4 bias regardless of other bias
setting commands
1101000X
0
Set Smart Icon Mode
Smart icon mode used for low power application.
X
0
= 0: smart icon mode disable (POR)
X
0
= 1: smart icon mode enable
11010010
0X
6
X
5
* * * * *
Set Phases of Smart Icon Mode
The contrast level of the smart icon is controlled by
4 phases. The more the total phases, the lower the
contrast level.
X
6
X
5
= 00: 5 phases
X
6
X
5
= 01: 7 phases (POR)
X
6
X
5
= 10: 9 phases
X
6
X
5
= 11: 16 phases
SSD1818A
Rev 1.1
P 23/43 Oct 2003
Solomon Systech
11010100
00X
5
X
4
0000
Set Total Frame Phases of Static
Icon
The On/Off of the Static Icon is given by 3 phases /
1 phase overlapping of the M and MSTAT signals.
This command set total phases of the M/MSTAT
signals for each frame.
The more the total phases, the lower the contrast
level.
X
5
X
4
= 00: 5 phases
X
5
X
4
= 01: 7 phases
X
5
X
4
= 10: 9 phases (POR)
X
5
X
4
= 11: 16 phases
11010011
00X
5
X
4
X
3
X
2
X
1
X
0
Set Display Offset
After POR, X
5
X
4
X
3
X
2
X
1
X
0
= 0
After setting MUX ratio less than default value, data
will be displayed at Center of display matrix.
To move display towards Row 0 by L, X
5
X
4
X
3
X
2
X
1
X
0
= L
To move display away from Row 0 by L,
X
5
X
4
X
3
X
2
X
1
X
0
= 64-L
Note: max. value of L = (POR default MUX ratio
display MUX)/2
11010110
001111X
1
X
0
Enable Band Gap Reference
Circuit
X1X0 =
00 01(POR) 10 11
100 ms 200 ms 400 ms 800 ms
Approx. band gap clock period
Recommendation: set the band gap clock period to
approx. 200ms
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Status Register Read
D
7
=0:
indicates the driver is ready for command.
D
7
=1:
indicates the driver is Busy.
D
6
=0:
indicates reverse segment mapping with
column address.
D
6
=1:
indicates normal segment mapping with
column address.
D
5
=0:
indicates the display is ON.
D
5
=1:
indicates the display is OFF.
D
4
=0:
initialization is completed.
D
4
=1:
initialization process is in progress after
RES or software reset.
D
3
D
2
D
1
D
0
= 1001 or 0011, the 4-bit is fixed to either
1001 or 0011 which could be used to identify as
Solomon Systech Device.
Table 6 - Extended Command Table
Note: - " * " stands for don't care bit
- Command patterns other than that given in Command Table and Extended Command Table are prohibited.
Otherwise, unexpected result will occur.
Solomon Systech
Oct 2003
P 24/43 Rev 1.1
SSD1818A
Data Read / Write
To read data from the GDDRAM, input High to R/ W ( WR ) pin and D/
C
pin for 6800-series parallel mode,
input Low to E (
RD
) pin and High to D/
C
pin for 8080-series parallel mode. No data read is provided in
serial interface mode.
In normal data read mode, GDDRAM column address pointer will be increased by one automatically after
each data read. However, no automatic increase will be performed in read-modify-write mode.
Also, a dummy read is required before first valid data is read. See Figure 3 on page 12 in Functional
Block Descriptions section for detail waveform diagram.
To write data to the GDDRAM, input Low to R/ W ( WR ) pin and High to D/
C
pin for both 6800-series and
8080-series parallel mode. For serial interface mode, it is always in write mode. GDDRAM column
address pointer will be increased by one automatically after each data write.
It should be noted that, after the automatic column address increment, the pointer will NOT wrap round to
0. The pointer will exit the memory address space after accessing the last column. Therefore, the pointer
should be re-initialized when progress to another page address
D/ C
R/ W ( WR )
Action
Auto Address Increment
0 0 Write
Command
No
0 1 Read
Status
No
1 0 Write
Data
Yes
1 1 Read
Data
Yes
Table 7 - Automatic Address Increment
SSD1818A
Rev 1.1
P 25/43 Oct 2003
Solomon Systech
COMMAND DESCRIPTIONS
Set Lower Column Address
This command specifies the lower nibble of the 8-bit column address of the display data RAM. The
column address will be increased by each data access after it is pre-set by the MCU.
Set Higher Column Address
This command specifies the higher nibble of the 8-bit column address of the display data RAM. The
column address will be increased by each data access after it is pre-set by the MCU.
Set Internal Regulator Resistors Ratio
This command is to enable any one of the eight internal resistor sets for different regulator gain when
using internal regulator resistor network (IRS pin pulled high). In other words, this command is used to
select which contrast curve from the eight possible selections. Please refer to Functional Block
Descriptions section for detail calculation of the LCD driving voltage.
Set Power Control Register
This command turns on/off the various power circuits associated with the chip. There are three related
power sub-circuits could be turned on/off by this command.
Internal voltage booster is used to generate the negative voltage supply (V
EE
) from the voltage input (V
SS1
- V
DD
). An external negative power supply is required if this option is turned off.
Internal regulator is used to generate the LCD driving voltage, V
L6
, from the negative power supply, V
EE
.
Output op-amp buffer is the internal divider for dividing the different voltage levels (V
L2
, V
L3
, V
L4
, V
L5
) from
the internal regulator output, V
L6
. External voltage sources should be fed into this driver if this circuit is
turned off.
Set Display Start Line
This command is to set Display Start Line register to determine starting address of display RAM to be
displayed by selecting a value from 0 to 63. With value equals to 0, D0 of Page 0 is mapped to COM0.
With value equals to 1, D1 of Page0 is mapped to COM0 and so on. Display start line values of 0 to 63
are assigned to Page 0 to 7.
Please refer to Table 4 on Page 17 as an example for display start line set to 56 (38h).
Set Contrast Control Register
This command adjusts the contrast of the LCD panel by changing the LCD driving voltage, V
L6
, provided
by the On-Chip power circuits. V
L6
is set with 64 steps (6-bit) in the contrast control register by a set of
compound commands.
See Figure 8 for the contrast control flow.
Solomon Systech
Oct 2003
P 26/43 Rev 1.1
SSD1818A
Figure 8 - Contrast Control Flow Set Segment Re-map
This command changes the mapping between the display data column addresses and segment drivers. It
allows flexibility in mechanical layout of LCD glass design. Please refer to Table 4 on Page 17 for
example.
Set LCD Bias
This command is used to select a suitable bias ratio required for driving the particular LCD panel in use.
The selectable values of this command for 64 MUX are 1/9 or 1/7, for 54 MUX are 1/8.4 or 1/6, for 48
MUX are 1/8 or 1/6, for 32 MUX are 1/6 or 1/5. For other bias ratio settings, extended commands should
be used.
Set Entire Display On/Off
This command forces the entire display, including the icon row, to be illuminated regardless of the
contents of the GDDRAM. In addition, this command has higher priority than the normal/reverse display.
This command is used together with "Set Display ON/OFF" command to form a compound command for
entering power save mode. See "Set Power Save Mode" later in this section.
Set Normal/Reverse Display
This command turns the display to be either normal or reverse. In normal display, a RAM data of 1
indicates an illumination on the corresponding pixel, while in reverse display, a RAM data of 0 will turn on
the pixel. It should be noted that the icon line will
not affect, that is not reverse by this command.
Set Display On/Off
This command is used to turn the display on or off. When display off is issued with entire display is on,
power save mode will be entered. See "Set Power Save Mode" later in this section for details.
Set Page Address
This command enters the page address from 0 to 8 to the RAM page register for read/write operations.
Please refer to Table 4 on Page 17 for detail mapping.
Set COM Output Scan Direction
This command sets the scan direction of the COM output allowing layout flexibility in LCD module
assembly. See Table 4 on Page 17 for the relationship between turning on or off of this feature.
In addition, the display will have immediate effect once this command is issued. That is, if this command
is sent during normal display, the graphic display will have vertical flipping effect.
No
Yes
Changes
Complete?
Set Contrast Control Register
Contrast Level Data
SSD1818A
Rev 1.1
P 27/43 Oct 2003
Solomon Systech
Set Read-Modify-Write Mode
This command puts the chip in read-modify-write mode in which:
1. column address is saved before entering the mode
2. column address is increased only after display data write but not after display data read.
This Read-Modify-Write mode is used to save the MCU's loading when a very portion of display area is
being updated frequently.
As reading the data will not change the column address, it could be get back from the chip and do some
operation in the MCU. Then the updated data could be writing back to the GDDRAM with automatic
address increment.
After updating the area, "Set End of Read-Modify-Write Mode" is sent to restore the column address and
ready for next update sequence.
Software Reset
Issuing this command causes some of the chip's internal status registers to be initialized:
Read-Modify-Write mode is off
Static indicator is turned OFF
Display start line register is cleared to 0
Column address counter is cleared to 0
Page address is cleared to 0
Normal scan direction of the COM outputs
Internal regulator resistors Ratio is set to 4
Contrast control register is set to 20h
Set End of Read-Modify-Write Mode
This command relieves the chip from read-modify-write mode. The column address before entering read-
modify-write mode will be restored no matter how much modification during the read-modify-write mode.
Set Indicator On/Off
This command turns on or off the static indicator driven by the M and MSTAT pins.
When the "Set Indicator On" command is sent, the second command byte "Indicator Display Mode" must
be followed. However, the "Set Indicator Off" command is a single byte command and no second byte
command is required.
The status of static indicator also controls whether standby mode or sleep mode will be entered, after
issuing the power save compound command. See "Set Power Save Mode" later in this section.
NOP
A command causing the chip takes No Operation.
Set Test Mode
This command forces the driver chip into its test mode for internal testing of the chip. Under normal
operation, users should NOT use this command.
Set Power Save Mode
Entering Standby or Sleep Mode should be done by using a compound command composed of "Set
Display ON/OFF" and "Set Entire Display ON/OFF" commands. When "Set Entire Display ON" is issued
when display is OFF, either Standby Mode or Sleep Mode will be entered.
The status of the Static Indicator will determine which power save mode is entered. If static indicator is off,
the Sleep Mode will be entered:
Solomon Systech
Oct 2003
P 28/43 Rev 1.1
SSD1818A
Internal oscillator and LCD power supply circuits are stopped
Segment and Common drivers output V
DD
level
The display data and operation mode before sleep are held
Internal display RAM can still be accessed
If the static indicator is on, the chip enters Standby Mode which is similar to sleep mode except addition
with:
Internal oscillator is on
Static drive system is on
Please also be noted that during Standby Mode, if the software-reset command is issued, Sleep Mode
will be entered. Both power-save modes can be exited by the issue of a new software command or by
pulling Low at hardware pin
RES
.
Status register Read
This command is issued by pulling
D/
C
Low during a data read (refer to Figure 9 on Page 34 and Figure
10 on Page 35 for parallel interface waveforms). It allows the MCU to monitor the internal status of the
chip.
No status read is provided for serial mode.
EXTENDED COMMANDS
These commands are used, in addition to basic commands, to trigger the enhanced features designed for
the chip.
Set Multiplex Ratio
This command switches default multiplex ratio to any multiplex mode from 2 to the maximum multiplex
ratio (POR value), including the icon line. Max. MUX ratio: 65
The chip pins ROW0-ROW63 will be switched to corresponding COM signal output, see Table 8 on Page
29 for examples of 18 multiplex (including icon line) settings with and without 7 lines display offset for
different MUX.
It should be noted that after changing the display multiplex ratio, the bias ratio might also need to be
adjusted to make display contrast consistent.
Set Bias Ratio
Except the 1/4 bias, all other available bias ratios could be selected using this command plus the "Set
LCD Bias" command.
For detail setting values and POR default, please refer to the extended command table, Table 6 on Page
21.
Set Temperature Coefficient (TC) Value
One out of 4 different temperature coefficient settings is selected by this command in order to match
various liquid crystal temperature grades. Please refer to the extended command table, Table 6 on Page
21, for detailed TC values.
Modify Oscillator Frequency
The oscillator frequency can be fine tuned by applying this command. Since the oscillator frequency will
be affected by some other factors, this command is not recommended for general usage. Please contact
SOLOMON Systech Limited application engineers for more detail explanation on this command.
Set 1/4 Bias Ratio
This command sets the bias ratio directly to 1/4. This bias ratio is especially designed for use in under 12
MUX display.
SSD1818A
Rev 1.1
P 29/43 Oct 2003
Solomon Systech
In order to restore to other bias ratio, this command must be executed, with LSB=0, before the "Set
Multiplex ratio" or "Set LCD Bias" command is sent.
Set Smart Icon Mode
The smart icon mode is designed for the low power application. This command is used to enable the
smart icon mode.
Set Phases of Smart Icon Mode
The contrast level of the smart icon is controlled by 4 phases. The more the total phases, the shorter
overlap time and thus the lower effective driving voltage. As a result, the contrast level of the smart icon
will be lower.
Change of this smart icon mode phases will not affect the total frame phases of the static icon. They are
independent commands.
Set Total Frame Phases of Static Icon
The total number of phases for one display frame is set by this command.
The overlapping of the M and MSTAT signals generates the Static Icon. These two pins output either V
SS
or V
DD
at same frequency but with phase different.
To turn on the Static Icon, 3 phases overlapping is applied to these signals, while 1 phase overlapping is
given to the off status.
The more the total frame phases, the shorter overlap time and thus the lower effective driving voltage. As
a result, the contrast level of the static icon will be lower.
Set Display Offset
This command should be sent ONLY when the multiplex ratio is set less than the default value.
When a lesser multiplex ratio is set, the display will be mapped in the middle (y-direction) of the LCD, see
the no offset columns on Table 8 on Page 29. Use this command could move the display vertically within
the 64 commons.
To make the Reduced-MUX Com 0 (Com 0 after reducing the multiplex ratio) towards the Row 0 direction
for L lines, the 6-bit data in second command should be given by L. An example for 7 lines moving
towards to Com0 direction is given on Table 8 on Page 29.
To move in the other direction by L lines, the 6-bit data should be given by 64-L.
Please note that the display is confined within the default multiplex value. That is the half of the default
value minus the reduced-multiplex ratio gives the maximum value of L. For an odd display MUX after
reduction, moving away from Row 0 direction will has 1 more step.
Enable Band Gap Reference Circuit
This command enables or disables the band gap reference circuit. There are four selections on the band
gap clock period. We recommended setting the band gap clock period to 200ms in normal operation.
Solomon Systech
Oct 2003
P 30/43 Rev 1.1
SSD1818A
48 MUX Mode
54 MUX Mode
32 MUX Mode
64 MUX Mode
No Offset
7 lines
Offset
No Offset
7 lines
Offset
No Offset
7 lines
Offset
No Offset
7 lines
Offset
ROW0
X X X X X COM0
X X
ROW1
X X X X X COM1
X X
ROW2
X X X X X COM2
X X
ROW3
X X X X X COM3
X X
ROW4
X X X X X COM4
X X
ROW5
X X X X X COM5
X X
ROW6
X X X X X COM6
X X
ROW7
X X X X COM0
COM7
X X
ROW8
X COM0
X X COM1
COM8
X X
ROW9
X COM1
X X COM2
COM9
X X
ROW10
X COM2
X X COM3
COM10
X X
ROW11
X
COM3 X
COM0 COM4 COM11 X
X
ROW12
X
COM4 X
COM1 COM5 COM12 X
X
ROW13
X
COM5 X
COM2 COM6 COM13 X
X
ROW14
X
COM6 X
COM3 COM7 COM14 X
X
ROW15
COM0 COM7 X
COM4 COM8 COM15
X
X
ROW16
COM1 COM8 X
COM5 NC
NC
X
COM0
ROW17
COM2 COM9 X
COM6 NC
NC
X
COM1
ROW18
COM3 COM10
COM0 COM7 NC
NC
X
COM2
ROW19
COM4 COM11
COM1 COM8 NC
NC
X
COM3
ROW20
COM5 COM12
COM2 COM9 NC
NC
X
COM4
ROW21
COM6
COM13
COM3
COM10
NC NC X COM5
ROW22
COM7
COM14
COM4
COM11
NC NC X COM6
ROW23
COM8
COM15
COM5
COM12
NC NC COM0
COM7
ROW24
NC NC COM6
COM13
NC NC COM1
COM8
ROW25
NC NC COM7
COM14
NC NC COM2
COM9
ROW26
NC NC COM8
COM15
NC NC COM3
COM10
ROW27
NC NC NC NC NC NC COM4
COM11
ROW28
NC NC NC NC NC NC COM5
COM12
ROW29
NC NC NC NC NC NC COM6
COM13
ROW30
NC NC NC NC NC NC COM7
COM14
ROW31
NC NC NC NC NC NC COM8
COM15
ROW32
COM9 COM16 COM9 COM16 COM9 COM16 COM9 COM16
ROW33 COM10 X
COM10 X
COM10 X
COM10 X
ROW34 COM11 X
COM11 X
COM11 X
COM11 X
ROW35 COM12 X
COM12 X
COM12 X
COM12 X
ROW36 COM13 X
COM13 X
COM13 X
COM13 X
ROW37 COM14 X
COM14 X
COM14 X
COM14 X
ROW38 COM15 X
COM15 X
COM15 X
COM15 X
ROW39 COM16 X
COM16 X
COM16 X
COM16 X
ROW40
X X X X X X X X
ROW41
X X X X X X X X
ROW42
X X X X X X X X
ROW43
X X X X X X X X
ROW44
X X X X X X X X
ROW45
X X X X X X X X
ROW46
X X X X X X X X
ROW47
X X X X X X X X
ROW48
X X X X NC
NC
X X
ROW49
X X X X NC
NC
X X
ROW50
X X X X NC
NC
X X
ROW51
X X X X NC
NC
X X
ROW52
X X X X NC
NC
X X
ROW53
X X X X NC
NC
X X
ROW54
X X X X NC
NC
X X
ROW55
X X X X NC
NC
X X
ROW56
NC NC X X NC NC X X
ROW57
NC NC X X NC NC X X
ROW58
NC NC X X NC NC X X
ROW59
NC NC NC NC NC NC X X
ROW60
NC NC NC NC NC NC X X
ROW61
NC NC NC NC NC NC X X
ROW62
NC NC NC NC NC NC X X
ROW63
NC NC NC NC NC NC X X
Table 8 - ROW pin assignment for COM signals for SSD1818A in an 18 MUX display
(including icon line) without/with 7 lines display offset towards ROW0
Note: X-Row pin will output non-selected COM signal
SSD1818A
Rev 1.1
P 31/43 Oct 2003
Solomon Systech
MAXIMUM RATINGS
Table 9 - Maximum Ratings (Voltage Referenced to V
SS
)
Symbol Parameter
Value
Unit
V
DD
-0.3 to +4.0
V
V
EE
Supply Voltage
0 to 12.0
V
Vin Input
Voltage
VSS-0.3 to
VDD+0.3
V
I
Current Drain Per Pin Excluding V
DD
and
V
SS
25 mA
T
A
Operating Temperature
-30 to +85
o
C
T
stg
Storage Temperature
-65 to +150
o
C
Maximum ratings are those values beyond which damages to the device may occur. Functional operation should be restricted to
the limits in the Electrical Characteristics tables or Pin Description section
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is
advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high
impedance circuit. For proper operation it is recommended that VDD and VEE be constrained to the range VSS < or = (VDD or
VEE) < or = VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open. This device may be light sensitive. Caution should be taken to avoid
exposure of this device to any light source during normal operation. This device is not radiation protected.
Solomon Systech
Oct 2003
P 32/43 Rev 1.1
SSD1818A
DC CHARACTERISTICS
Table 10 - DC Characteristics (Unless otherwise specified, Voltage Referenced to V
SS
, V
DD
= 2.4 to
3.5V, T
A
= -30 to 85
C)
Symbol Parameter
Test
Condition
Min Typ Max
Unit
V
DD
Logic Circuit Supply Voltage
Range
Recommend Operating Voltage
Possible Operating Voltage
2.4 2.7
3.5
V
V
I
AC
Access Mode Supply
Current Drain (V
DD
Pins)
V
DD
= 2.7V, Voltage Generator
On, 4X DC-DC Converter
Enabled, Write accessing, Tcyc
=3.3MHz, Typ. Osc. Freq.,
Display On, no panel attached.
- 480
600
A
I
DP1
Display Mode Supply
Current Drain (V
DD
Pins)
V
DD
= 2.7V, V
EE
= -8.1V, Voltage
Generator Disabled, R/ W ( WR )
Halt, Typ. Osc. Freq., Display
On, V
L6
- V
DD
= -9V, no panel
attached.
- 50
100
A
I
DP2
Display Mode Supply
Current Drain (V
DD
Pins)
V
DD
= 2.7V, V
EE
= -8.1V, Voltage
Generator On, 4x DC-DC
Converter Enabled, R/ W ( WR )
Halt, Typ. Osc. Freq., Display
On, V
L6
- V
DD
= -9V, no panel
attached.
- 120
200
A
I
SB
Standby Mode Supply
Current Drain (V
DD
Pins)
V
DD
= 2.7V, LCD Driving
Waveform Off, Typ. Osc. Freq.,
R/ W ( WR ) halt.
- 5
10
A
I
SLEEP
Sleep Mode Supply Current
Drain (V
DD
Pins)
V
DD
= 2.7V, LCD Driving
Waveform Off, Oscillator Off,
R/ W ( WR ) halt.
- 1
5
A
V
EE
LCD Driving Voltage
Generator Output (V
EE
Pin)
Display On, Voltage Generator
Enabled, DC-DC Converter
Enabled, Typ. Osc. Freq.,
Regulator Enabled, Divider
Enabled.
-12.0 - -2.4
V
V
LCD
LCD Driving Voltage Input
(V
EE
Pin)
Voltage Generator Disabled.
-12.0
-
-2.4
V
V
OH1
Logic High Output Voltage
Iout=-100mA
0.9*V
DD
- V
DD
V
V
OL1
Logic Low Output Voltage
Iout=100mA
0
-
0.1*
V
DD
V
V
L6
LCD Driving Voltage Source
(V
L6
Pin)
Regulator Enabled (V
L6
voltage
depends on Int/Ext Contrast
Control)
V
EE
-0.5 - V
DD
V
V
L6
LCD Driving Voltage Source
(V
L6
Pin)
Regulator Disable
-
floating
-
V
V
IH1
Logic High Input voltage
0.8*V
DD
- V
DD
V
V
IL1
Logic Low Input voltage
0 -
0.2*
V
DD
V
SSD1818A
Rev 1.1
P 33/43 Oct 2003
Solomon Systech
- 1/a*V
L6
- V
- 2/a*V
L6
- V
-
(a-2)/a
*V
L6
- V
-
(a-1)/a
*V
L6
- V
V
L2
V
L3
V
L4
V
L5
V
L6
LCD Display Voltage Output
(V
L2
, V
L3
, V
L4
, V
L5
, V
L6
Pins)
Voltage reference to V
DD
, Bias
Divider Enabled, 1:a bias ratio
- V
L6
- V
V
L3
- V
DD
V
V
L4
- V
L2
V
V
L5
- V
L3
V
V
L6
- V
L4
V
V
L2
V
L3
V
L4
V
L5
V
L6
LCD Display Voltage Input
(V
L2
, V
L3
,V
L4
, V
L5
, V
L6
Pins)
Voltage reference to V
DD
,
External Voltage Generator,
Bias Divider Disabled
-12V - V
L5
V
I
OH
Logic High Output Current
Source
Vout = V
DD
-0.4V 50
-
-
A
I
OL
Logic Low Output Current
Drain
Vout = 0.4V
-
-
-50
A
I
OZ
Logic Output Tri-state
Current Drain Source
-1
-
1
A
I
IL
/I
IH
Logic Input Current
-1
-
1
A
C
IN
Logic Pins Input
Capacitance
-
5
7.5
pF
V
L6
Variation of V
L6
Output (V
DD
is fixed)
Regulator Enabled, Internal
Contrast Control Enabled, Set
Contrast Control Register = 0
-3 0 3
%
TC0
Temperature Coefficient
Compensation
Flat Temperature Coefficient
(POR)
0 -0.07
-0.11 %/
o
C
TC2
Temperature Coefficient 2*
-0.11
-0.13
-0.15 %/
o
C
TC4
Temperature Coefficient 4*
-0.15
-0.26
-0.28 %/
o
C
TC7
Temperature Coefficient 7*
Voltage Regulator Enabled
-0.28 -0.29 -0.30
%/
o
C
The formula for the temperature coefficient is:
TC(%) = V
ref
at 50
o
C V
ref
at 0
o
C x
1
x 100 %
50
o
C 0
o
C
V
ref
at 25
o
C
Solomon Systech
Oct 2003
P 34/43 Rev 1.1
SSD1818A
AC CHARACTERISTICS
Table 11 - AC Characteristics (Unless otherwise specified, Voltage Referenced to V
SS
, V
DD
= 2.4 to
3.5V, T
A
= -30 to 85
C)
Symbol Parameter
Test
Condition
Min Typ Max Unit
Fosc
Oscillation Frequency of
Display Timing Generator for:
64 Mux Mode
54 Mux Mode
Internal Oscillator Enabled
(default), VDD = 2.7V
Remark:
Oscillation Frequency vs.
Temperature change (-20C to
70C): -0.5%/C *
15.9
26.4
18.7
31.5
25.7
42.72
KHz
F
FRM
Frame Frequency
64 Mux Mode
54 Mux Mode
48 Mux Mode
32 Mux Mode
104 x 64 Graphic Display Mode,
Display ON, Internal Oscillator
Enabled
104 x 64 Graphic Display Mode,
Display ON, Internal Oscillator
Disabled, External clock with
freq., Fext, feeding to CL pin.
104 x 54 Graphic Display Mode,
Display ON, Internal Oscillator
Enabled
104 x 54 Graphic Display Mode,
Display ON, Internal Oscillator
Disabled, External clock with
freq., Fext, feeding to CL pin.
104 x 48 Graphic Display Mode,
Display ON, Internal Oscillator
Enabled
104 x 48 Graphic Display Mode,
Display ON, Internal Oscillator
Disabled, External clock with
freq., Fext, feeding to CL pin.
104 x 32 Graphic Display Mode,
Display ON, Internal Oscillator
Enabled
104 x 32 Graphic Display Mode,
Display ON, Internal Oscillator
Disabled, External clock with
freq., Fext, feeding to CL pin.
Fosc
4x65
Fext
4x65
Fosc
8x54
Fext
8x54
Fosc
8x49
Fext
4x49
Fosc
8x33
Fext
4x33
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Remarks:
Fext stands for the frequency value of external clock feeding to the CL pin
Fosc stands for the frequency value of internal oscillator
Frequency limits are based on the software command set: set multiplex ratio
to 64 MUX
SSD1818A
Rev 1.1
P 35/43 Oct 2003
Solomon Systech
Symbol
Parameter
Min Typ Max Unit
t
cycle
Clock Cycle Time
300
-
-
ns
t
AS
Address Setup Time
0
-
-
ns
t
AH
Address Hold Time
0
-
-
ns
t
DSW
Write Data Setup Time
40
-
-
ns
t
DHW
Write Data Hold Time
15
-
-
ns
t
DHR
Read Data Hold Time
20
-
-
ns
t
OH
Output Disable Time
-
-
70
ns
t
ACC
Access
Time
-
-
140
ns
PW
CSL
Chip Select Low Pulse Width (read)
Chip Select Low Pulse Width (write)
120
60
-
-
-
-
ns
PW
CSH
Chip Select High Pulse Width (read)
Chip Select High Pulse Width (write)
60
60
-
-
-
-
ns
t
R
Rise
Time
-
-
15
ns
t
F
Fall
Time
-
-
15
ns
Table 12 - Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -35 to 85C)
t
OH
t
DHR
t
ACC
Valid Data
Valid Data
t
DSW
t
DHW
t
R
t
F
PW
CSL
PW
CSH
t
cycle
t
AH
t
AS
D
0
-D
7
(Read data from driver)
D
0
-D
7
(Write data to driver)
CS1
CS2 = 1
E
D/C
R/W
Figure 9 - 6800-series MPU Parallel Interface Characteristics
Solomon Systech
Oct 2003
P 36/43 Rev 1.1
SSD1818A
Symbol
Parameter
Min Typ Max Unit
t
cycle
Clock Cycle Time
300
-
-
ns
t
AS
Address Setup Time
0
-
-
ns
t
AH
Address Hold Time
0
-
-
ns
t
DSW
Write Data Setup Time
40
-
-
ns
t
DHW
Write Data Hold Time
15
-
-
ns
t
DHR
Read Data Hold Time
20
-
-
ns
t
OH
Output Disable Time
-
-
70
ns
t
ACC
Access
Time
-
-
140
ns
PW
CSL
Chip Select Low Pulse Width (read)
Chip Select Low Pulse Width (write)
120
60
-
-
-
-
ns
PW
CSH
Chip Select High Pulse Width (read)
Chip Select High Pulse Width (write)
60
60
-
-
-
-
ns
t
R
Rise
Time
-
-
15
ns
t
F
Fall
Time
-
-
15
ns
Table 13 - Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -35 to 85C)
t
OH
t
DHR
t
ACC
Valid Data
Valid Data
t
DSW
t
DHW
t
R
t
F
PW
CSL
PW
CSH
t
cycle
t
AH
t
AS
D
0
-D
7
(Read data from driver)
D
0
-D
7
(Write data to driver)
WR
RD
CS1
CS2 = 1
D/C
Figure 10 - 8080-series MPU Parallel Interface Characteristics
SSD1818A
Rev 1.1
P 37/43 Oct 2003
Solomon Systech
Symbol
Parameter
Min Typ Max Unit
t
cycle
Clock Cycle Time
250
-
-
ns
t
AS
Address Setup Time
150
-
-
ns
t
AH
Address Hold Time
150
-
-
ns
t
DSW
Write Data Setup Time
100
-
-
ns
t
DHW
Write Data Hold Time
100
-
-
ns
T
CLKL
Clock Low Time
100
-
-
ns
T
CLKH
Clock High Time
100
-
-
ns
t
CSS
Chip Select Setup Time (for D7 input)
120
-
-
-
-
ns
t
CSH
Chip Select Hold Time (for D0 input)
60
-
-
-
-
ns
t
R
Rise
Time
-
-
15
ns
t
F
Fall
Time
-
-
15
ns
Table 14 - Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -35 to 85C)
t
DSW
Valid Data
t
CSS
t
DHW
t
R
t
F
t
cycle
t
AH
t
AS
D/C
SDA
SCK
CS1
CS2 = 1
D/C
t
CLKL
t
CLKH
CS1
(CS2 = 1)
SDA
SCK
D7
D2
D3
D4
D5
D6
D1
D0
Figure 11 - Serial Interface Characteristics
Solomon Systech
Oct 2003
P 38/43 Rev 1.1
SSD1818A
APPLICATION EXAMPLES
Logic pin connections not specified above:
Pins connected to VDD: CS2, E/
RD
, M/
S
, CLS, C68/
80
, P/
S
, HPM
Pins connected to VSS: VSS1
Pins floating: DOF , CL
Figure 12
- Application Circuit of 104 x 64 plus an icon line using SSD1818A, configured with: external
VEE, internal regulator, divider mode enabled (Command: 2B), 6800-series MPU parallel interface, internal
oscillator and master mode
DISPLAY PANEL SIZE
104 x 64 + 1 ICONS LINE
SSD1818A IC
64 MUX
SEG0..................................SEG103
Segment Remapped
[Command: A1]
ICONS
COM0
:
:
COM10
COM11
:
:
COM30
COM31
COM32
COM33
:
:
:
:
COM63
ICONS
COM44
COM45
:
:
:
:
:
COM63
ICONS
COM10
COM11
:
:
COM18
COM19
:
:
COM30
COM31
COM43............COM32 G103............................SEG0 ICONS COM0 ...........
R
e
m
a
pp
ed
C
O
M
SC
AN
D
i
re
c
t
i
i
o
n
[Co
m
m
a
n
d
: C8
]
R
e
m
a
pp
ed
C
O
M
SC
AN
D
i
re
c
t
i
i
o
n
[Co
m
m
a
n
d
: C8
]
D0
-
D
7
/CS
1
/RE
S
D/C
R/
W
VSS
[
G
N
D
]
VE
E
IRS
External Vneg =
-9.5V
VDD = 2.775V
VL6
VL4
VL2
VL3
VL5
0.1 ~ 0.47 uF x 5
SSD1818A
Rev 1.1
P 39/43 Oct 2003
Solomon Systech
Logic pin connections not specified above:
Pins connected to VDD: CS2, E/
RD
, M/
S
, CLS, C68/
80
, P/
S
, HPM
Pins connected to VSS: VSS1
Pins floating: DOF , CL
Figure 13 - Application Circuit of 104 x 64 plus an icon line using SSD1818A, configured with all
internal power control circuit enabled, 6800-series MPU parallel interface, internal oscillator and
master mode.
DISPLAY PANEL SIZE
104 x 64 + 1 ICONS LINE
SSD1818A IC
64 MUX
(DIE FACE UP)
SEG0.................................SEG103
ICONS
COM0
:
:
COM10
COM11
:
:
COM30
COM31
COM32
COM33
:
:
:
:
COM63
ICONS
COM44
COM45
:
:
:
:
:
COM63
ICONS
COM10
COM11
:
:
COM18
COM19
:
:
COM30
COM31
COM43............COM32 SEG103............................SEG0 ICONS COM0 .......... .
R
e
m
a
pp
ed
C
O
M
SC
AN
D
i
r
e
c
t
ii
o
n
[Co
m
m
a
n
d
: C8
]
R
e
m
a
pp
ed
C
O
M
SC
AN
D
i
r
e
c
t
ii
o
n
[Co
m
m
a
n
d
: C8
]
D
0
-
D
7 an
d
Co
n
t
r
o
l
B
u
s
VSS [GND]
0.47 - 4.7uF x 5
5X boosting
VSS VEE C3N C1P C1N C2N C2P C4N
VDD = 2.775V
VL6
VL4
VL2
VL3
VL5
0.1 ~ 0.47 uF x 5
Solomon Systech
Oct 2003
P 40/43 Rev 1.1
SSD1818A
Initialization Routine
Command (Hex)
(Refer to Figure 12: All internal power
control circuit enable)
Command (Hex)
(Refer to Figure 13: External V
EE
, Internal
regulator and divider enable)
Description
1 E2
E2
Software
Reset
2
2F
2B
Set power control register
3
24 24
Set internal resistor gain
= 24h
4 81
20
81
20
Set contrast level = 20h
5
D6
3D
D6
3D
Enable band gap
reference circuit
Set band gap clock period
= 200ms
6
A0 A0
Set Column address is
map to SEG0
7
C0 C0
Set Row address is map
to COM0
8
A4 A4
Set entire display on/off
= Normal display
9
A6 A6
Set normal / reverse
display = Normal display
10
AF
AF
Set Display On
Example
Internal booster, regulator and
divider are enabled.
V
OP
= approx. -8.573V with
reference to V
DD
External booster, Internal regulator
and divider are enabled.
V
OP
= approx. -8.593V with
reference to V
DD
SSD1818A
Rev 1.1
P 41/43 Oct 2003
Solomon Systech
APPENDIX 1 TAB DRAWING
SSD1818AT Copper View Layout
Solomon Systech
Oct 2003
P 42/43 Rev 1.1
SSD1818A
SSD1818AT Detail descriptions
SSD1818A
Rev 1.1
P 43/43 Oct 2003
Solomon Systech
SSD1818AT Pin Assignment
Solomon Systech
Oct 2003
P 44/43 Rev 1.1
SSD1818A
Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or
incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for
each customer application by customer's technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of
others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the
body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could
create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or
manufacture of the part.
http://www.solomon-systech.com
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