8-bit D/A Converter Supporting with I
2
C Bus
Description
The CXA1315M/P is developed as a 5-channel 8-
bit D/A converter supporting with I
2
C bus.
Features
Serial control through I
2
C bus
5-channel 8-bit D/A converter
Built-in 4general-purpose I/O ports (Digital I/O)
I/O can be specified to respective ports independently
Selection of 8 slave addresses possible through
address select pins (3 pins)
Applications
The IC, which cannot support I
2
C bus, can support
it by connecting its control pin to the CXA1315M/P.
Structure
Bipolar silicon monolithic lC
Absolute Maximum Ratings (Ta = 25C)
Supply voltage
V
CC
12
V
Operating temperature
Topr
20 to +75
C
Storage temperature
Tstg 65 to +150 C
Allowable power dissipation P
D
960
mW
Operating Conditions
Supply voltage
V
CC
8.2 to 9.8
V
Operating temperature
Topr
20 to +75
C
1
E88Z45E26-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Purchase of Sony's I
2
C components conveys a license under the Philips I
2
C Patent Rights to use these components in
an I
2
C system, provided that the system conforms to the I
2
C Standard Specifications as defind by Philips.
CXA1315M/P
CXA1315M
16 pin SOP (Plastic)
CXA1315P
16 pin DIP (Plastic)
2
CXA1315M/P
Pin Configuration (Top View)
Block Diagram
16
V
CC
1
SW1
15
SCL
2
SW0
14
SDA
3
DAC4
13
SAD2
4
DAC3
12
SAD1
5
DAC2
11
SAD0
6
DAC1
10
SW3
7
DAC0
9
SW2
8
GND
SW I/O
DAC output
SW I/O
Slave address select pin
I
2
C bus
I
2
C Decoder
Level
Conversion
LATCH
Level
Conversion
SW0 to 3
Open collector
SAD2 SAD1 SAD0
Level
Conversion
I
2
C BUS
SDA
SCL
Power On
Reset
LATCH
DAC
AMP
DAC4
LATCH
DAC
AMP
DAC3
LATCH
DAC
AMP
DAC2
LATCH
DAC
AMP
DAC1
LATCH
DAC
AMP
DAC0
V
CC
REG
V
CC
GND
3
CXA1315M/P
Pin Description
No.
Symbol
1
2
9
10
SW1
SW0
SW2
SW3
14
SDA
Equivalent circuit
Description
I/O pin for genera-purpose I/O port
V
ILmax
: 1.5V
V
IHmin
: 3V
V
OLmax
: 0.4V
SDA I/O pin for I
2
C bus
150
V
CC
4.5k
V
CC
11
12
13
SAD0
SAD1
SAD2
15
16
SCL
V
CC
Slave address input pin
Input at positive logic
V
ILmax
: 1.5V
V
IHmin
: 3V
SCL input pin for I
2
C bus
Power supply pin
150
V
CC
4.5k
V
CC
3
4
5
6
7
DAC4
DAC3
DAC2
DAC1
DAC0
8
GND
D/A converter output pin
GND pin
56
V
CC
V
CC
20k
20k
22k
Electrical Characteristics
(Ta = 25C, V
CC
= 9V)
No.
1
Item
Circuit current
Symbol
lcc
Test conditions
Min.
DAC 0 to 4 = 127
Test
circuit
1
8
Typ.
11
Max.
15
Unit
mA
D/A Converter Block
2
3
4
5
6
7
Differential linearity
Minimum output
voltage
Maximum output
voltage
Output current
Output impedance
Repple rejection
DLE
Vmin
Vmax
Iout
Zo
Grip
V (DAC0 to 4 = n + 1) V (DAC0 to 4 = N)
128 1
V (DAC0 to 4 = 191) V (DAC0 to 4 = 63)
n = 0 to 127
DAC 0 to 4 = 0
DAC 0 to 4 = 255
Current that can be flowed from Pins 3 to 7
V (1mA) V (1mA)
DAC 0 to 4 = 127,
2mA
DAC 0 to 4 = 127, REF = 0
Superimose 100Hz to V
CC
, 1Vp-p
1
1
1
2
2
3
1
0.1
8.3
1
0
--
0
0.4
8.5
3
60
+1.1
0.62
8.9
+1
6
40
LSB
V
V
mA
dB
CXA1315M/P
SW, SAD Pins
8
8
9
10
11
Low level input
voItage
High level input
voltage
Low level input
current
High level input
current
Low level input
voltage
V
IL
V
IH
I
IL
I
IH
V
OL
Input voltage where ST0 to ST3 become "0"
Input voltage where ST0 to ST3 become "1"
lnput current when 0.4V is applied
lnput current when 4.5V is applied
SW 0 to 3 = 1,
Output voltage when 1mA flows in
4
4
4
4
5
--
3.0
10
10
0
--
--
0
0
0.2
1.5
--
+10
+10
0.4
V
V
A
A
V
No.
Item
Symbol
Test conditions
Min.
Test
circuit
Typ. Max. Unit
I
2
C Bus Block Items (SDA, SCL)
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
IH
V
IL
I
IH
I
IL
V
OL
I
OL
C
I
f
SCL
t
BUF
t
HD; STA
t
LOW
t
HIGH
t
SU; STA
t
HD; DAT
t
SU; DAT
t
R
t
F
t
SU; STO
3.0
0
--
--
0
3
--
0
4.7
4.0
4.7
4.0
4.7
5
250
--
--
4.7
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
5.0
1.5
10
10
0.4
--
10
100
--
--
--
--
--
--
--
1
300
--
V
V
A
A
V
mA
pF
kHz
s
s
s
s
s
s
ns
s
ns
s
No.
Item
Symbol
Min. Typ. Max. Unit
High level input voltage
Low level input voltage
High level input current
Low level input current
Low level output voltage, at 3mA flow to SDA (Pin 14)
Maximum flowing current
lnput capacitance
Maximum clock frequency
Data change minimum waiting time
Data transfer start minimum waiting time
Low level clock pulse width
High level clock pulse width
Minimum start preparation waiting time
Minimum data hold time
Minimum data preparation time
Rise time
Fall time
Minimum stop preparation waiting time
I
2
C bus load conditions: Pull-up resistance 4k
(Connected to +5V)
Load capacitance 200pF (Connected to GND)
I
2
C Bus Control Signal
t
LOW
t
BUF
t
HD; STA
t
R
t
HD; DAT
t
HIGH
t
SU; DAT
t
F
t
HD; STA
t
SU; STA
t
SU; STO
SDA
SCL
P
S
Sr
P
4
5
CXA1315M/P
Electrical Characteristics Measurement Circuit
Measurement Circuit 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
CXA1315M/P
I
2
C BUS
5V
0.022
10
+9V
100p
100p
100p
100p
100p
Measurement Circuit 2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
CXA1315M/P
I
2
C BUS
0.022
10
+9V
100p
100p
100p
100p
100p
1mA
Measurement Circuit 3
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
CXA1315M/P
I
2
C BUS
0.022
10
+9V
100p
100p
100p
100p
100p
100Hz, 1Vp-p
Measurement Circuit 4
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
CXA1315M/P
I
2
C BUS
0.022
10
+9V
V
4
V
4
=
1.5V (No.8)
2.0V (No.9)
0.4V (No.10)
4.5V (No.11)
Measurement Circuit 5
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
CXA1315M/P
I
2
C BUS
0.022
10
+9V
1mA
6
CXA1315M/P
Definition of I
2
C Bus Register
<SIave address>
0
1
0
0
SAD2 SAD1
SAD0
R/W
MSB
LSB
R/W
0: SLAVE RECEIVER
1: SLAVE TRANSMITTER
SAD0 to 2:11 to13 pin
0: "Low"
1: "High"
<Register table>
With the lC reset all registers are reset to "0"
: Not defined
x: Don't care
Sub address is auto incremented
lt can be used as a 6-bit D/A converter by setting the lower two bits of DAC0 to 4 registers to "0", but take
care that the max. voltage of DA output will lower about 100mV compared with the use of 8 bits.
Control Register
Sub address
x x x x x 0 0 0
x x x x x 0 0 1
x x x x x 0 1 0
x x x x x 0 1 1
x x x x x 1 0 0
x x x x x 1 0 1
Bit 7
REF
DAC0 (8)
DAC1 (8)
DAC2 (8)
DAC3 (8)
DAC4 (8)
Bit 6
Bit 5
Bit 4
Bit 3
SW3
Bit 2
SW2
Bit 1
SW1
Bit 0
SW0
Bit 7
PONRES
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
ST3
Bit 2
ST2
Bit 1
ST1
Bit 0
ST0
Status Register
7
CXA1315M/P
<Registers> In brackets ( ) number of bits
REF
(1) : Switches D/A converter reference voltage
0:
Standardizes the inner regulator
1:
Standardizes voltage resistance divided from Vcc
SW0 to 3
(1) : Selects ON/OFF of Pins 1, 2, 9 and 10
(Each pin is the open collector output of NPN transistor)
0:
OFF
1:
ON
DAC0 to 4
(8) : Digital data input register of D/A converter
0:
Output voltage turns to minimum
255: Output voItage turns to maximum
PONRES
(1) : Detects POWER ON RESET
0:
Master passes from the bus and is reset to "0" after having read this status
1:
Sets to "1" when power supply is turned on or when there has been a power dip
ST0 to 3
(1) : Detects and registers the voltage condition of Pins 1, 2, 9 and 10
0:
1.5V and below
1:
3.0V and above
Note) SW0 to 3 effective during "0"
I
2
C Bus Signal
There are 2 signals in I
2
C bus. SDA (Serial Data) and SCL (Serial Clock).
SDA is double-way.
As SDA is bidirectional it has 3 state outputs, H, L and Hi-Z.
I
2
C transfer begins with Start Condition and ends with Stop Condition.
SDA
SCL
Start Condition S
Stop Condition P
H
L
Hi-Z
L
8
CXA1315M/P
I
2
C data write (Write from I
2
C controller to IC)
I
2
C data read (Read from IC to I
2
C controller)
SDA
SCL
MSB
1
2
3
4
5
6
MSB
LSB
Hi-Z
Hi-Z
At "L" during write
7
8
9
1
8
9
Address
ACK
Sub Address
ACK
S
LSB
Hi-Z
MSB
Hi-Z
1
8
9
1
8
9
DATA (n)
DATA (n + 1)
ACK
ACK
DATA (n + 2)
Hi-Z
Hi-Z
8
9
1
8
9
DATA
DATA
ACK
ACK
P
The number of data that can be
transferred at a time is confined to
units of 8-bit that can be set as required.
Sub Address is incremented automatically.
8
9
1
7
8
9
6
7
1
Hi-Z
Address
DATA
ACK
ACK
P
S
SDA
SCL
At "H" during read
Read timing
7
8
9
5
6
3
4
1
2
9
LSB
MSB
DATA
ACK
ACK
SCL
Read timing
IC output SDA
Data read is performed with SCL rise.
9
CXA1315M/P
Application Circuit
2SC2785
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
CXA1315M/P
I
2
C BUS
0.022
10
+9V
D/A converter output
10k
10k
10k
10k
2SC2785
10k
10k
10k
10k
General-purpose
output port
General-purpose
input port
Slave address for 4Ch and 4Dh
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Characteristics Diagram
25
0.1
D/A converter output temperture
characteristics (REF: 1)
T [C]
Voltage variation at. 25
C [V]
0
25
50
75
0
0.1
Data: 0
Data: 128
Data: 255
Data: 255
Data: 128
Data: 0
V
CC
= 9V
25
0.1
D/A converter output temperture
characteristics (REF: 0)
T [C]
Voltage variation at. 25
C [V]
0
25
50
75
0
0.1
Data: 0
Data: 128
Data: 255
Data: 255
Data: 128
Data: 0
V
CC
= 9V
10
CXA1315M/P
Package Outline
Unit: mm
CXA1315M
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
SONY CODE
EIAJ CODE
JEDEC CODE
SOP-16P-L01
SOP016-P-0300
COPPER ALLOY
SOLDER PLATING
EPOXY RESIN
16PIN SOP (PLASTIC)
9.9 0.1
+ 0.4
16
9
1
8
1.27
0.45
0.1
5.3
0.1
+ 0.3
7.9
0.4
6.9
1.85 0.15
+ 0.4
0.5
0.2
0.2 0.05
+ 0.1
0.1 0.05
+ 0.2
0.2g
0.15
M
0.24
LEAD PLATING SPECIFICATIONS
ITEM
LEAD MATERIAL
COPPER ALLOY
SOLDER COMPOSITION
Sn-Bi Bi:1-4wt%
PLATING THICKNESS
5-18
m
SPEC.
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
SONY CODE
EIAJ CODE
JEDEC CODE
SOP-16P-L01
SOP016-P-0300
COPPER ALLOY
SOLDER PLATING
EPOXY RESIN
16PIN SOP (PLASTIC)
9.9 0.1
+ 0.4
16
9
1
8
1.27
0.45
0.1
5.3
0.1
+ 0.3
7.9
0.4
6.9
1.85 0.15
+ 0.4
0.5
0.2
0.2 0.05
+ 0.1
0.1 0.05
+ 0.2
0.2g
0.15
M
0.24
CXA1315M/P
11
CXA1315P
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
COPPER ALLOY
19.2 0.1
+ 0.4
9
1
8
2.54
0.5
0.1
1.2
0.15
3.0 MIN
0.5 MIN
3.7
0.1
+ 0.4
6.4
0.1
+ 0.3
7.62
0.25
0.05
+ 0.1
0 to 15
16
16PIN DIP (PLASTIC)
1.0 g
SONY CODE
EIAJ CODE
JEDEC CODE
DIP-16P-01
DIP016-P-0300
Similar to MO-001-AE
1.All mat surface type.
Two kinds of package surface:
2.All mirror surface type.
LEAD PLATING SPECIFICATIONS
ITEM
LEAD MATERIAL
COPPER ALLOY
SOLDER COMPOSITION
Sn-Bi Bi:1-4wt%
PLATING THICKNESS
5-18
m
SPEC.
Package Outline
Unit: mm
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
COPPER ALLOY
19.2 0.1
+ 0.4
9
1
8
2.54
0.5
0.1
1.2
0.15
3.0 MIN
0.5 MIN
3.7
0.1
+ 0.4
6.4
0.1
+ 0.3
7.62
0.25
0.05
+ 0.1
0 to 15
16
16PIN DIP (PLASTIC)
1.0 g
SONY CODE
EIAJ CODE
JEDEC CODE
DIP-16P-01
DIP016-P-0300
Similar to MO-001-AE
1.All mat surface type.
Two kinds of package surface:
2.All mirror surface type.
12
CXA1315M/P
Sony Corporation
CXA1315P
Package Outline
Unit: mm
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
COPPER
DIP-16P-191
DIP016-P-0300-AU
MS-001-AA
16PIN DIP (PLASTIC) 300mil
0 to 10
0.28
0.06
6.35
0.127
7.62
1
8
9
16
19.35
0.5
2.54
0.254
0.457
0.076
1.016
3.1 MIN
0.508 MIN
5.08 MAX
+ 0.1
1.0g
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