--1--

E94612B5Z-TE

US Audio Multiplexing Decoder

CXA1734S

30 pin SDIP (Plastic)

Absolute Maximum Ratings (Ta=25°C)

· Supply voltage

· Operating temperature

Topr

20 to +75

°C

· Storage temperature

Tstg

65 to +150

°C

· Allowable power dissipation

1.35

Range of Operating Supply Voltage

9 ± 0.5

Applications

TV, VCR and other decoding systems for US audio

multiplexing TV broadcasting

Structure

Bipolar silicon monolithic IC

Description

The CXA1734S is an IC designed as a decoder

for the Zenith TV Multi-channel System also

corresponds with I

C BUS. Functions include stereo

demodulation, SAP (Separate Audio Program)

demodulation and dbx noise reduction. Various

kinds of filters are built in while adjustment and

mode control are all executed through I

C BUS.

Features

· Audio multiplexing decoder and dbx noise

reduction decoder are all included in a single chip.

Almost any sort of signal processing is possible

through this IC.

· All adjustments are possible through I

C BUS to

allow for automatic adjustment.

· Various built-in filter circuits greatly reduce external

parts.

Standard I/O Level

· Input level

COMPIN (Pin 11)

245 mVrms

· Output level

LOUT (Pin 29)

490 mVrms

ROUT (Pin 28)

490 mVrms

Pin Configuration (Top View)

LOUT

ROUT

ITIME

VCATC

VCAWGT

VEOUT

VETC

VEWGT

SAPOUT

GND

NOISETC

VCAIN

SAPIN

SDA

SCL

DGND

SAD

VGR

IREF

MAININ

PLINT

STFIL

COMPIN

SAPTC

SUBOUT

STIN

MAINOUT

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

For the availability of this product, please contact the sales office.

--2--

CXA1734S

Block Diagram

VGR

IRE

SAD

DGND

SCL

SDA

SAPOU

SAPIN

STIN

VEWG

VETC

VEOU

VCAI

VCAW

VCAT

ININ

INOU

SUBO

PLIN

STFI

I
N

I
SET

SAPT

OGIC

I
X

BPF

SAPVC

OIS

SAPI

SAPF

"
P

ES"

I
N

"
SAPL

SAPVD

"
SAP"

"
N

I
SE"

SAPVC

SAPL

/
F

/
SAPC

/
M

I
D

EBAN

SPEC

"
SAPVC

(
+

4dB

)

S I

/
F

6dB

--3--

CXA1734S

Symbol

Equivalent circuit

Description

No.

voltage

Pin Description

(Ta = 25°C, V

= 9 V)

SDA

SCL

DGND

SAD

VGR

1.3V

Serial data I/O pin.

> 3.0 V

< 1.5 V

Serial clock input pin.

> 3.0 V

< 1.5 V

Digital block GND.

Slave address control

switch.

The slave address is

selected by changing the

voltage applied to this pin.

Band gap reference output

pin. Connect a 10 µF

capacitor between this pin

and GND.

7.5k

4.5k

7.5k

35µ

2.1V

7.5k

35µ

2.1V

19.5k

40k

80k

10k

11k

9.7k

19.4k

2.06k

147

1.3V

11k

--4--

CXA1734S

Symbol

Equivalent circuit

Description

No.

voltage

IREF

MAININ

MAINOUT

PLINT

1.3V

4.0V

6.3V

Set the filter and VCO

reference current. The

reference current is

adjusted with the BUS

DATA based on the

current which flows to this

pin. (Connect a 62 k

±1%) resistor between this

pin and GND.)

Input the (L + R) signal

from MAINOUT (Pin 8).

(L + R) signal output pin.

Pilot cancel circuit loop

filter integrating pin.

(Connect a 1 µF capacitor

between this pin and

GND.)

40k

30k

30p 1.8k

16k

6.3k

147

30k

15k

30k

147

23k

47k

10µ

147

15k

200µ

147

12k

10k

20k

26µ

50µ

--6--

CXA1734S

Symbol

Equivalent circuit

Description

No.

voltage

STIN

SAPIN

NOISETC

GND

SAPOUT

4.0V

3.0V

4.0V

Input the (L - R) signal

from SUBOUT (Pin 13).

Input the (SAP) signal

from SAPOUT (Pin 18).

Supply voltage pin.

Set the time constant for

the noise detection circuit.

(Connect a 4.7 µF

capacitor and a 200 k

resistor between this pin

and GND.)

Analog block GND.

SAP FM detector output

pin.

Variable de-emphasis

integrating pin.

(Connect a 2700 pF

capacitor and a 3.3 k

resistor in series between

this pin and GND.)

23k

147

47k

20k

11.7k

23k

147

47k

3.3k

Vcc

10k

Vcc

24k

500

Vcc

500

17k

7.4k

147

10µ

50µ

7.5k

147

--7--

CXA1734S

Symbol

Equivalent circuit

Description

No.

voltage

VEWGT

VETC

VEOUT

VCAIN

4.0V

1.7V

4.0V

Weight the variable de-

emphasis control effective

value detection circuit.

(Connect a 0.047 µF

capacitor and a 3 k

resistor in series between

this pin and GND.)

Determine the restoration

time constant of the

variable de-emphasis

control effective value

detection circuit. The

specified restoration time

constant can be obtained

by connecting a 3.3 µF

capacitor between this pin

and GND.

Variable de-emphasis

output pin.

(Connect a 4.7 µF non-

polar capacitor between

Pins 23 and 24.)

VCA input pin.

Input the variable de-

emphasis output signal

from Pin 23 via a coupling

capacitor.

Vcc

36k

2.9V

500

147

500

30k

8µ

50µ

20k

Vcc

50µ

7.5µ

Vcc

10k

500

20k

47k

--8--

CXA1734S

Symbol

Equivalent circuit

Description

No.

voltage

VCAWGT

VCATC

ITIME

4.0V

1.7V

1.3V

Weight the VCA control

effective value detection

circuit.

(Connect a 1 µF capacitor

and a 3.9 k

resistor in

series between this pin and

GND.)

Determine the restoration

time constant of the VCA

control effective value

detection circuit.

The specified restoration

time constant can be

obtained by connecting a

10 µF capacitor between

this pin and GND.

Set the reference current

for the effective value

detection timing current.

The reference current is

adjusted with the BUS

DATA "SPECTRAL" based

on the current which flows

to this pin.

The timing current

determines the restoration

time constant of the

detection circuit and the

variable de-emphasis

characteristics.

Connect a 43 k

(±1%)

resistor between this pin

and GND.

30k

36k

2.9V

500

500 147

40k

50µ

8µ

20k

50µ

7.5µ

40k

30k

30p 1.8k

2.6V

25k

147

20k

40k

10k

47k

--10--

CXA1734S

Electrical Characteristics

Main (L+R)

=245mVrms

(Pre-Emphasis : OFF)

COMPIN input level

SUB (L-R)

=490mVrms

(dbx-TV : OFF)

(100% modulation level)

Pilot

=49mVrms

SAP Carrier

=147mVrms

=15.734kHz

No.

Item

Current consumption

Main output level

De-emphasis frequency

characteristics

Main LPF frequency

characteristics

Main distortion

Main overload

distortion

Mono S/N

Sub output level

Sub LPF frequency

characteristics

Sub distortion

Sub overload

distortion

Sub S/N

Sub pilot leak

ST on level

ST on/off hysteresis

Symbol

Icc

Vmain

FCdeem

FCmain

THDm

THDmmax

SNmain

Vsub

FCsub

THDsub

THDsmax

SNsub

PCsub

THst

HYst

Mode

Mono

Input

Min.

440

1.2

3.0

150

3.0

8.0

3.5

Typ.

490

1.0

0.1

0.15

190

0.5

0.1

0.5

1.0

6.0

Max.

540

1.0

0.5

230

1.0

2.0

7.0

4.0

8.5

Unit

mVrms

Input signal

MAIN 1k 100%

Pre-em ON

MAIN 5k 30%

Pre-em ON

MAIN 12k 30%

Pre-em ON

MAIN 1k 100%

Pre-em ON

MAIN 1k 200%

Pre-em ON

NO Signal

SUB 1k 100%

NR-OFF

SUB 12k 30%

NR-OFF

SUB 1k 100%

NR-OFF

SUB 1k 200%

NR-OFF

0dB

(49mVrms)

0dB

(49mVrms)

Output

Others

Using 15 kHz LPF

Compared with the TEST2 output level

Using 15 kHz LPF

Compared with the TEST8 output level

Using f

BPF

0dB=49mVrms

Conditions

--11--

CXA1734S

No.

Item

ST separation 1

ST separation 2

SAP output level

SAP LPF frequency

characteristics

SAP distortion

SAP S/N

SAP on level

SAP on/off hysteresis

Symbol

STsep1

STsep2

Vsap

FCsap

THDsap

SNsap

THsap

HYsap

Mode

SAP

Input

Min.

150

3.0

2.5

Typ.

190

2.5

Max.

230

2.5

6.0

6.5

5.5

Unit

mVrms

Input signal

ST 300Hz

30%, NR-ON

ST 3kHz

30%, NR-ON

SAP 1k 100%

NR-OFF

SAP 10k 30%

NR-OFF

SAP 1k 100%

NR-OFF

SAP Carrier

147mVrms

SAP Carrier

Output

Others

Using 15kHz LPF

Compared with the TEST18 output level

0dB=147mVrms

Conditions

--12--

CXA1734S

C BUS block items (SDA, SCL)

C BUS load conditions:

Pull-up resistor 4 k

(Connect to +5 V)

Load capacity 200 pF (Connect to GND)

C BUS Control Signal

No.

Item

High level input voltage

Low level input voltage

High level input current

Low level input current

Low level output voltage SDA (Pin 1) during 3 mA inflow

Max. inflow current

Input capacitance

Max. clock frequency

Minimum waiting time for data change

Minimum waiting time for start of data transfer

Low level clock pulse width

High level clock pulse width

Minimum waiting time for start preparation

Min. data hold time

Min. data preparation time

Rise time

Fall time

Minimum waiting time for stop preparation

Symbol

SCL

BUF

HD:STA

LOW

HIGH

SU:STA

HD:DAT

SU:DAT

SU:STO

Min.

3.0

4.7

4.0

4.7

4.0

4.7

250

4.7

Typ.

Max.

5.0

1.5

0.4

100

300

Unit

µA

kHz

µs

SDA

SCL

tBUF

tHD;STA

tLOW

tHD;DAT

tHIGH

tHD;STA

tSU;STA

tSU;STO

tSU;DAT

--13--

CXA1734S

Electrical Characteristics Measurement Circuit

LOUT

ROUT

ITIME

VCATC

VCAWGT

VEOUT

VETC

VEWGT

SAPOUT

GND

NOISETC

VCAIN

SAPIN

SDA

SCL

DGND

SAD

VGR

IREF

MAININ

PLINT

STFIL

COMPIN

SAPTC

SUBOUT

STIN

MAINOUT

C BUS DATA

DGND

220

10µ

62k

METAL ±1

4.7µ

1µ

C10

0.47µ

2.2k

C11

0.22µ

C13

4.7µ

C18

4.7µ

C17

4.7µ

SIGNAL

GENERATOR

GND

C19

100µ

C16

4.7µ

C15

4.7µ

3.3k

2700p

C14

0.047µ

C12

TANTALUM

3.3µ

4.7µ

1µ

10µ

43k

METAL ±1

4.7µ

3.9k

4.7µ

BUFF

FILTERS

MEASURES

15kHz LPF

BPF

200k

TANTALUM

--14--

CXA1734S

C BUS Register Data Standard Setting Values

Classification

A: Adjustment

U: User control

S: Proper to set

T: Test

ATT

STVCO

SAPVCO

SAPLPF

STLPF

SPECTRAL

WIDEBAND

TEST-DA

TEST1

NRSW

FOMO

SAPC

ATTSW

Number of

bits

Classification

Standard

setting

Contents

Center point

Normal mode

According to the

mode control table

Mute OFF

Fixed by the set

specifications

Setting value when electrical

characteristics are measured

Adjustment point

List of Adjustment Contents

Adjustment

item

MAIN VCA

ST VCO

SAP VCO

ST & dbx

FILTER

SAP

FILTER

Low frequency

ST separation

High frequency

ST separation

Adjustment

data

ATT

STVCO

SAPVCO

STLPF

SAPLPF

WIDEBAND

SPECTRAL

Input pin

COMPIN

(Pin 11)

None

COMPIN

(Pin 11)

COMPIN

(Pin 11)

COMPIN

(Pin 11)

COMPIN

(Pin 11)

COMPIN

(Pin 11)

Input signal

100Hz

245mVrms

None

(78.67k)

147mVrms

9.4kHz

600mVrms

88kHz

120mVrms

ST-L 30%

300Hz

ST-L 30%

3kHz

Measurement

item

LOUT output

level

ROUT output

frequency

STA7

(SAPVCO1)

STA8

(SAPVCO2)

STA3

(STLPF)

STA4

(SAPLPF)

ROUT output

level

ROUT output

level

Adjustment contents

Adjust as close to 490

mVrms as possible

Adjust as close to 62.936

kHz as possible

Adjust to the center of the

SAPVCO1 = 0, SAPVCO2

= 1 condition

Adjust to the center of the

STLPF = 1 condition

Adjust to the center of the

SAPLPF = 1 condition

Minimize the output level

Test mode

setting

TEST-DA=1

TEST1=1

--15--

CXA1734S

Adjustment Method

ATT adjustment

1. TEST BIT is set to "TEST1 = 0" and "TEST-DA = 0".

2. Input a 100 Hz, 245 mVrms sine wave signal to COMPIN and monitor the LOUT output level. Then,

adjust the "ATT" data for ATT adjustment so that LOUT output goes to the standard value.

3. Adjustment range:

±30%

Adjustment bits:

4 bits

Stereo VCO adjustment

1. TEST BIT is set to "TEST1 = 0" and "TEST-DA = 1".

2. Monitor the ROUT output (4 f

free run) frequency in a no input state, and adjust "STVCO" adjustment

data so that this frequency is as close to 4f

(62.936 kHz) as possible.

3. Adjustment range:

±20%

Adjustment bits:

6 bits

SAPVCO adjustment

1. TEST BIT is set to "TEST1 = 0" and "TEST-DA = 0".

2. Input a 5f

(SAP carrier , 78.67 kHz) , 147 mVrms sine wave signal to COMPIN. While monitoring the

STATUS FLAG (STA7, STA8) condition, adjust "SAPVCO" adjustment data.

3. Adjustment range:

±20%

Adjustment bits:

4 bits

Align SAPVCO with the center of the STA7 = 0 and STA8 = 1 (adjustment OK) condition range.

Stereo block dbx filter adjustment

1. TEST BIT is set to "TEST1 = 1" and "TEST-DA = 0".

2. Input a 9.4 kHz, 600 mVrms sine wave signal to COMPIN. While monitoring the STATUS FLAG

(STA3) condition, adjust the "STLPF" adjustment data.

3. Adjustment range:

±20%

Adjustment bits:

6 bits

Align STLPF with the center of the STA3 = 1 (adjustment OK) condition range.

Adjustment point

1
0

Control data
"SAPVCO"

Measurement data
STA7 "SAPVCO1"

STA8 "SAPVCO2"

Adjustment point

1
0

Control data
"STLPF"

Measurement data
STA3 "STLPF"

--16--

CXA1734S

SAP block filter adjustment

1. TEST BIT is set to "TEST1 = 1" and "TEST-DA = 0".

2. Input a 88 kHz, 120 mVrms sine wave signal to COMPIN. While monitoring the STATUS FLAG (STA4)

condition, vary and adjust the "SAPLPF" adjustment data.

3. Adjustment range:

±20%

Adjustment bits:

4 bits

Align SAPLPF with the center of the STA4 = 1 (adjustment OK) condition range.

Separation adjustment

1. TEST BIT is set to "TEST1 = 0" and "TEST-DA = 0".

2. Set the unit to stereo mode and input the left channel only signal (modulation factor 30%, frequency

300 Hz) to COMPIN. At this time, adjust the "WIDEBAND" adjustment data to reduce ROUT output to

the minimum.

3. Next, set the frequency only of the input signal to 3 kHz and adjust the "SPECTRAL" adjustment data

to reduce ROUT output to the minimum.

4. Then, the adjustments in 2 and 3 above are performed to optimize the separation.

5. "WIDEBAND"

"SPECTRAL"

Adjustment range:

±30%

Adjustment range:

±15%

Adjustment bits:

6 bits

Adjustment bits:

6 bits

Adjustment point

1
0

Control data
"SAPLPF"

Measurement data
STA4 "SAPLPF"

--17--

CXA1734S

Description of Operation

The US audio multiplexing system possesses the base band spectrum shown in Fig. 1.

Fig. 1. Base band spectrum

Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block)

Fig. 3. dbx-TV block

PEAK DEV

kHz

L+R

50-15kHz

L-R

dbx-TV

AM-DSB-SC

SAP

dbx-TV NR

FM 10kHz

50-10kHz

TELEMETRY

FM 3kHz

=15.734kHz

6.5f

PILOT

(COMPIN)

STEREO LPF

PLL

(VCO 8f

)

C BUS

DECODER
MODE
CONTROL

PILOT

DET

MVCA

PILOT

CANCEL

MAIN LPF DE.EM

(MAIN OUT)

L+R

4.7µ

(MAIN IN)

L-R (DSB)

DET

INJ.

LOCK

SUBVCA

SUB LPF

WIDEBAND

(SUBOUT) (ST IN)

4.7µ

NR SW

dbx-TV

BLOCK

MATRIX

(L-OUT)

(R-OUT)

MODE

CONTROL

(SAP IN)

4.7µ

SAP(FM)

DET

SAP LPF

SAP

DET

SAP BPF

(SAP OUT)

L-R

C BUS

DECODER
MODE
CONTROL

NOISE

DET

C BUS

DECODER

0°

90°

0°

NR SW

FIXED

DEEMPHASIS

VARIABLE

DEEMPHASIS (VE OUT) (VCA IN)

MATRIX

4.7µ

HPF

LPF

VCA

RMS

DET

RMS

DET

--18--

CXA1734S

(1) L + R (MAIN)

After the audio multiplexing signal input from COMPIN (Pin 11) passes through MVCA, the SAP signal

and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the

L - R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened

(de-emphasized) and input to the matrix.

(2) L - R (SUB)

The L - R signal follows the same course as L + R before the pilot signal is canceled. L - R has no

carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM

modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave)

to be used for the demodulation of the L - R signal. In the last stage, the residual high frequency

components are removed by SUB LPF and the L - R signal is input to the dbx-TV block via the NRSW

circuit after passing through SUBVCA.

(3) SAP

SAP is an FM signal using 5f

as a carrier as shown in the Fig.1. First, the SAP signal only is

extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency

components are removed and freqency characteristics flattened using SAP LPF, and the SAP signal is

input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 18 output is soft

muted.

(4) Mode discrimination

Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is

performed by detecting the 5f

carrier amplitude. NOISE discrimination is performed by detecting the

noise near 25 kHz after FM detection.

(5) dbx-TV block

Either the SAP signal or L - R signal input respectively from ST IN (Pin 14) or SAP IN (Pin 19) is

selected by the mode control and input to the dbx-TV block.

The input signal then passes through the fixed de-emphasis circuit and is applied to the variable de-

emphasis circuit. The signal output from the variable de-emphasis circuit passes through an external

capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a

current to a voltage using an operational amplifier and then input to the matrix.

The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by each of

effective value detection circuits. Each of the effective value detection circuits passes the input signal

through a predetermined filter for weighting before the effective value of the weighted signal is

detected to provide the control signal.

(6) Others

"MVCA" is a VCA which adjusts the input signal level to the standard level of this IC. In addition, the

input signal enters the decoder without passing through MVCA by setting to ATTSW = 1.

The signals (L + R, L - R, SAP) input to "MATRIX" are selected according to the BUS data and

whether there is ST or SAP discrimination, and any one of the ST-L, ST-R, MONO or SAP signals is

output to LOUT and ROUT.

"Bias" supplies the reference voltage and reference current to the other blocks. The currents flowing to

the resistors connecting IREF (Pin 6) and ITIME (Pin 27) with GND become the reference current.

--19--

CXA1734S

Register Specifications

Slave address

: Don't Care

Status Register

When TEST1 = 0

When TEST1 = 1

STA1

STA2

STA3

STA4

STA5

STA6

STA7

STA8

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

POWER

STEREO

SAP

NOISE

SAP VCO1

SAP VCO2

ON RESET

STA1

STA2

STA3

STA4

STA5

STA6

STA7

STA8

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

POWER

STEREO

STLPF

SAPLPF

ON RESET

SAD pin

SLAVE RECEIVER

SLAVE TRANSMITTER

GND

80H

81H

8AH

8BH

SUB ADDRESS

MSB

LSB

0000

0001

0010

0011

0100

0101

0110

DATA

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

ATTSW

TEST-DA

TEST1

ATT [4] INPUT LEVEL adj

STVCO [6] STEREO VCO adj

(SAPVCO [4] SAP VCO adj)

(SAPLPF [4] SAP FILTER adj)

STLPF [6] ST FILTER adj

SPECTRAL [6]

WIDEBAND [6]

NRSW

FOMO

SAPC

--20--

CXA1734S

Description of Registers

Control registers

Classification

U: User control

A: Adjustment

S: Proper to set

T: Test

Status registers

ATT

STVCO

SAPVCO

SAPLPF

STLPF

SPECTRAL

WIDEBAND

TEST-DA

TEST1

NRSW

FOMO

SAPC

ATTSW

Number

of bits

Classifi-

cation

Contents

Input level adjustment

STEREO VCO free running frequency adjustment

SAP VCO free running frequency adjustment

SAP filter adjustment

STEREO and dbx filter adjustment

Adjustment of stereo separation (3 kHz)

Adjustment of stereo separation (300 Hz)

Turn to DAC test mode and STVCO adjustment mode by means of

TEST-DA = 1.

Turn to test mode by means of TEST = 1. (Adjustment of STLPF and

SAPLPF)

Selection of the output signal (STEREO mode , SAP mode)

Turn to forced MONO by means of FOMO = 1. (LOUT only is

MONO during SAP output.)

Selection of mute ON/OFF (0: mute ON, 1: mute OFF)

Selection of SAP mode or L + R mode according to the presence of

SAP broadcasting

Turns the input stage MVCA off when ATTSW = 1.

PONRES

STEREO

SAP

NOISE

STLPF

SAPLPF

SAPVCO1

SAPVCO2

Number of bits

Contents

POWER ON RESET detection;

1: RESET

Stereo discrimination of the input signal;

1: Stereo

SAP discrimination of the input signal;

1: SAP

Noise level discrimination of the input signal mode;

1: Noise

Status of STEREO filter adjustment;

1: OK range

Status of SAP filter adjustment;

1: OK range

Status 1 of SAP VCO free running frequency adjustment; 0: OK range

Status 2 of SAP VCO free running frequency adjustment; 1: OK range

--21--

CXA1734S

Description of Control Registers

ATT (4):

Adjust the signal level input to COMPIN (Pin 11) to the reference level (245 mVrms).

Variable range of the input signal:

245 mVrms 5.0 dB to +3.0 dB

0 = Level min.

F = Level max.

STVCO (6):

Adjust STEREO VCO free running frequency (f

Variable range:

±20%

0 = Free running frequency min.

3F = Free running frequency max.

SAPVCO (4):

Adjust SAPVCO free running frequency (f

Variable range:

±20%

0 = Free running frequency min.

F = Free running frequency max.

SAPLPF (4):

Adjust the filter f

of the SAP block.

Variable range:

±20%

0 = Frequency min.

F = Frequency max.

STLPF (6):

Adjust the filter f

of the ST and dbx blocks.

Variable range:

±20%

0 = Frequency min.

3F = Frequency max.

SPECTRAL (6): Perform high frequency (fs = 3 kHz) separation adjustment.

0 = Level max.

3F = Level min.

WIDEBAND (6): Perform low frequency (fs = 300 Hz) separation adjustment.

0 = Level min.

3F = Level max.

TEST1 (1):

Set filter adjustment mode.

0 = Normal mode

1 = STLPF (STA3) and SAPLPF (STA4) adjustment mode

In addition, the following outputs are present at Pins 28 and 29.

LOUT (Pin 29):

SAP BPF OUT

ROUT (Pin 28):

NR BPF OUT

TEST-DA (1):

Set DAC output test mode and STVCO adjustment mode.

0 = Normal mode

1 = DAC output test mode and STVCO adjustment mode

LOUT (Pin 29):

DA control DC level

ROUT (Pin 28):

STEREO VCO oscillation frequency (4 f

)

--23--

CXA1734S

Description of Mode Control

Priority ranking: TEST-DA > TEST1 > M1 > (NRSW & FOMO & SAPC)

Mode control

NRSW

FOMO

SAPC

TEST1

TEST-DA

SAPC=0

"Select dbx input and LOUT & ROUT output"

Conditions: FOMO = 0

NRSW = 0 (MONO or ST output)

· During ST input:

LOUT : L,

ROUT : R

· During other input:

LOUT : L + R,

ROUT : L + R

NRSW = 1 (SAP output)

· When there is "SAP" during SAP

discrimination

LOUT: SAP, ROUT: SAP

· When there is "No SAP", output is the same

as when NRSW = 0.

"Forced MONO"

FOMO = 1

· During SAP output: LOUT: L + R, ROUT: SAP

· During ST or MONO output: LOUT: L + R, ROUT: L + R

Change the selection conditions for "MONO or ST output" and "SAP output".

SAPC = 0:

Switch to SAP output when there is SAP discrimination.

Do not switch to SAP output when there is no SAP discrimination.

SAPC = 1:

Switch to SAP output regardless of whether there is SAP

discrimination.

"MUTE"

M1 = 0

Output is muted.

"TEST1"

TEST1 = 1

Return adjustment data with STATUS REGISTER as an adjustment mode.

In addition, outputs are as follows.

LOUT: SAP BPF OUT

ROUT: NR BPF OUT

"TEST-DA"

TEST-DA = 1

Used to TEST of D/A.

LOUT: D/A output

ROUT: STVCO oscillation frequency (4 f

)

SAPC=1

"Select dbx input and LOUT & ROUT output"

Conditions: FOMO = 0

NRSW = 0 (MONO or ST output)

As on the left

NRSW = 1 (SAP output)

· Regardless of the presence of SAP

discrimination,

dbx input: "SAP"

LOUT: SAP, ROUT: SAP

However, when there is no SAP, SAPLPF

output is soft muted (7 dB)

--24--

CXA1734S

Mode Control No. 1 (SAPC = 1)

Note)

(SAP) : The SAPOUT output signal is soft muted (approximately 7 dB).

The signal is soft muted when NOISE = 1.

: Don't care.

1) : SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is

inputted in the weak electric field.

"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.

Input signal mode

Mode detection

Mode control

dbx

Output

SAP

NOISE

NRSW

FOMO

SAPC

input

Lch

Rch

MUTE

L+R

SAP

MONO

SAP

L+R

SAP

MUTE

L+R

(SAP)

L+R

(SAP)

L-R

MUTE

L+R

L-R

STEREO

MUTE

L+R

SAP

L+R

SAP

(SAP)

L+R

(SAP)

MUTE

L+R

MUTE

L+R

MONO & SAP

SAP

L+R

SAP

(SAP)

L+R

(SAP)

L-R

MUTE

L+R

STEREO & SAP

SAP

L+R

SAP

(SAP)

L+R

(SAP)

--25--

CXA1734S

Mode Control No. 2 (SAPC = 0)

Note)

(SAP) : The SAPOUT output signal is soft muted (approximately 7 dB).

The signal is soft muted when NOISE = 1.

: Don't care.

1) : SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is

inputted in the weak electric field.

"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.

Input signal mode

Mode detection

Mode control

dbx

Output

SAP

NOISE

NRSW

FOMO

SAPC

input

Lch

Rch

MUTE

L+R

MONO

MUTE

L+R

MUTE

L+R

(SAP)

L+R

(SAP)

L-R

MUTE

L+R

L-R

STEREO

MUTE

L+R

L-R

MUTE

L+R

(SAP)

L+R

(SAP)

MUTE

L+R

MUTE

L+R

SAP

MONO & SAP

SAP

L+R

SAP

MUTE

L+R

MUTE

L+R

MUTE

L+R

MUTE

L+R

L-R

MUTE

L+R

SAP

STEREO & SAP

SAP

L+R

SAP

L-R

MUTE

L+R

L-R

MUTE

L+R

ACK

DATA

HIZ

DATA(n)

DATA(n+1)

ACK

DATA(n+2)

HIZ

LSB

MSB

Address

SDA

SCL

MSB

L during Write

MSB

LSB

HIZ

ACK

Sub Address

ACK

SDA

SCL

Start Condition S

Stop Condition P

HIZ

--26--

CXA1734S

C BUS Signal

There are two I

C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signal. SDA is a bidirectional signal.

· Accordingly there are 3 values outputs, H, L and HIZ.

· I

C transfer begins with Start Condition and ends with Stop Condition.

· I

C data Write (Write from I2C controller to the IC)

Data can be transferred in 8-bit units

to be set as required.

Sub address is incremented

automatically.

--28--

CXA1734S

Input level vs. Distortion characteristics 2 (Stereo)

Input level vs. Distortion characteristics 1 (MONO)

1.0

0.1

Input level [dB]

Standard level (100%)

Input signal: MONO (Pre-emphasis on), 1 kHz

0dB=100% modulation LPF

=9V, 30kHz using LPF

Measurement point: L/R out

Distortion (%)

1.0

Input level [dB]

Standard level (100%)

Input signal: Stereo L=-R
(dbx-TVNR ON), 1kHz
0dB=100% modulation level
V

=9V, 30kHz using LPF, ST mode

Measurement point: L/R out

Input level vs. Distortion characteristics 3 (SAP)

1.0

Input level [dB]

Standard level (100%)

Input signal: SAP (dbx-TVNR ON)
1kHz, 0dB=100% modulation
level
V

=9V, 30kHz using LPF, SAP mode

Measurement: L/R out

Distortion (%)

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA1734S

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA1734S