1
CXA1782CQ/CR
E95908C78
RF Signal Processing Servo Amplifier for CD players
Description
The CXA1782CQ/CR is a bipolar IC with built-in
RF signal processing and various servo ICs. A CD
player servo can be configured by using this IC,
DSP and driver.
Features
Low operating voltage (V
CC
V
EE
= 3.0 to 11.0V)
Low power consumption (39mW, V
CC
= 3.0V)
Supports pickup of either current output, voltage
output
Automatic adjustment comparator for tracking
balance gain
Single power supply and positive/negative dual
power supplies
Applications
RF I-V amplifier, RF amplifier
Focus and tracking error amplifier
APC circuit
Mirror detection circuit
Defect detection and prevention circuits
Focus servo control
Tracking servo control
Sled servo control
Comparators of tracking adjustment for balance
and gain
Structure
Bipolar silicon monolithic IC
Absolute Maximum Ratings (Ta = 25C)
Supply voltage
V
CC
12
V
Operating temperature Topr
20 to +75
C
Storage temperature
Tstg
65 to +150
C
Allowable power dissipation
P
D
833 (CXA1782CQ) mW
457 (CXA1782CR)
mW
Recommended Operating Condition
Operating supply voltage
V
CC
V
EE
3.0 to 11.0
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXA1782CQ
48 pin QFP (Plastic)
CXA1782CR
48 pin LQFP (Plastic)
For the availability of this product, please contact the sales office.
2
CXA1782CQ/CR
Block Diagram
RF IV AMP1
FCS PHASE COMPENSATION
TRACKING
PHASE COMPENSATION
I SET
I IL DATA REGISTER INPUT SHIFT REGISTER
ADRESS.DECODER
F SET
WINDOW COMP.
2
3
4
5
6
11
12
1
7
8
9
10
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
40
APC
FE AMP
F IV AMP
TE AMP
E IV AMP
RF IV AMP2
BAL1
BAL2
BAL3
TOG1
TOG2
TOG3
LEVEL S
FOK
MIRR
DFCT
I IL
TTL
I IL
TTL
I IL
TTL
OUTPUT DECODER
TOG1 to 3
BAL1 to 3
FS1 to 4 TG1 to 2 TM1 to 7
PS1 to 4
LPF COMP
HPF COMP
TM6
TM5
TM4
TM3
TM7
TM2
TG1
TM1
DFCT
TZC COMP
FS4
DFCT
ATSC
FZC COMP
FS1
FS2
TG2
FE_BIAS
F
E
EI
V
EE
TEO
LPFI
ATSC
TEI
TZC
VC
TDFCT
FEO
FEI
FGD
FLB
FDFCT
FE_O
SRCH
FE_M
TGU
TG2
FSET
TA_M
PHD2
PHD1
LD
RF_M
PHD
RF_O
CP
RF_I
CB
CC1
CC2
FOK
SENS
C.OUT
XRST
DATA
XLT
CLK
Vcc
SL_O
ISET
SL_M
TA_O
SL_P
The switch state in Block Diagram is for initial resetting.
Switch turns to side for 1 and to side for 0 in Serial Data Truth Table.
DFCT switch turns to side when defect signal generates for DEFECT = E in Serial Data Truth Table.
TG1 switch turns to side and TG2 switch is left open when TG1 and TG2 (address 1 : D3) is 1.
3
CXA1782CQ/CR
Pin Description
Pin
No.
Symbol
I/O
Equivalent circuit
Description
1
FEO
O
Focus error amplifier output.
Connected internally to the FZC
comparator input.
2
FEI
I
3
FDFCT
I
Focus error input.
Capacitor connection pin for defect
time constant.
4
FGD
I
Ground this pin through a capacitor
when decreasing the focus servo
high-frequency gain.
5
FLB
I
External time constant setting pin
for increasing the focus servo low-
frequency.
6
FE_O
O
13
TA_O
O
16
SL_O
O
Focus drive output.
Tracking drive output.
Sled drive output.
7
FE_M
I
Focus amplifier inverted input.
147
50k
90k
7
250
6
13
16
40k
5
1
147
300
25p
174k
10k
51k
9k
147
100k
147
2
3
147
130k
4
68k
20
4
CXA1782CQ/CR
Pin
No.
Symbol
I/O
Equivalent circuit
Description
8
SRCH
I
External time constant setting pin for
generating focus servo waveform.
9
TGU
I
External time constant setting pin for
switching tracking high-frequency
gain.
10
TG2
I
External time constant setting pin for
switching tracking high-frequency
gain.
11
FSET
I
High cut-off frequency setting pin for
focus and tracking phase
compensation amplifier.
12
TA_M
I
Tracking amplifier inverted input.
14
SL_P
I
15
SL_M
I
Sled amplifier non-inverted input.
Sled amplifier inverted input.
14
147
12
147
100k
11
147k
11
15k
15k
147
50k
8
11
20k
9
110k
82k
2
10
470k
147
22
15
5
CXA1782CQ/CR
Pin
No.
Symbol
I/O
Equivalent circuit
Description
17
ISET
I
Setting pin for Focus search, Track
jump, and Sled kick current.
19
CLK
I
20
XLT
I
21
DATA
I
22
XRST
I
Serial data transfer clock input from
CPU. (no pull-up resistance)
Serial data input from CPU.
(no pull-up resistance)
Reset input; resets at Low.
(no pull-up resistance)
Latch input from CPU.
(no pull-up resistance)
23
C. OUT
O
24
SENS
O
Track number count signal output.
Outputs FZC, DFCT, TZC, gain,
balance, and others according to
the command from CPU.
25
FOK
O
Focus OK comparator output.
26
CC2
I
27
CC1
O
28
CB
I
Input for the DEFECT bottom hold
output with capacitance coupled.
DEFECT bottom hold output.
Connection pin for DEFECT bottom
hold capacitor.
28
147
147
27
147
26
147
20k
100k
25
40k
17
147
147
19
20
21
22
15
1k
23
24
147
20k
100k
6
CXA1782CQ/CR
Pin
No.
Symbol
I/O
Equivalent circuit
Description
29
CP
I
Connection pin for MIRR hold
capacitor.
MIRR comparator non-inverted
input.
30
RF_I
I
31
RF_O
O
32
RF_M
I
33
LD
O
APC amplifier output.
34
PHD
I
APC amplifier input.
35
36
PHD1
PHD2
I
I
RF I-V amplifier inverted input.
Connect these pins to the photo
diode A + C and B + D pins.
147
35
36
10k
11.6k
100
34
147
17
33
1k
10k
29
147
30
147
147
31
32
147
Input for the RF summing amplifier
output with capacitance coupled.
RF sunning amplifier output.
Eye-pattern check point.
RF summing amplifier inverted
input.
The RF amplifier gain is determined
by the resistance connected
between this pin and RFO pin.
7
CXA1782CQ/CR
Pin
No.
Symbol
I/O
Equivalent circuit
Description
37
FE_BIAS
I
Bias adjustment of focus error
amplifier.
38
39
F
E
I
I
F I-V and E I-V amplifier inverted
input.
Connect these pins to photo diodes
F and E.
40
EI
--
I-V amplifier E gain adjustment.
(When not using automatic balance
adjustment)
42
TEO
O
Tracking error amplifier output.
E-F signal is output.
43
LPFI
I
Comparator input for balance
adjustment.
(Input from TEO through LPF)
147
43
147
23k 11k
4.8k
42
12k
10k
150k
150k
164k
32k
8
37
25p
147
260k
10
12p
38
39
513
40
260k
6.8k
20.3k
102k 57k
28k
8
CXA1782CQ/CR
Pin
No.
Symbol
I/O
Equivalent circuit
Description
44
TEI
I
47
TDFCT
I
Tracking error input.
Capacitor connection pin for defect
time constant.
45
ATSC
I
46
TZC
I
48
VC
O
Window comparator input for ATSC
detection.
Tracking zero-cross comparator
input.
(V
CC
+ V
EE
)/2 DC voltage output.
10k
46
75k
147
100k
147
44
47
45
10k
1k
100k
100k
1k
48
VC
50
120
120
9
CXA1782CQ/CR
T1
T2
RF amplifier
FE amplifier
TE amplifier
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
Current consumption 1
Current consumption 2
Offset
Voltage gain
Max. output voltage-High
Max. output voltage-Low
Offset
Voltage gain 1
Voltage gain 1
Voltage gain difference
Max. output voltage-High
Max. output voltage-Low
Offset
Voltage gain F
0
Voltage gain F
1
Voltage gain F
2
Voltage gain F
3
Voltage gain E
0
Voltage gain E
1
Voltage gain E
2
1kHz input ratio
V1 = 100mV
DC
V1 = 100mV
DC
V1 = 1kHz I/O ratio
V1 = 1kHz I/O ratio
V1 = 100mV
DC
V1 = 100mV
DC
V1 = 1kHz TOG1, 2, 3: OFF
V1 = 1kHz TOG1: ON
Reference to F
0
V1 = 1kHz TOG2: ON
Reference to F
0
V1 = 1kHz TOG3: ON
Reference to F
0
V1 = 1kHz TOG1, 2, 3: OFF
V1 = 1kHz BAL1: ON
Reference to E
0
V1 = 1kHz BAL2: ON
Reference to E
0
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
18
41
31
42
10
14
20
mA
20
14
10
mA
50
0
50
25.1
28.1
31.1
mV
--
0.9
0.3
V
120
0
120
V
27.0
30.0
33.0
mV
27.0
30.0
33.0
dB
3.0
0
3.0
dB
1.0
1.3
--
dB
--
1.3
1.0
V
25
0
25
V
0.5
3.5
6.5
mV
2.33
1.83
1.33
dB
3.93
3.43
2.93
dB
6.69
6.19
5.69
dB
0.6
2.4
5.4
dB
0.1
0.4
0.7
dB
0.4
0.7
1.0
dB
Item
1
2
3
4
5
6
8
7
9
10
11
12
13
14
15
16
17
18
Measure-
ment pin
SD
RST
Measurement conditions
Min.
Typ.
Max.
Unit
SW conditions
Electrical Characteristics
(V
CC
= 1.5V, V
EE
= 1.5V, Ta = 25C)
3F
3E
3D
3B
37
36
35
1.2
1.3
--
dB
dB
Ratings
1
10
CXA1782CQ/CR
TE amplifier
APC
FCS servo
TRK servo
V1 = 1kHz BAL3: ON
Reference to E
0
V1 = 1V
DC
BAL2: ON
V1 = 1V
DC
BAL2: ON
V2 = 120mV
V2 = 145mV
V2 = 170mV
0.8mA sink
T29 + T8 (or T9)
Output gain difference between
SD = 00 and SD = 08.
V1 = 200mV
DC
V1 = 200mV
DC
Pin 1 threshold (preliminary)
T37 + T14
Output gain difference between
SD = 20 and SD = 25.
V1 = 0.5V
DC
1.08
0.5
--
900
900
180
200
100
18
49
1.0
--
640
360
185
12.25
16.1
1.0
1.38
0.6
0.6
21.0
51
1.3
1.3
500
500
225
14.6
18.1
1.3
1.68
--
0.5
480
380
1120
500
100
24
53
35
--
1.0
360
640
265
17.6
20.1
39
dB
V
V
mV
mV
mV
mV
mV
dB
dB
dB
V
V
mV
mV
mV
dB
dB
dB
V
T21
T22
T23
T24
T25
T26
T27
T28
T29
T30
T31
T32
T33
T34
T35
T36
T37
T38
T39
T40
Voltage gain E
3
Max. output voltage-High
Max. output voltage-Low
Output voltage 1
Output voltage 2
Output voltage 3
Output voltage 4
Center amplifier output
offset
DC voltage gain
FCS total gain
Feed through
Max. output voltage-High
Max. output voltage-Low
Search voltage ()
Search voltage (+)
FZC threshold
DC voltage gain
TRK total gain
Feed through
Max. output voltage-High
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
33
3F
3F
08
00
08
08
02
03
00
25
42
33
48
6
24
13
Item
1
2
3
4
5
6
8
7
9
10
11
12
13
14
15
16
17
18
Measure-
ment pin
SD
Measurement conditions
Min.
Typ.
Max.
Unit
SW conditions
Ratings
13
10
24
25
16
23
24
11
CXA1782CQ/CR
TRK Servo
Sled
MIRR
DEFECT
V1 = +0.5V
DC
Output gain difference between
SD = 20 and SD = 25.
V1 = +0.4V
DC
V1 = 0.4V
DC
Measures at C. OUT pin.
Measures at C. OUT pin.
Measures at C. OUT pin.
Measures at SENS pin.
Measures at SENS pin.
Measures at SENS pin.
Measures at SENS pin.
640
360
25
7
20
12
120
400
50
1.0
750
450
30
1.8
2.5
1.8
1.3
500
500
15
15
0
17
130
356
1.3
1.3
600
600
1.0
360
640
7
25
20
22
140
330
34
1.0
450
750
0.3
1
0.5
V
mV
mV
mV
mV
mV
mV
mV
mV
dB
dB
V
V
mV
mV
kHz
Vp-p
Vp-p
kHz
kHz
Vp-p
Vp-p
T41
T42
T43
T44
T45
T46
T47
T48
T49
T50
T51
T52
T53
T54
T55
T56
T57
T58
T59
T60
T61
T62
Max. output voltage-Low
Jump output voltage ()
Jump output voltage (+)
ATSC threshold ()
ATSC threshold (+)
TZC threshold
BAL COMP threshold
GAIN COMP threshold
FOK threshold
DC open gain
Feed through
Max. output voltage-High
Max. output voltage-Low
Kick voltage ()
Kick voltage (+)
Max. operating frequency
Min. input operating voltage
Max. input operating voltage
Min. operating frequency
Max. operating frequency
Min. input operating voltage
Max. input operating voltage
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
25
2C
28
25
25
25
30
38
25
20
25
23
22
14
10
Item
1
2
3
4
5
6
8
7
9
10
11
12
13
14
15
16
17
18
Measure-
ment pin
SD
Measurement conditions
Min.
Typ.
Max.
Unit
SW conditions
Ratings
12
CXA1782CQ/CR
Electrical Characteristics Measurement Circuit
10k
S10
0.1
47k
100k
200k
10k
S11
S12
510k
0.015
200k
100k
S13
10k
S14
5.1k
13k
60k
240k
V
EE
A
Vcc
CLK
XLT
DATA
XRST
Vcc
10k
Vcc
10k
10k
3300p
1000p
3000p
S15
10k
22k
S16
Vcc
S17
V
EE
V2
S1
10k
10k
S2
10k
390k
S3
390k
S4
A
V
EE
S18
S5
S6
S7
S8
AC
DC
V1
0.1
S9
V
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
1
FE_BIAS
F
E
EI
V
EE
TEO
LPFI
TEI
ATSC
TZC
TDFCT
VC
FEO
FEI
FDFCT
FGD
FLB
FE_O
FE_M
SRCH
TGU
TG2
FSET
TA_M
SENS
C. OUT
XRST
DATA
XLT
CLK
Vcc
ISET
SL_O
SL_M
SL_P
TA_O
PD2
PD1
PD
LD
RF_M
RF_O
RF_I
CP
CB
CC1
CC2
FOK
13
CXA1782CQ/CR
Application Circuit (Dual 5V power supplies)
0.1
680k
510k
0.015
Vcc
DSP
DSP
DSP
MICRO
COMPUTER
0.033
22k
2200p
0.1
0.1
100k
4.7
Driver
0.033
Vcc
100k
Driver
15k
22
3.3
Driver
100k
8.2k
0.015
120k
V
EE
DSP
DSP
MICRO
COMPUTER
0.01
0.033
0.01
22k
Vcc
10
100
/6.3V
1/6.3V
10H
100
500
V
EE
Vcc
V
EE
V
EE
100k 150k
0.01
0.01
BPF
0.022
0.1
10
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
1
FE_BIAS
F
E
EI
V
EE
TEO
LPFI
TEI
ATSC
TZC
TDFCT
VC
FEO
FEI
FDFCT
FGD
FLB
FE O
FE M
SRCH
TGU
TG2
FSET
TA M
SENS
C. OUT
XRST
DATA
XLT
CLK
Vcc
ISET
SL O
SL M
SL P
TA O
PD2
PD1
PD
LD
RF M
RF O
RF I
CP
CB
CC1
CC2
FOK
82k
Vcc
1k
1/0.3V
A
C
B
D
47k
F
E
Application Circuit (Single +3V power supply)
0.1
680k
510k
0.015
Vcc
DSP
DSP
DSP
MICRO
COMPUTER
0.033
22k
2200p
0.1
0.1
100k
4.7
Driver
0.033
Vcc
100k
Driver
15k
22
3.3
Driver
100k
8.2k
0.015
120k
DSP
DSP
MICRO
COMPUTER
0.01
0.033
0.01
22k
Vcc
10
100
/6.3V
1/6.3V
10H
100
500
Vcc
1k
1/0.3V
A
C
B
D
Vcc
47k
F
E
100k 150k
0.01
0.01
BPF
0.022
0.1
10
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
1
FE_BIAS
F
E
EI
V
EE
TEO
LPFI
TEI
ATSC
TZC
TDFCT
VC
FEO
FEI
FDFCT
FGD
FLB
FE O
FE M
SRCH
TGU
TG2
FSET
TA M
SENS
C. OUT
XRST
DATA
XLT
CLK
Vcc
ISET
SL O
SL M
SL P
TA O
PD2
PD1
PD
LD
RF M
RF O
RF I
CP
CB
CC1
CC2
FOK
10
Vcc
82k
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
14
CXA1782CQ/CR
Description of Functions
RF Amplifier
The photo diode currents input to the input pins (PD1 and PD2) are each I-V converted via a 58k
equivalent
resistor by the PD I-V amplifiers. these signals are added by the RF summing amplifier, and the photo diode
(A + B + C + D) current-voltage converted voltage is output to the RFO pin. An eye-pattern check can be
performed at this pin.
The low frequency component of the RFO output voltage is V
RFO
= 2.2
(V
A
+ V
B
) = 127.6k
(iPD1 + iPD2).
Focus Error Amplifier
The focus error amplifier calculates the difference between output VA and VB of the RF I-V amplifier, and
output current-voltage converted voltage of the photo diode (A + C B D).
The FEO output voltage (low frequency) is V
FEO
= 5.4
(V
A
V
B
) = (iPD2 iPD1)
315k
.
Be aware that the rotation of the focus bias volume has reversed for the usual CD RF IC.
1k
3.3
A
C
B
D
35
36
PD1
iPD1
PD2
iPD2
58k
VA
10k
VC
PD1 IV AMP
58k
VB
10k
VC
PD2 IV AMP
32
31
RF_M
RF_O
22k
VC
RF SUMMING AMP
(B + D)
(A + C)
VB
VA
32k
32k
VC
25p
87k
164k
37
25p
174k
FE AMP
1
FEO
FE_BIAS
47k
V
EE
V
CC
15
CXA1782CQ/CR
Tracking Error Amplifier
The photo diode currents input to E and F pins are each current-voltage converted by the E I-V and F I-V
amplifiers.
The CXA1782 tracking block has built-in circuits for balance and gain adjustments to enable software-based
automatic adjustment.
The balance adjustment is performed by varying the combined resistance value of the T-configured feedback
resistance at E I-V AMP.
F I-V AMP feedback resistance = R
F1
+ R
F2
+ = 403k
E I-V AMP feedback resistance = R
E1
+ R
E2
+
Vary the value of R
E3
in the formula above by using the balance adjustment switches (BAL1 to BAL3).
For the gain adjustment, the TE AMP output is resistance-divided by the gain adjustment switches (TOG1 to
TOG3), and it is output at Pin 42.
These balance and gain adjustment switches are controlled through software commands.
1k
3.3
iF
F
38
R
F1
260k
12p
VF
F I-V AMP
13k
R
F2
26k
R
F3
VC
VC
R
E1
260k
12p
VE
E I-V AMP
VC
iE
39
E
6.8k
R
E2
20.3k
102k
BAL1
57k
BAL2
28k
BAL3
VC
40
EI
R
E3
12k
10k
22k
TOG1
10k
TOG2
4.8k
TOG3
VC
TE AMP
96k
30k
30k
96k
VC
42
TEO
R
E1
x R
E2
R
E3
R
F1
x R
F2
R
F3
16
CXA1782CQ/CR
Tracking Automatic Adjustment for Gain/Balance
Balance adjustment
This adjustment is performed by routing the tracking error signal (TE signal) through the LPF, extracting the
offset DC, and comparing it to the reference level.
However, the TE signal frequency distribution ranges form DC to 2kHz. Merely sending the signal through
the LPF leaves lower frequency components, and the complete DC offset can not be extracted. To extract it,
monitor the TE signal frequency at all times, and perform adjustment only when, a frequency that can lower a
sufficient gain appears on the LPF. Use the C. OUT output to check this frequency.
Gain adjustment
This adjustment is performed by passing the TE signal through the HPF and comparing the AC component to
the reference level. The HPF signal is implemented by taking the difference between the TE signal and the
LPF component input to Pin 43.
The comparison signal is output from Pin 24 (SENS). Address 3 selects the automatic adjustment
comparator output, and HPF for data (D3) = 1 or LPF for data (D3) = 0 is selected.
The anti-shock circuit always operates in the CXA1782 so that TG1 and TG2 (address 1 : D3) should be set
to 1 for tracking adjustment to prevent this effect.
When the anti-shock function is not used, Pin 45 (ATSC) should be fixed to VC.
42
TEO
100k
150k
0.01
0.01
LPF
43
+
LPF
HPF
TZC
DFCT FZC
23
24
Balance
Gain
SENS
C. OUT
Balance OK
Gain OK
Frequency
check
Resistance
switching
-CON
LPFI
BUFFER
AMP
The CXA1782 has balance control, gain control, and comparator circuits required to perform tracking
automatic adjustment. LPF is set externally at approximately 100Hz.
17
CXA1782CQ/CR
Center Voltage Generation Circuit
(Single voltage application; Connect to GND when it's positive/negative dual power supplies.)
Maximum current is approximately 3mA. Output impedance is approximately 50
.
Vcc
30k
30k
50
VC
48
VC
V
EE
APC Circuit
When the laser diode is driven with constant current, the optical output possesses large negative temperature
characteristics. Therefore, the current must be controlled with the monitor photo diode to ensure the output
remains constant.
Vcc
100
/6.3V
10H
1
/6.3V
GND
LD
PD
V
EE
34
33
LD
PD
55k
10k
V
EE
56k
10k
10k
56k
Vcc
1k
V
EE
VREF
1.25V
18
CXA1782CQ/CR
Focus Servo
FZC
9k
51k
FE
1
2
3
4
10k
2200p
22k
FEO
FEI
100k
DFCT
FS4
Focus
phase
Compensation
68k
100k
FE_O
6
FOCUS COIL
7
FE_M
100k
17
ISET 120k
11
22
FS2
FS1
50k
50k
8
11
5
4.7
0.01
510k
0.1
FSET
FLB
40k
0.47
0.1
680k
FDFCT
FGD
SRCH
The above figure shows a block diagram of the focus servo.
Ordinarily the FE signal is input to the focus phase compensation circuit through a 68k
resistance; however,
when DFCT is detected, the FE signal is switched to pass through a low-pass filter formed by the internal
100k
resistance and the capacitance connected to Pin 3. When this DFCT prevention circuit is not used,
leave Pin 3 open. The defect switch operation can be enabled and disabled with command.
The capacitor connected between Pin 5 and GND is a time constant to raise the low frequency in the normal
playback state.
The peak frequency of the focus phase compensation is approximately 1.2kHz when a resistance of 510
is
connected to Pin 11.
The focus search height is approximately 1.1Vp-p when using the constants indicated in the above figure.
This height is inversely proportional to the resistance connected between Pin 17 and VEE. However, changing
this resistance also changes the height of the track jump and sled kick as well.
The FZC comparator inverted input is set to 15% of V
CC
and VC (Pin 48); (V
CC
VC)
15%.
510k
resistance is recommended for Pin 11.
19
CXA1782CQ/CR
Tracking Sled Servo
HPF
130mV
+
17mV
LPF
TE
42
TEO
43
BUFFER AMP
LPFI
0.01
0.01
150k
100k
44
DFCT
TEI
100k
47
TDFCT
0.47
45
ATSC
47p
330k
470k
0.047
0.022
46
TZC
TZC
9
10
TGU
TG2
0.033
470k
TG2
20k
11
510k
0.01
FSET
Tracking Phase
Compensation
10k
90k
TM4
TM3
11A
11A
12
13
100k
TRACKING
COIL
82k
15k
22
3.3
14
15
SL_P
TM2
TM6
TM5
22A
22A
100k
1k
1k
100k
ATSC
8.2k
120k
0.015
16
M
SLED MOTOR
SL_O
SL_M
TM1
680k
680k
66p
TA_M
TA_O
TG1
TM7
The above figure shows a block diagram of the tracking and sled servo.
The capacitor connected between Pins 9 and 10 is a time constant to decrease the high-frequency gain when
TG2 is OFF. The peak frequency of the tracking phase compensation is approximately 1.2kHz when a 510k
resistance connected to Pin 11. In the CXA1782, TG1 and TG2 are inter-linked switches.
To jump tracks in FWD and REV directions, turn TM3 or TM4 ON. During this time, the peak voltage applied to
the tracking coil is determined by the TM3 or TM4 current and the feedback resistance from Pin 12. To be
more specific,
Track jump peak voltage = TM3 (or TM4) current
feedback resistance value
The FWD and REV sled kick is performed by turning TM5 or TM6 ON. During this time, the peak voltage
applied to the sled motor is determined by the TM5 or TM6 current and the feedback resistance from Pin 15;
Sled kick peak voltage = TM5 ( or TM6) current
feedback resistance
The values of the current for each switch are determined by the resistance connected between Pin 17 and
VEE. When this resistance is 120k
:
TM3 ( or TM4) = 11A, and TM5 (or TM6) = 22A.
As is the case with the FE signal, the TE signal is switched to pass through a low-pass filter formed by the
internal resistance (100k
) and the capacitance connected to Pin 47.
20
CXA1782CQ/CR
Focus OK Circuit
31
30
25
RF
15k
92k
VG
54k
20k
V
CC
0.625V
C5
0.01
RF_O
RF_I
FOK
1
FOCUS OK AMP
FOCUS OK
COMPARATOR
The focus OK circuit creates the timing window okaying the focus servo from the focus search state.
The HPF output is obtained at Pin 30 from Pin 31 (RF signal), and the LPF output (opposite phase) of the
focus OK amplifier output is also obtained.
The focus OK output reverses when V
RFI
V
RFO
0.37V.
Note that, C5 determines the time constant of the HPF for the EFM comparator and mirror circuit and the LPF
of the focus OK amplifier. Ordinarily, with a C5 equal to 0.01F selected, the fc is equal to 1kHz, and block
error rate degradation brought about by RF envelope defects caused by scratched discs can be prevented.
DEFECT Circuit
After the RFI signal is reverted, two time constants, long and short, are held at bottom. The short time constant
bottom hold responds to 0.1ms or greater disc mirror defects, and the long time constant bottom hold holds the
pre-defect mirror level. By differentiating and level-shifting these constants with capacitor coupling and
comparing both signals, the mirror defect detection signal is generated.
RF_O
a
24
28
2
31
26
27
b
DEFECT AMP
CC1
CC2
SENS
CB
0.01
0.033
DEFECT SW
DEFECT COMPARATOR
DEFECT BOTTOM
HOLD
e
c
d
e
d
c
b
a
BOTTOM
HOLD (1) ;
solid Line:
CC1
DEFECT
AMP
RFO
DEFECT
BOTTOM
HOLD (2) ;
dotted Line:
CC2
H
L
21
CXA1782CQ/CR
Mirror Circuit
The mirror circuit performs peak and bottom hold after the RFI signal has been amplified.
The peak and bottom holds are both held through the use of a time constant. For the peak hold, a time
constant can follow a 30kHz traverse, and, for the bottom hold, one can follow the rotation cycle envelope
fluctuation.
The DC playback envelope signal J is obtained by amplifying the difference between the peak and bottom hold
signals H and I. Signal J has a large time constant of 2/3 its peak value, and the mirror output is obtained by
comparing it to the peak hold signal K. Accordingly, when on the disc track, the mirror output is Low; when
between tracks (mirrored portion), it is High; and when a defect is detected, it is High. The mirror hold time
constant must be sufficiently large compared with the traverse signal.
In the CXA1782, this mirror output is used only during braking operations, and no external output pin is
attached. Accordingly, when connecting DSP such as the CXD2500 with MIRR input pin, input the C. OUT
output to the MIRR input of the DSP.
RF
20k
0.033
RF_O
RF_I
CP
MIRROR
COMPARATOR
PEAK&
BOTTOM
HOLD
31
30
1.4
29
K
MIRROR HOLD AMP
J
H
I
1
LOGIC
G
MIRROR AMP
RF_O
H
L
0V
0V
0V
0V
G
(RF_I)
H
(PEAK HOLD)
I
(BOTTOM HOLD)
(MIRROR HOLD)
J
K
MIRR
22
CXA1782CQ/CR
Commands
The input data to operate this IC is configured as 8-bit data; however, below, this input data is represented by
2-digit hexadecimal numerals in the form $XX, where X is a hexadecimal numeral between 0 and F.
Commands for the CXA1782 can be broadly divided into four groups ranging in value from $0X to $3X.
1. $0X ("FZC" at SENS pin (Pin 24))
These commands are related to focus servo control.
The bit configuration is as shown below.
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
FS4
DEFECT
FS2
FS1
Four focus-servo related switches exist: FS1, FS2, FS4, and DEFECT corresponding to D0 to D3, respectively.
$00
When FS1 = 0, Pin 8 is charged to (22A 11A)
50k
= 0.55V.
If, in addition, FS2 = 0, this voltage is no longer transferred, and the output at Pin 6 becomes 0V.
$02
From the state described above, the only FS2 becomes 1. When this occurs, a negative signal is output
to Pin 6. This voltage level is obtained by equation 1 below.
(22A 11A)
50k
.
.
.
.
Equation 1
$03
From the state described above, FS1 becomes 1, and a current source of +22A is split off.
Then, a CR charge/discharge circuit is formed, and the voltage at Pin 8 decreases with the time as
shown in Fig. 1 below.
This time constant is obtained with the 50k
resistance and an external capacitor.
By alternating the commands between $02 and $03, the focus search voltage can be constructed. (Fig. 2)
$04
When the fact that the RF signal is missing is detected and the scratches on the disc are detected with
DEFECT = 0, DFCT (FS3) is turned ON.
0V
0V
$
00 02
03
02
03
02
00
Fig. 1. Voltage at Pin 8 when FS1 gose from 0
1
Fig. 2. Constructing the search voltage by alternating between $02 and $03. (Voltage at Pin 6)
resistance between Pins 6 and 7
50k
23
CXA1782CQ/CR
The instant the signal is brought into focus.
$08
$03
($00)
$02
(20ms) (200ms)
Drive voltage
Focus error
SENS pin
(FZC)
Focus OK
1-1. FS4
This switch is provided between the focus error input (Pin 2) and the focus phase compensation, and is in
charge of turning the focus servo ON and OFF.
$00
$08
Focus OFF
Focus ON
1-2. Procedure of focus activation
For description, suppose that the polarity is as described below.
a) The lens is searching the disc from far to near;
b) The output voltage (Pin 6) is changing from negative to positive; and
c) The focus S-curve is varying as shown below.
The focus servo is activated at the operating point indicated by A in Fig. 3. Ordinarily, focus searching and the
turning the focus servo switch ON are performed during the focus S-curve transits the point A indicated in Fig. 3.
To prevent misoperation, this signal is ANDed with the focus OK signal.
In this IC, FZC (Focus Zero Cross) signal is output from the SENS pin (Pin 24) as the point A transit signal. In
addition, focus OK is output as a signal indicating that the signal is in focus (can be in focus in this case).
Following the line of the above description, focusing can be well obtained by observing the following timing
chart.
The broken lines in the figure
indicate the voltage assuming
the signal is not in focus.
t
A
Fig. 3. S-curve
Fig. 4. Focus ON timing chart
24
CXA1782CQ/CR
1-3. SENS pin (Pin 24)
The output of the SENS pin differs depending on the input data as shown below.
$0X: FZC
$1X: DEFECT
$2X: TZC
$3X: Automatic adjustment comparator output
$4X to 7X: HIGH-Z
2. $1X ("DEFECT" at SENS pin (Pin 24))
These commands deal with switching TG1/TG2, brake circuit ON/OFF, and the sled kick output.
The bit configuration is as follows
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
TG1, TG2 Break
Sled kick
circuit
height
ON/OFF
ON/OFF
TG1, TG2
The purpose of these switches is to switch the tracking servo gain Up/Normal. TG1 and TG2 are interlinked
switches. The brake circuit (TM7) is to prevent the occurrence of such frequently occurring phenomena as
extremely degraded actuator settling due to the servo motor exceeding the linear range causing what should
be a 100-track jump to fall back down to a 10-track jump after a 100 or 10-track jump has been performed. To
do this, when the actuator travels radially; that is, when it traverses from the inner track to the outer track of
the disc and vice versa, the brake circuit utilizes the fact that the phase relationship between the RF envelope
and the tracking error is 180out-of-phase to cut the unneeded portion of the tracking error and apply braking.
Note that the time from the High to Low transition of FZC to the time command $08 is asserted must be
minimized. To do this, the software sequence shown in B is better than the sequence shown in A.
FZC
?
NO
YES
F. OK ?
NO
Transfer $08
Latch
FZC
?
NO
F. OK ?
NO
Transfer $08
Latch
(A)
(B)
YES
YES
YES
Fig. 5. Poor and good software command sequences
D1
(PS1)
0
0
1
1
D0
(PS0)
0
1
0
1
1
2
3
4
Sled kick height
Relative
value
25
CXA1782CQ/CR
Envelope Detection
Waveform Shaping
Waveform Shaping
Edge Detection
30
46
[
B]
[
E]
RF_I
(TZC)
Tracking error
CXA1782
(Latch)
Q
D
CK
(MIRR)
[
C]
[
F]
[
G]
BRK
D2
TM7
Low: open
High: make
[
A]
[
D]
Fig. 6. TMI movement during braking operation
0V
("MIRR")
("TZC")
Braking is
applied from
here.
[
A]
[
B]
[
C]
[
D]
[
E]
[
F]
[
G]
[
H]
From outer to inner track
From inner to outer track
Fig. 7. Internal waveform
3. $2X ("TZC" at SENS pin (Pin 24))
These commands deal with turning the tracking servo and sled servo ON/OFF, and creating the jump pulse
and fast forward pulse during access operations.
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
Tracking
Sled
control
control
00: OFF
00: OFF
01: Servo ON
01: Servo ON
10: F-JUMP
10: F-FAST FORWARD
11: R-JUMP
11: R-FAST FORWARD
TM1, TM3, TM4
TM2, TM5, TM6
26
CXA1782CQ/CR
4. $3X
These commands control the balance and gain control circuit switches used during automatic tracking
adjustment.
In the initial resetting state, BAL1 to BAL3 switches are OFF and TOG1 to TOG3 switches are ON.
Balance adjustment
The balance adjustment switches BAL1 to BAL3 can be controlled by setting D3 = 0. The switches are set
using D0 to D2.
At this time, the balance adjustment LPF comparator output is selected at the SENS pin.
Data is set by specifying switch conditions D0 to D2 and sending a latch pulse with D3 = 0.
Sending a latch pulse with D3 = 1 does not change the balance switch settings.
START
C. OUT
Is the frequency
high enough ?
SENS output
Balance OK ?
Adjustment Completed
BAL1 to BAL3
Switch Control
YES
NO
Gain adjustment
The gain adjustment switches TOG1 to TOG3 can be controlled by setting D3 = 1. These switches are set
using D0 to D2. At this time, the balance adjustment HPF comparator output is selected for SENS pin.
In a fashion similar to the method used with the balance adjustment, set the data by sending a latch pulse
with D3 = 1, specifying the switch conditions D0 to D2.
START
SENS
GAIN OK ?
Adjustment Completed
TOG1 to TOG3
Switch control
YES
NO
Balance adjustment
Gain adjustment
27
CXA1782CQ/CR
CPU Serial Interface Timing Chart
t
WCK
D0
D1
D2
D3
D4
D5
D6
D7
D0
t
WCK
t
SU
1/fck
t
h
t
CD
t
WL
t
D
DATA
CLK
XLT
Item
Clock frequency
Clock pulse width
Setup time
Hold time
Delay time
Latch pulse width
Data transfer interval
Symbol
fck
fwck
t
su
t
h
t
D
t
WL
t
CD
Min.
500
500
500
500
1000
1000
Type.
Max.
Unit
MHz
ns
ns
ns
ns
ns
ns
1
(V
CC
= 3.0V)
System Control
Focus Control
Tracking Control
Tracking Mode
Select
D7 D6 D5 D4
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
FS4
Focus
ON = 1, OFF = 0
TG1, TG2
ON = 1, OFF = 0
DEFECT (FS3)
Disable = 1
Enable = 0
Brake
ON = 1, OFF = 0
FS2
Search
ON = 1, OFF = 0
Sled
Kick + 2
FS1
Search
Up = 1, Down = 0
Sled
Kick + 1
FZC
DEFECT
TZC
Gain/Bal
Tracking Mode
1
Sled Mode
2
Automatic tracking adjustment mode
ADRESS
D3
D2
D1
D0
DATA
SENS
output
1
TRACKING MODE
FWD JUMP
REV JUMP
D3
0
0
1
1
D2
0
1
0
1
OFF
ON
2
SLED MODE
FWD MOVE
REV MOVE
D1
0
0
1
1
D0
0
1
0
1
OFF
ON
Item
28
CXA1782CQ/CR
Serial Data Truth Table
FOCUS CONTROL
Hex
Functions
FS = 4321
FS4
DEFECT
FS2
FS1
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
Serial Data
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 1 0
0 0 0 0 0 0 1 1
0 0 0 0 0 1 0 0
0 0 0 0 0 1 0 1
0 0 0 0 0 1 1 0
0 0 0 0 0 1 1 1
0 0 0 0 1 0 0 0
0 0 0 0 1 0 0 1
0 0 0 0 1 0 1 0
0 0 0 0 1 0 1 1
0 0 0 0 1 1 0 0
0 0 0 0 1 1 0 1
0 0 0 0 1 1 1 0
0 0 0 0 1 1 1 1
0
E
0
0
0
E
0
1
0
E
1
0
0
E
1
1
0
D
0
0
0
D
0
1
0
D
1
0
0
D
1
1
1
E
0
0
1
E
0
1
1
E
1
0
1
E
1
1
1
D
0
0
1
D
0
1
1
D
1
0
1
D
1
1
DEFECT
E: enable
D: disable
TRACKING MODE
TM = 6 5 4 3 2 1
Hex
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
$2B
$2C
$2D
$2E
$2F
0 0 1 0 0 0 0 0
0 0 1 0 0 0 0 1
0 0 1 0 0 0 1 0
0 0 1 0 0 0 1 1
0 0 1 0 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 0 0 1 1 0
0 0 1 0 0 1 1 1
0 0 1 0 1 0 0 0
0 0 1 0 1 0 0 1
0 0 1 0 1 0 1 0
0 0 1 0 1 0 1 1
0 0 1 0 1 1 0 0
0 0 1 0 1 1 0 1
0 0 1 0 1 1 1 0
0 0 1 0 1 1 1 1
0 0 0 0 0 0
0 0 0 0 1 0
0 1 0 0 0 0
1 0 0 0 0 0
0 0 0 0 0 1
0 0 0 0 1 1
0 1 0 0 0 1
1 0 0 0 0 1
0 0 0 1 0 0
0 0 0 1 1 0
0 1 0 1 0 0
1 0 0 1 0 0
0 0 1 0 0 0
0 0 1 0 1 0
0 1 1 0 0 0
1 0 1 0 0 0
29
CXA1782CQ/CR
Automatic
adjustment mode
TOG SW
3 2 1
BAL SW
3 2 1
Hex
$30
$31
$32
$33
$34
$35
$36
$37
$38
$39
$3A
$3B
$3C
$3D
$3E
$3F
0 0 1 1 0 0 0 0
0 0 1 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 1 0 0 1 1
0 0 1 1 0 1 0 0
0 0 1 1 0 1 0 1
0 0 1 1 0 1 1 0
0 0 1 1 0 1 1 1
0 0 1 1 1 0 0 0
0 0 1 1 1 0 0 1
0 0 1 1 1 0 1 0
0 0 1 1 1 0 1 1
0 0 1 1 1 1 0 0
0 0 1 1 1 1 0 1
0 0 1 1 1 1 1 0
0 0 1 1 1 1 1 1
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
DATA D3 = 0: Balance switch setting
DATA D3 = 1: Gain switch setting
Note) 0 means OFF and 1 means ON for TOG SW and BAL SW. These are not equal to the setting values of
each bit for serial data.
Initial State (resetting state)
Item
Focus Control
Tracking Control
Tracking Mode
Select
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
ADDRESS
DATA
HEXADECIMAL
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 1
1 0 0 0
$00
$10
$20
$37
$38
The above data means the following operation modes.
Focus Control
Focus off, Defect enable, Focus Search off, Focus Search down
Tracking Control
TG1 TG2 off, Brake off, Sled Kick + 2 off, Sled Kick + 1 off
Tracking Mode
Tracking off, Sled off
Select
Tracking gain
min. (TOG SW: 1 1 1)
Tracking balance: RE3
max. (TBAL SW: 0 0 0)
30
CXA1782CQ/CR
6. Sled amplifier
The sled amplifier may oscillate when used by the buffer amplifier. Use with a gain of approximately 20dB.
Sled/Tracking internal phase compensation and reference design material
Notes on Operation
1. FSET pin
The FSET pin determines the fc for the focus and tracking high-frequency phase compensation.
2. ISET pin
ISET current = 1.27V/R
= Focus search current
= Tracking jump current
= Sled kick current ($1X: PS1 = PS0 = 0)
Use the setting resistance within the range of 120k
to 240k
. If the resistance value is out of this range,
the oscillation may be occurred in the ISET block.
3. FE (focus error)/TE (tracking error) gain changing method
1) High gain: Resistance between FE pins (pins 6 and 7) 100k
Large
Resistance between TE pins (pins 12 and 13) 100k
Large
2) Low gain: A signal, whose resistance is divided between Pins 1 and 2, is input to FE. The internal gain
adjustment circuit is used for TE.
4. Input voltage at Pins 19 to 22 of the microcomputer interface should be as follows:
V
IH
V
CC
90% or more
V
IL
V
CC
10% or less
5. Focus OK circuit
1) Refer to the "Description of Operation" for the time constant setting of the focus OK amplifier LPF and the
mirror amplifier HPF.
V
CC
20k
40k
100k
V
EE
V
EE
25
R
L
FOK
V
CC
The FOK and comparator output are as follows:
Output voltage High: V
FOKH
near V
CC
Output voltage Low: V
FOKL
Vsat (NPN)
Item
SD
Measurement pin
Conditions
Typ.
Unit
1.2kHz gain
1.2kHz phase
1.2kHz gain
1.2kHz phase
2.7kHz gain
2.7kHz phase
08
08
25
25
25
13
25
13
6
C
FLB
= 0.1F
C
FGD
= 0.1F
21.5
63
13
125
26.5
130
dB
deg
dB
deg
dB
deg
C
TGU
= 0.1F
13
FCS
TRK
1
2
31
CXA1782CQ/CR
Package Outline
Unit: mm
CXA1782CQ
SONY CODE
EIAJ CODE
JEDEC CODE
M
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY RESIN
SOLDER / PALLADIUM
PLATING
COPPER / 42 ALLOY
48PIN QFP (PLASTIC)
15.3 0.4
12.0 0.1
+ 0.4
0.8
0.3 0.1
+ 0.15
0.12
13
24
25
36
37
48
1
12
2.2 0.15
+ 0.35
0.9
0.2
0.1 0.1
+ 0.2
13.5
0.15
0.15 0.05
+ 0.1
QFP-48P-L04
QFP048-P-1212-B
0.7g
CXA1782CR
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY / PHENOL RESIN
SOLDER PLATING
42 ALLOY
PACKAGE STRUCTURE
48PIN LQFP (PLASTIC)
9.0 0.2
7.0 0.1
1
12
13
24
25
36
37
48
(0.22)
0.18 0.03
+ 0.08
0.5 0.08
(8.0)
0.5
0.2
0.127 0.02
+ 0.05
0.1 0.1
0.5
0.2
A
1.5 0.1
+ 0.2
0 to 10
DETAIL A
0.2g
LQFP-48P-L01
QFP048-P-0707-A
0.1
NOTE: Dimension "
" does not include mold protrusion.
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
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