Description

The CXA1854AR is an IC designed exclusively to

drive color LCD panels LCX009AK/AKB/LCX005BK/

BKB. This IC greatly reduces the number of circuits

and parts required to drive LCD panels by

incorporating RGB decoder functions for video

signals, driver functions, and a timing generator for

driving panels onto a single chip.

Features

· Color LCD panels

LCX009AK/AKB/LCX005BK/BKB driver

· Both NTSC/PAL compatible

· Supports composite inputs, Y/C inputs and Y/color

difference inputs

· Band-pass filter, trap and delay line

· Sharpness function

· 2-point

compensation circuits

· R, B output delay time adjustment circuit

(supports both right and left inversion)

· Polarity reversed circuit / line inverted mode

· Supports external RGB input

· Supports line inversion

· Supports AC drive for LCD panel during no signal

Applications

· Color LCD viewfinders

· Liquid crystal projectors

· Industrial monitors

Structure

Bipolar CMOS IC

Absolute Maximum Ratings (Ta = 25°C)

· Supply voltage

1 GND

· Supply voltage

2 GND

· Supply voltage

· Analog input pin voltage

VINA

0.3 to V

· Digital input pin voltage

VIND

0.3 to V

+ 0.3 V

· Operating temperature range

Topr

15 to +70

°C

· Storage temperature range

Tstg

40 to +150

°C

· Allowable power dissipation

PD (Ta

70°C)

400

Operating conditions

· Supply voltage

1 GND

4.6 to 5.3

· Supply voltage

2 GND

11.0 to 13.0

· Supply voltage

LCX009 mode V

4.5 to 5.5

LCX005 mode V

2.7 to 5.5

CXA1854AR

E95X01A73

Decoder/Driver/Timing Generator for Color LCD Panels

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

64 pin LQFP (Plastic)

For the availability of this product, please contact the sales office.

CXA1854AR

Block Diagram

DECODER &

H-TIMING

PULSE GEN

V-POS

RESET GEN

V-CTL

DECODER

V-POS

COUNTER

H-CTL

DECODER

PLL

COUNTER

AUX-V

COUNTER

DECODER

H-POS

COUNTER

V-CTL

COUNTER

FIELD & LINE

CTL

PAL PULSE

ELIM &

MODE SEL

POL SW

SUB

BRIGHT

RGB GAIN

GAMMA

DEMOD

LPF

MATRIX

CONTRAST

SUB

CONTRAST

EXT SW

BRIGHT

S/H

INT/EXT

CLAMP

PAL ID

PAL SW

RESET

APC

VXO

HUE

ACC DET

KILLER

FILT CAL

AGG DET

COLOR

CONT

BPF

PIC CONT

AGC

DL 2

DL 1

TRAP

CLAMP

ACC AMP

SYNC SEP

H. FILTER

HALF-H

KILLER

H-SYNC DET

H-SKEW DET

MODE

SELECT

PLL PHASE

COMP

PULSE GEN

V-TIMING

TEST

S/R

1/7

V-SYNC SEP

buf

REG.

MASTER

SUB

BGP

CLP

BLK

EQP

XCLR

REGV

R G B

YC/YRB/COMP

SPAL/DPAL/NTSC

SH1

SH2

SH3

SH4

FRP

+5V

+12V

+5V

GND2

1
2

B-YIN

R-YIN

COUT

HUE/RST

COLOR

XVXO

R-BRT

B-BRT

RGB-GAIN

GAMMA2

GAMMA1

BRIGHT

CONTRAST

CIN

R-GAIN

B-GAIN

TEST5

HCK1

HCK2

HST1

TEST4

CLR

VCK1

VCK2

VST1

TEST3

SLCK

TEST0

TEST1

TEST2

CKO

CKI

RPD

EXT-B

EXT-G

EXT-R

MODE2

MODE1

GND1

PICT

AGCTC

AGCADJ

YIN

SYNCIN

RGT

TEST6

TEST7

TEST8

GND2

R OUT

FB R

G OUT

FB G

B OUT

FB B

BLKLIM

REG

GND1

CXA1854AR

Pin Description

(H: Pull up, M: Intermediate setting, L: Pull down)

Sync input

Y signal input

AGC level adjustment

AGC time constant

Y signal frequency characteristics adjustment

Analog 5V GND

Switches between NTSC (H), DPAL

(M) and SPAL

(L)

Switches between composite (H), Y/color difference (M) and YC input (L)

External digital input R (input conditions noted separately)

External digital input G (input conditions noted separately)

External digital input B (input conditions noted separately)

Phase comparator output

Digital GND

Oscillation cell input

Oscillation cell output

Test

Switches between LCX005BK (H) and LCX009AK (L)

Leave this pin open.

V start pulse 1 output

V clock pulse 2 output

V clock pulse 1 output

EN pulse output

CLR pulse output

Leave this pin open.

H start pulse 1 output

H clock pulse 2 output

H clock pulse 1 output

HD pulse output

VD pulse output

Leave this pin open.

SYNC IN

Y IN

AGCADJ

AGCTC

PICT

GND1

MODE1

MODE2

EXT-R

EXT-G

EXT-B

RPD

CKI

CKO

TEST2

TEST1

TEST0

SLCK

TEST3

VST1

VCK2

VCK1

CLR

TEST4

HST1

HCK2

HCK1

TEST5

DPAL supports demodulation methods which use an external delay line during demodulation; SPAL supports

methods which internally process chroma demodulation.

No.

Symbol

I/O

Description

Input pin for

open status

CXA1854AR

No.

Digital 5V power supply

Switches between Normal scan (H) and Reverse scan (L)

Leave this pin open.

Analog 12V GND

R output

R signal DC voltage feedback input

G output

G signal DC voltage feedback input

B output

B signal DC voltage feedback input

Analog 12V power supply

Black peak limiter level adjustment

Analog 5V power supply

Constant voltage capacitor connection

B-Y demodulator input (or B-Y/color difference signal input)

R-Y demodulator input (or R-Y/color difference signal input)

Chroma signal output (for PAL 1HDL)

Hue adjustment/system reset

Color adjustment

VXO crystal oscillator connection

R brightness adjustment

B brightness adjustment

RGB gain adjustment

2 adjustment

1 adjustment

Brightness adjustment

Contrast adjustment

Chroma signal input

R gain adjustment

B gain adjustment

RGT

TEST6

TEST7

TEST8

GND2

R OUT

FB R

G OUT

FB G

B OUT

FB B

BLKLIM

REG

B-YIN

R-YIN

COUT

HUE/RST

COLOR

XVXO

R-BRT

B-BRT

RGB-GAIN

GAMMA2

GAMMA1

BRIGHT

CONTRAST

CIN

R-GAIN

B-GAIN

Symbol

I/O

Description

Input pin for

open status

CXA1854AR

Analog Block Pin Description

SYNC IN

Sync input.
Normally inputs the Y signal.
The standard signal input level
is 0.5Vp-p (up to 100% white
level from the sync chip).

200

50p

GND1

YIN

3.2V

Y signal input.
The standard signal input level
is 0.5Vp-p (up to 100% white
level from the sync chip).
Input at low impedance (75

less).

50µA

GND1

AGCADJ

1/2

AGC gain adjustment pin.

GND1

40k

2.5V

AGCTC

AGC detection filter connection.

GND1

20k

50µA

PICT

1/2

Adjusts frequency
characteristics of luminance
signal.
Increasing the voltage
emphasizes contours.

GND1

47k

2.5V

50µA

No.

Symbol

Pin voltage

Equivalent circuit

Description

CXA1854AR

EXT-R

EXT-G

EXT-B

R OUT

G OUT

B OUT

FB R

FB G

FB B

External digital signal input.
There are two threshold
values: Vth1 (approximately
1.2V) and Vth2 (approximately
2.2V). When one of the EXT-
RGB signals exceeds Vth1, all
of the RGB outputs go to
black level (black side clip
level); when an input exceeds
Vth2, only the corresponding
output goes to white level
(white side limiter level).

RGB primary color signal
output.

Smoothing capacitor
connection for the feedback
circuit of RGB output DC level
control.
Use a low-leakage capacitor
because of high impedance.

GND1

200

GND2

BLKLIM

Sets the RGB output amplitude
(black-black) clip level.

GND1

50k

REG

4.2V

Smoothing capacitor
connection for the internally
generated constant voltage
source circuit.
Connect a capacitor of 1µF or
more.

GND1

60k

40k

No.

Symbol

Pin voltage

Equivalent circuit

Description

CXA1854AR

B-YIN

R-YIN

Color difference demodulation
circuit inputs during DPAL
mode.
Leave this pin open for NTSC.
Color difference signal is input
respectively when Y/color
difference input. (Standard
input is 0.15Vp-p.)
At this time, the bias is 3.5V.

200

GND1

50µA

COUT

2.3V

Color adjusted chroma signal
is output.
When taking the chroma
signal, connect to GND with a
load resistor (approximately
5k

GND1

50µA

HUE/RST

3.2V

Color phase adjustment pin
during NTSC.
Use for detective axis
adjustment of the R-Y/B-Y
axes during SPAL.
Also doubles as the reset pin.
The system is reset when this
pin is connected to GND.

GND1

100k

50µA

12k

3.2V

COLOR

3.2V

Color adjustment.

GND1

100k

50µA

25k

3.2V

XVXO

3.5V

Crystal oscillator connection.

GND1

500

No.

Symbol

Pin voltage

Equivalent circuit

Description

CXA1854AR

RBRT

BBRT

1/2

Fine adjustment for R and B
signal brightness.

GND1

47k

2.5V

RGB-GAIN

1/2

Adjusts RGB output amplitude
gain.

GND1

47k

2.5V

GAMMA2

1/2

Adjusts voltage gain change
point

GND1

47k

2.5V

GAMMA1

1/2

Adjusts voltage gain change
point

GND1

47k

2.5V

BRIGHT

1/2

RGB output brightness
adjustment. It does not
influence the

compensation

curve.

GND1

47k

2.5V

No.

Symbol

Pin voltage

Equivalent circuit

Description

CXA1854AR

Setting Conditions for Measuring Electrical Characteristics

When measuring the DC characteristics, the TG block must be horizontally synchronized by performing Setting 2.

Setting 2 must also be performed when measuring the AC characteristics. When measuring items with bands

greater than 2MHz such as the Y frequency response or sharpness characteristics, settings 1 and 3 must also

be performed and measurements made with the sample-and-hold circuit set to through status.

Setting 1. System reset

After turning on the power, set SW52 to ON and start up V52 from GND in order to activate the

timing controller system reset. (See Fig. 1-1.)

Setting 2. Horizontal AFC adjustment

Input SIG6 (VL = 0mV) to (A) and adjust VR12 so that WL and WH of the TP12 output waveform are

the same. (See Fig. 1-2.)

Setting 3. S/H off

Input the signals shown in Fig. 1-3 to Pins 16, 17, 18 and 19 in order to set the sample-and-hold

circuit to through status.

V52 (RESET)

> 10µs

SIG6

TP12

WL = WH

Fig. 1-1. System reset

Fig. 1-2. Horizontal AFC adjustment

GND

Pin 19

Pin 18

Pin 17

Pin 16

Fig. 1-3. S/H off input pattern

CXA1854AR

Electrical Characteristics DC Characteristics (1)

Unless otherwise specified, Setting 2 and the following setting conditions are required.

1 = 5.0V, V

2 = 12.0V, GND1 = GND2 = GND, V

= 5.0V, V

= GND

V3, V5, V46, V55, V56, V57, V58, V59, V60, V61, V63, V64 = 2.5V

V52, V53 = 3.2V

SW3, SW5, SW46, SW52, SW53, SW55, SW56, SW57, SW58, SW59, SW60, SW61, SW63, SW64 = ON

Set SW7, SW8, SW9, SW10, SW11 and SW19 are setting A.

Input SIG5 to (A) and SIG3 (0dB) to (B).
Measure the I

1 current value.

COMP input mode

Input SIG5 to (A) and SIG3 (0dB) to (B).
Set SW8 to C.
Measure the I

1 current value.

Y/C input mode

Input SIG5 to (A) and SIG5 to (F) and (G).
Set SW8 to B.
Measure the I

1 current value.

Y/color difference input mode

Input SIG5 to (A) and SIG3 (0dB) to (B).
Measure the I

2 current value.

Input SIG5 to (A) and SIG3 (0dB) to (B).
Measure the I

current value.

LCX009 mode

Input SIG5 to (A) and SIG3 (0dB) to (B).
Set SW19 to B.
Measure the I

current value.

LCX005 mode

Input SIG5 to (A) and SIG3 (0dB) to (B).
Set SW19 to B.

= 3.0V

Measure the I

current value.

LCX005 mode

42.5

5.5

10.5

4.5

Power supply characteristics

Current
consumption V

Item

Symbol

Conditions

Min. Typ. Max. Unit

CXA1854AR

Input pin with pull-up resistor

VIN = V

Input pin with pull-down resistor

VIN = V

IOH = 2mA

= 5.0V

= 3.0V

= 5.0V

= 3.0V

= 5.0V

= 3.0V

= 5.0V

= 3.0V

240

144

0.8

1.0

100

240

144

µA

II1

II2

VOH1

Digital block I/O characteristics

Input current 1

Input current 2

High level output
voltage
Output pins except
CKO and RPD

IOH = 3mA

IOL = 3mA

IOH = 1mA

IOL = 1.5mA

High impedance status
VOUT = V

or VOUT = V

CMOS input cell

MODE M

L level threshold

SW7, SW8 = B

MODE M

H level threshold

SW7, SW8 = B

0.5V

1.2

0.7V

0.2V

0.6V

0.3V

0.7V

0.5V

1.0

0.3V

0.4V

0.8V

µA

VOH2

VOL2

VOH3

VOL3

IOFF

VIH

VIL

MDTHL

MDTHH

High level output
voltage
CKO pin

Low level output
voltage
CKO pin

High level output
voltage
RPD pin

Low level output
voltage
RPD pin

Output off leak
current
RPD pin

High level input
voltage
SLCK and RGT pins

Low level input
voltage
SLCK and RGT pins

Ternary input
switching
threshold voltage
(MODE1/MODE2)

Low level output
voltage
Output pins except
CKO and RPD

VOL11

IOL = 2mA

0.5

0.6

VOL12

IOL = 500µA

0.3

Input pins with pull-up resistors: RGT, TEST6, TEST7, TEST8

Input pins with pull-down resistors: SLCK, TEST0, TEST1, TEST2, TEST5

Output pins except CKO and RPD: HD, VD, VST1, VCK1, VCK2, CLR, EN, HST1, HCK1, HCK2, TEST3,

TEST4

Item

Symbol

Conditions

Min. Typ. Max. Unit

CXA1854AR

Electrical Characteristics AC Characteristics (1)

Unless otherwise specified, Setting 2 and the following setting conditions are required.

Vcc1 = 5.0V, Vcc2 = 12.0V, GND1 = GND2 = GND, (V

= 5.0V, V

= GND)

V5, V55, V56, V57, V60, V61, V63, V64 = 2.5V V3, V58 = 0V V46, V59 = 5.0V

V52, V53 = 3.2V

SW3, SW5, SW46, SW52, SW53, SW55, SW56, SW57, SW58, SW59, SW60, SW61, SW63, SW64 = ON

Set SW7, SW8, SW9, SW10, SW11 and SW19 are setting A.

Unless otherwise specified, measure the non-reversed outputs for TP39, TP41 and TP43.

Input SIG5 to (A) and measure the ratio between the
output amplitude (white-black) and input amplitude at
TP41.

Assume the output amplitude at
TP41 when SIG2 (0dB, no burst,
100kHz) is input to (A) as 0dB. Vary
the frequency of the input signal to
obtain the frequency with an output
amplitude of 3dB. Settings 1 and 3
are required.

Assume the output amplitude at TP41 when SIG8
(100kHz) is input to (A) as 0dB. Obtain the output
amplitude ratio for the input SIG8 (2.0MHz).
V5 = 4.0V
Settings 1 and 3 are required.

Composite input

Assume the output amplitude at TP41 when SIG8
(100kHz) is input to (A) as 0dB. Obtain the output
amplitude ratio for the input SIG8 (2.5MHz).
V5 = 4.0V, SW8 = C
Settings 1 and 3 are required.

Y/C input

Assume the output amplitude at TP41 when SIG8
(100kHz) is input to (A) as 0dB. Obtain the output
amplitude ratio for the input SIG8 (2.0MHz).
V5 = 0V
Settings 1 and 3 are required.

Composite input

Assume the output amplitude at TP41 when SIG8
(100kHz) is input to (A) as 0dB. Obtain the output
amplitude ratio for the input SIG8 (2.5MHz).
V5 = 0V, SW8 = C
Settings 1 and 3 are required.

Y/C input

13.5

5.0

2.5

3.0

16.5

19.5

MHz

FCYYC

FCYCMN

FCYCMP

GSHPMXC

GSHPMXY

GSHPMNC

GSHPMNY

Y signal block

Video maximum
gain

Y signal frequency

Characteristics

Sharpness
characteristics
MAX

Sharpness
characteristics
MIN

Y/C input,
SW8 = C

Composite input
(NTSC)

Composite input
(PAL), SW7 = C

Item

Symbol

Conditions

Min. Typ. Max. Unit

CXA1854AR

Adjust the output amplitude at TP41 when SIG1 (APL:
50%) is input to (A) to 1.5Vp-p with V61. Assume this as
0 dB, and obtain the TP41 output amplitude ratio when
input SIG1 (APL: 90%) is input.
V3 = 2.5V, V60 = 3.5V

Adjust the output amplitude at TP41 when SIG1 (APL:
50%) is input to (A) to 1.5Vp-p with V61. Assume this as
0dB, and obtain the TP41 output amplitude ratio when
input SIG1 (APL: 10%) is input.
V3 = 2.5V, V60 = 3.5V

Input SIG5 to (A) and obtain the ratio between the TP41
output amplitude when V61 = 2.5V and the TP41 output
amplitude when V61 = 5V.

Input SIG5 to (A) and obtain the ratio between the TP41
output amplitude when V61 = 2.5V and the TP41 output
amplitude when V61 = 1V.

Input SIG3 (0dB) to (A) and (B). Adjust the chroma signal
phase so that the amplitude (black white) at TP43 is at a
maximum. Using a spectrum analyzer, measure the input
and the 3.58MHz or 4.43MHz component, and obtain
CRRLK = 150mV

d/20

using their difference

SW7 = A for NTSC measurement, and C for PAL
measurement.

Input SIG6 (VL = 150mV) to (A).
Measure the delay time from the
rising edge of the input signal to the
rising edge of the non-reversed
output.
V5 = 2V

2.5

400

780

760

250

630

610

550

930

910

mVpp

GAPL90

GAPL10

GCNTMX

GCNTMN

CRRLK

TDYYC

TDYCMN

TDYCMP

APL = 90%

APL = 10%

Contrast
characteristics
MAX

Contrast
characteristics MIN

Carrier leak
(residual carrier)

Y signal I/O delay
time

Y/C input
SW8 = C

Composite input
(NTSC)

Composite input
(PAL), SW7 = C

AGC characteristics

Item

Symbol

Conditions

Min. Typ. Max. Unit

CXA1854AR

Input SIG6 (VL = 0mV) to (A) and SIG3
(0dB/+6dB/20dB, 3.58MHz burst/chroma
phase = 180°, or 4.43MHz burst/chroma
phase = ±135°) to (B). Measure the output
amplitude at TP51, assuming the output
corresponding to 0dB, +6dB and 20dB as
V0, V1 and V2, respectively.
ACC1 = 20log (V1/V0)
ACC2 = 20log (V2/V0)

Input SIG6 (VL = 0mV) to (A) and SIG3
(0dB, 3.58MHz burst/chroma phase = 180°,
or 4.43MHz burst/chroma phase = ±135°) to
(B), and measure the output amplitude at
TP43. Changing the SIG3 burst frequency,
mesure the frequency fl which TP43 output
changes (the killer mode is canceled).
(The crystal parallel floating capacitance is
2pF or less)
NTSC: FAPCN = fl 3579545Hz
PAL: FAPCP = fl 4433619Hz

Input SIG6 (VL = 0mV) to (A) and SIG3 (0dB, 3.58MHz
burst/chroma phase = 180°) to (B). Assume the chroma
amplitude when V53 = 3.2V, 5V and 2.1V as V0, V1
and V2, respectively, and calculate GCOLMX = 20log
(V1/V0) and GCOLMN = 20log (V2/V0).

Input SIG6 (VL = 0mV) to (A) and SIG3 (0 dB) to (B).
Assume the phase at which the output amplitude at TP43
reaches a minimum when V53 = 3.2V, 5V and 1.6V as

1 and

2, respectively, and calculate TNTMX

0 and TNTMN =

Input SIG6 (VL = 0mV) to (A) and SIG3
(level variable, 3.58MHz burst/chroma
phase = 180°, or 4.43MHz burst/chroma
phase = ±135°) to (B), and measure the
output amplitude at TP43. Gradually reduce
the SIG3 amplitude and measure the level
at which the killer operation is activated.

350

5.5

deg

350

ACC1N

ACC1P

ACC2N

ACC2P

FAPCNU

FAPCND

FAPCPU

FAPCPD

GCOLMX

GCOLMN

TNTMX

TNTMN

ACKN

ACKP

Chroma signal block

ACC amplitude
characteristics 1

ACC amplitude
characteristics 2

APC pull-in range

Color adjustment
characteristics MAX

Color adjustment
characteristics MIN

HUE adjustment
range MAX

HUE adjustment
range MIN

Killer operation
input level

NTSC

PAL
SW7 = C

NTSC

PAL
SW7 = C

NTSC
upper limit
CL = 20pF

NTSC
lower limit
CL = 20pF

PAL

upper limit
SW7 = C

CL = 16pF

PAL

lower limit

SW7 = C

CL = 16pF

NTSC

PAL
SW7 = C

Electrical Characteristics AC Characteristics (2)

Item

Symbol

Conditions

Min. Typ. Max. Unit

CXA1854AR

Input SIG6 (VL = 0mV) to (A) and SIG3 (0dB, 3.58MHz)
to (B) and change the chroma phase. Assume the
maximum amplitude at TP39 as VR, the maximum
amplitude at TP41 as VG, and the maximum amplitude
at TP43 as VB, and calculate VRBN = VR/VB and VGBN
= VG/VB. V60 = 3.5V

Input SIG6 (VL = 0mV) to (A) and SIG3 (0dB, 3.58MHz)
to (B) and change the chroma phase. Assume the phase
at which the maximum amplitude at TP39, TP41 and
TP43 as

G and

B, respectively, and calculate

RBN =

B and

GBN =

V60 = 3.5V

Input SIG6 (VL = 0mV) to (A) and SIG3 (0 dB, 4.43MHz)
to (B) and change the chroma phase. Assume the
maximum amplitude at TP39 as VR, the maximum
amplitude at TP41 as VG, and the maximum amplitude
at TP43 as VB, and calculate VRBP = VR/VB and VGBP
= VG/VB. V60 = 3.5V, SW7 = C

Input SIG6 (VL = 0mV) to (A) and SIG3 (0 dB, 4.43MHz)
to (B) and change the chroma phase. Assume the phase
at which the maximum amplitude at TP39, TP41 and
TP43 as

G and

B, respectively, and calculate

RBP =

B and

GBP =

V60 = 3.5 V, SW7 = C

0.63

0.32

109

242

0.75

0.40

244

0.53

0.25

230

0.65

0.33

232

0.73

0.39

119

254

0.85

0.47

100

256

deg

VRBN

VGBN

RBN

GBN

VRBP

VGBP

RBP

GBP

Demodulation
output amplitude
ratio (NTSC)

Demodulation
output phase
difference (NTSC)

Demodulation
output amplitude
ratio (PAL)

Demodulation
output phase
difference (PAL)

Item

Symbol

Conditions

Min. Typ. Max. Unit

CXA1854AR

Input SIG6 (VL = 0mV) to (A). Adjust V60 so that the
output (black-black) at TP41 is 9Vp-p and measure the
DC voltage at TP39, TP41 and TP43.

Input SIG6 (VL = 0mV) to (A). Adjust V60 so that the
output (black-black) at TP41 is 9Vp-p, measure the DC
voltage at TP39, TP41 and TP43, and obtain the
maximum difference between these values.

Input SIG6 (VL = 0mV) to (A) and measure the output
(black-black) at TP39, TP41 and TP43 when V60 = 0V.

Input SIG6 (VL = 0mV) to (A) and measure the output
(black-black) at TP39, TP41 and TP43 when V60 = 5V.

Input SIG6 (VL = 0mV) to (A) and measure the
difference between the outputs (black-black) at TP39 and
TP43 and the output (black-black) at TP41 when V55
and V56 = 1V and when V55 and V56 = 4V.

Input SIG5 to (A) and measure the difference between
the outputs (white-black) at TP39 and TP43 and the
output (white-black) at TP41 when V63 and V64 = 1V
and when V63 and V64 = 4V.

Input SIG5 to (A) and obtain the gain difference between
the non-reversed output amplitudes (white-black) and the
reversed output amplitudes at TP39, TP41 and TP43.

Input SIG9 to (A) and adjust the non-reversed output
amplitude (white-black) at TP41 to 4Vp-p with V61.
Calculate the following:

1 = 20log (VG1/0.0357)

2 = 20log (VG2/0.0357)

3 = 20log (VG3/0.0357)

(See Fig. 6 for definitions of VG1, VG2 and VG3.)

Input SIG4 to (A) and adjust the output amplitude (white-
black) at TP41 to 4Vp-p with V61 when V57 and V58
= 0V and V59 = 5V. Measure the point where the gain of
the non-reversed output at TP41 changes and the
voltage difference V

1 between this output and V

2/2

when V59 = 0V and when V59 = 2.7V. V

1MN when

V59 = 0V, and V

1MX when V59 = 2.7V (See Fig. 7.)

Input SIG4 to (A) and adjust the output amplitude (white-
black) at TP41 to 4Vp-p with V61 when V57 and V58
= 0V. Measure the point where the gain of the
non-reversed output at TP41 changes and the voltage
difference V

2 between this output and V

2/2 when

V58 = 5V and when V58 = 1.5V. V

2MN when V58

= 5V and V

2MX when V58 = 1.5V. (See Fig. 7.)

21.5

9.5

18.5

3.5

2.0

25.5

12.5

23.5

29.5

15.5

26.5

2.0

0.9

5.85

9.0

±2

0.6

6.05

±4

6.25

100

3.0

0.6

VOUT

BRTMX

BRTMN

SBBRT

SBCNT

G (NR)

Item

RGB signal output characteristics

characteristics

RGB output DC
voltage

RGB output DC
voltage difference

Amount of change
in brightness

Amount of change
in sub-brightness

Amount of change
in sub-contrast

Difference in RGB
reversed/
non-reversed gain

gain

1 adjustment

variable range

2 adjustment

variable range

1MN

1MX

2MN

2MX

Symbol

Conditions

Min. Typ. Max. Unit

Electrical Characteristics AC Characteristics (3)

CXA1854AR

Input SIG6 (VL = 0mV, WS = 4.7µs, VS variable) to (A) and
confirm that it is synchronized with the output at TP30.
Gradually reduce the VS of SIG6 from 143mV and obtain the
VS at which input and output become non-synchronized.

Input SIG6 (VL = 0mV, VS = 143mV, WS = 4.7µs) to (A)
and measure the delay time with the output at TP30.
TDHDH is from the falling edge of the input sync signal to
the rising edge of TP30, and TDHDL from the rising edge
of the input sync signal to the falling edge of TP30.

Input SIG6 (VL = 0mV, VS = 143mV, WS = 4.7µs,
horizontal frequency variable) to (A) and confirm that
it is synchronized with the output at TP30. Obtain the
frequency fH where the input and output are
synchronized by changing the horizontal frequency
of SIG6 from the non-synchronized condition.
HPLLN = fH 15734, HPLLP = fH 15625

Input SIG6 (VL = 0mV) to (A) and SIG7 (VL variable) to (C),
(D) and (E). Raise the amplitude from 0 V and assume the
voltage, where the outputs at TP39, TP41 and TP43 go to
black level as VT1EXT. Then raise the amplitude further and
assume the voltage where these outputs go to white level as
VT2EXT. SW9 = B, SW10 = B, SW11 = B

Input SIG6 (VL = 0 mV) to (A) and SIG7 (VL = 3 V) to (C),
(D) and (E), and adjust the output amplitudes at TP39, TP41
and TP43 to 2.0V with V57. Measure the rise delay time
TD1EXTand the fall delay time TD2EXT.
SW9 = B, SW10 = B, SW11 = B (See Fig. 2.)

Input SIG6 (VL = 0mV) to (A) and SIG7 (VL = 1.7V) to
(C), (D) and (E), and measure the difference from the
black level of the outputs at TP39, TP41 and TP43.
SW9 = B, SW10 = B, SW11 = B

Input SIG6 (VL = 0mV) to (A) and SIG7 (VL = 2.7V) to
(C), (D) and (E), and measure the difference from the
black level of the outputs at TP39, TP41 and TP43.
SW9 = B, SW10 = B, SW11 = B

2.9

4.4

±500

1.0

2.0

100

1.8

3.2

4.7

1.2

2.2

200

2.2

3.5

5.0

1.4

2.4

300

µs

VSSEP

TDHDH

TDHDL

HPLLN

HPLLP

VT1EXT

VT2EXT

TD1EXT

TD2EXT

EXTBK

EXTWT

Item

Sync separation, TG block

Sync separation
input voltage
sensitivity

HD output delay
time

Horizontal pull-in
range

External RGB
input threshold
voltage

Propagation delay
time between
external RGB
input and output

Black level voltage
during external
RGB input

White level voltage
during external
RGB input

Symbol

Conditions

Min. Typ. Max. Unit

Electrical Characteristics AC Characteristics (4)

External I/O characteristics

NTSC

PAL
SW7 = C

CXA1854AR

Input SIG6 (VL =0 mV) to (A) and SIG2 (0dB,
frequency variable) to (B). Obtain frequencies
fc1 and fc2 which reduce the output amplitude
by 3dB from the maximum output at TP51 by
changing the frequency, and calculate F0BPF
= (fc1 + fc2)/2. Settings 1 and 3 are required.

Input SIG6 (VL = 0mV) to (A) and SIG2
(0dB, frequency variable) to (B).
Assume TP51 when the center
frequency is input as 0dB and measure
the output level at TP51 when the
frequencies noted on the right are
input. Settings 1 and 3 are required.

Input SIG2 (0dB, 3.58MHz, 4.43MHz) to (A) and
measure the output at TP41 with a spectrum
analyzer. Assume the output during Y/C mode
(SW8 = A) as 0dB and measure the amount of
attenuation during COMP mode (SW8 = C).
Settings 1 and 3 are required.

Input SIG6 (VL = 0mV) to (A) and SIG2 (amplitude
100mV, frequency variable) to (F) and (G). Assume the
output amplitude at TP41 when 100kHz is input as 0dB,
and measure the frequency which attenuates the output
amplitude by 3dB.

Input SIG6 (VL = 0mV) to (A).
Load 30pF (See Fig. 4.)
V3, V46, V58, V59 = 2.5V

Input SIG6 (VL = 0 mV) to (A).
Load 30pF (see Fig. 5.) HCK1/HCK2
V3, V46, V58, V59 = 2.5V

Input SIG6 (VL = 0mV) to (A).
Measure the HCK1 and HCK2 output duty.
Load 30pF
V3, V46, V58, V59 = 2.5V

3.33

4.13

0.6

3.58

4.43

0.8

3.83

4.73

1.2

MHz

F0BPFN

F0BPFP

ATBPF

ATRAPN

ATRAPP

DEMLP

tTLH

tTHL

DTYHC

Item

Filter characteristics

BPF center
frequency

Amount of BPF
attenuation

Amount of TRAP
attenuation

R-Y, B-Y and LPF
characteristics

Output transition
time (Note 3 pins)

Cross-point time
difference

HCK duty

Symbol

Conditions

Min.

Typ. Max. Unit

Electrical Characteristics AC Characteristics (5)

Digital block I/O characteristics

NTSC

PAL
SW7 = C

2.78MHz

1.50MHz

3.23MHz

2.00MHz

NTSC

PAL
SW7 = C

NTSC

PAL
SW7 = C

CXA1854AR

Description of Electrical Characteristics Measurement Methods

SIG7

TP39, 41, 43
non-reversed output

TD1EXT

TD2EXT

GND

CMAX

CMAX 3dB

Chroma output

fc1

fc2

BPF center frequency

FOBPF =

fc1 + fc2

Fig. 2. Measuring the delay between external

RGB input and output

Fig. 3. BPF center frequency

tTLH

90%

tTHL

10%

50%

Fig. 4. Output transition time measurement

condition

Fig. 5. Cross-point time difference measurement

condition

Non-reversed output

Input

1/2 V

White peak limiter

White

Black

Non-reversed output

Input

1/2 V

White

Black

Fig. 6.

characteristics measurement condition

Fig. 7.

adjustment variable range

CXA1854AR

Electrical Characteristics Measurement Circuit

B-YIN

R-YIN

COUT

HUE/RST

COLOR

XVXO

R-BRT

B-BRT

RGB-GAIN

GAMMA2

GAMMA1

BRIGHT

CONTRAST

CIN

R-GAIN

B-GAIN

TEST5

HCK1

HCK2

HST1

TEST4

CLR

VCK1

VCK2

VST1

TEST3

SLCK

TEST0

TEST1

SYNCIN

YIN

AGCADJ

AGCTC

PICT

GND1

MODE1

MODE2

EXT-R

EXT-G

EXT-B

RPD

CKI

CKO

TEST2

REG

BLKLIM

FB B

B OUT

FB G

G OUT

FB R

R OUT

GND 2

TEST8

TEST7

TEST6

RGT

SW52

SW53

SW55

SW56

SW57

SW58

SW59

SW60

SW61

SW63

SW64

V52

V53

V55

V56

V57

V58

V59

V60

V61

V63

V64

(B)

(G)

TP51

(F)

1µ

4.7k

1µ

47µ 0.1µ

+5V

TP39

TP41

100p

330k

1µ

100p

330k

1µ

0.1µ

330k

TP43

47µ

+12V

SW46

V46

1µ

0.1µ

47µ

+5V

0.01µ

+12V

47k

10k

30p

220p

S16

33k

3300p

3.3µ

10k

+5V

SW8

SW7

SW5

SW3

1µ

S18

S17

TP31

TP30

TP29

TP28

TP27

TP26

TP25

TP24

TP23

TP22

TP21

S19

+5V

40 39 38 37 36 35 34 33

9 10 11 12 13 14 15 16

(A)

CXA1854AR

10k

SW19

VR12

SW11

SW10

SW9

Used crystal: KINSEKI CX-5F
Frequency deviation: within ±30ppm,
frequency temperature characteristics: within ±30ppm
During NTSC: 3.579545MHz, load capacity: 16pF, CL = 20pF
During PAL: 4.433619MHz, load capacity: 16pF, CL = 16pF
Measure under the condition that the crystal parallel floating
capacitance is within 2pF.

Vari-cap diode: 1T369 (SONY)

L value: 10µH when using the LCX005

4.7µH when using the LCX009

CXA1854AR

Description of Operation

The CXA1854AR incorporates the three functions of an RGB decoder block, an RGB driver block and a timing
generator (TG) block onto a single chip using BiCMOS technology. This section describes these functions and
their mutual relationship.

1) Description of the overall configuration

RGB decoder

EXT-R

EXT-G

EXT-B

SYNC

R-Y

B-Y

CXA1854AR

ENB

CLR

VST1

VCK2

VCK1

HST1

HCK2

HCK1

FRP

R OUT

G OUT

B OUT

SYNC

BLK

3.58MHz
or 4.43MHz

RPD

CKI

RGB driver

VCO

Corresponding LCD panels

LCX009AK/AKB

1.8cm 180K dots

LCX005BK/BKB

1.4cm 113K dots

2) Description of RGB decoder block operation

· Input mode switching

Signal input: Composite input, Y/C input and Y/color difference input switching is supported by Pin 8

(MODE2).

During composite input:

The composite signal is input to Pins 1, 2 and 62.

During Y/C input:

The Y signal is input to Pins 1 and 2, and the C signal to Pin 62.

During Y/color difference input: The Y signal is input to Pins 1 and 2, the R-Y signal to Pin 50, and the B-Y

signal to Pin 49.

(Chroma signal input (delay line output) is also used during PAL, but is

switched with the MODE1 setting.)

Recommended input signal voltages for each mode are shown in the Pin Description table. The Y signal

enters the TRAP circuit in composite mode, but through operation is performed in all other modes. Also, the

picture center frequency is set separately for composite input and Y/C input. (See the AC Characteristics

tables.)

· NTSC/PAL switching

NTSC and PAL (DPAL using an external delay line and SPAL) are switched by MODE1.

The built-in TRAP and BPF center frequencies are switched automatically according to the external crystal.

The center frequency is stabilized by the APC operation.

The R-Y demodulation detective axis is set internally to 90° during SPAL/DPAL. However, optimally adjust

the demodulation phase axis with the HUE adjustment pin.

· Video AGC/ACC circuit

Different AGC characteristics are obtained depending on the APL level of the luminance signal. The gain for

the luminance signal is adjusted with the average value. The sync amplitude of the burst signal output is

detected and used to adjust the ACC amplifier gain.

CXA1854AR

· VXO, APC detection

The VXO local oscillation circuit is crystal oscillation circuit. The phases of the input burst signal and the VXO

oscillator output are compared in the APC detection block, and the detective output is used to form a PLL

loop that controls the VXO oscillation frequency, which means that the need for adjustments is eliminated. In

addition, the filter f0 is automatically adjusted, since the BPF and TRAP center frequency is feedback

controlled by VXO.

· Crystal oscillator for the XVXO pin connection

A 3.579545MHz crystal vibrator is connected to the XVXO pin during NTSC, and a 4.433619MHz crystal

vibrator during PAL. (Use KINSEKI CX-5F crystal vibrator with a load capacity of 16pF, frequency deviation

within ±30ppm, and frequency temperature characteristics within ±30ppm.)

· External inputs

Digital input with two thresholds is optimal for multiplexed character output to screens. When one of the RGB

inputs is higher than the lower threshold Vth1, all RGB outputs go to black level. When the higher threshold

Vth2 is exceeded, the output for only the signal in question goes to white level, while the other outputs

remain at black level. Externally connect a pull-down resistor (10k

or more).

3) Description of RGB driver block operation

· 2-point

compensation circuit

In order to support the characteristic of LCD panels, the I/O characteristics are as shown in Fig. 1. The

voltage at

gain change point A can be changed to that shown in Fig. 2 by adjusting the GAMMA1 pin (Pin

59). Also, the voltage at the

2 gain change point can be changed to that shown in Fig. 3 by adjusting the

GAMMA2 pin (Pin 58). The drive for LCD panels can be optimized by adjusting the overall gain with these

two gain change points and the RGB-GAIN pin (Pin 57).

Output

Input

Output

Input

Output

Input

Fig. 1

Fig. 3

Fig. 2

CXA1854AR

· Sample-and-hold circuit

As the LCD panels sample-and-hold RGB signals simultaneously, RGB signal output from CXA1854R must

be synchronized to LCD panel drive pulses and sample-and-hold performed. Sample-and-hold is performed

by receiving the SH1 to SH4 pulses from the TG block. Since LCD panels perform color coding using an

RGB delta arrangement, each horizontal line must be compensated by 1.5 dots. This relationship is reversed

during right/left inversion. These timing pulses are generated by the TG block. Accordingly, RGB signals are

each sampled-and-held at the optimal timing and output by the RGB driver block.

S/H

SH1 SH3

SH2

SH4

HCK

SH3

SH1

SH4

SH2

Normal scan

HCK

SH2

SH1

SH4

SH3

Reverse scan

Example of sample-and-hold circuits and S/H timing

· RGB output

RGB outputs (Pins 39, 41, and 43) are reversed each horizontal line by the FRP pulse supplied from the TG

block as shown in the figure below. Feedback is applied so that the center voltage of the output signal

matches the reference voltage (V

2 + GND1)/2. In addition, the white level output is clipped by the Vsig

center voltage level, and the black level output is clipped by the limiter operation point that is adjusted at the

BLKLIM pin (Pin 46).

Video IN

FRP

RGB OUT

waveform

Black level limiter
(reversed side)

Vsig center voltage

Black level limiter
(non-reversed side)

CXA1854AR

4) Description of TG block operation

This section describes the main functions of the TG block. (See individual description materials for details.)

· PLL circuit block

The PLL circuit block contains a phase comparator and frequency division counter circuit in order to

accurately align the timing, and performs PLL operation by externally connecting a VCO circuit. The average

voltage of the RPD pin (Pin 12) is locked roughly in the center by adjusting it to V

/2. (See the attached

Application Circuit for the external circuit diagram. The 1T369 is recommended as the vari-cap diode used in

the VCO circuit.)

· SYNC detection circuit

This circuit separates the input SYNC signal into HSYNC and VSYNC, and recognizes the EVEN and ODD

fields and line numbers, etc. This circuit is necessary for the reasons (1) and (2).

(1) Shifts 1.5 dots each horizontal line for the RGB delta arrangement.

(2) Field recognition and accurate line number recognition for changing the eliminated lines for each EVEN

and ODD field and smoothing the picture during PAL.

In addition, if the SYNC waveform is not detected for more than a certain interval, the unit shifts automatically

to the free running state and the LCD panel is driven by self oscillation.

· Pulse generator block

The pulse generator circuit is synchronized to the previously mentioned SYNC detection circuit and PLL

circuit, and generates the pulses necessary to drive the LCD panel. (The main output pulse timings are

shown for each mode in a later section.) At the same time, the pulse generator circuit also generates the

BGP, BLK and other waveforms for the RGB decoder. Therefore, TG block PLL circuit operation is necessary

for RGB decoder functions.

· AC drive during no signal

HST1, HCK1, HCK2, FRP, VST1, VCK1, VCK2, HD and VD are made to run free so that the LCD panel is

AC driven even when there is no composite sync from the SYNC pin. During this time, the HSYNC

separation circuit stops and the PLL counter is made to run free. In addition, the reference pulse for

generates VD and VST, and the auxiliary V counter creates the reference pulse for generates VD and VST.

The VSYNC separation circuit is also stopped and The period of the V counter is designed to be 269H for

NTSC and 321H for PAL. When there is no VSYNC during 269H or 321H, the free running state is assumed.

In addition, RPD is kept at high impedance in order to prevent the AFC circuit from producing a phase error

due to phase comparison when there is no signal.

· AFC circuit (702/1050fh generation)

A fully synchronized AFC circuit is built in. PLL error signal is generated at the following timing. The phase

comparison output of the entire bottom of SYNC and the internal H counter becomes RPD. RPD output is

converted to DC error with the lag-lead filter, and then it changes the vari-cap diode capacitance and the

oscillation frequency is stabilized at 702fh in the LCX005BK/BKB and 1050fh in the LCX009AK/AKB.

4.7µs

SYNC

RPD

SYNC center

CXA1854AR

5) Description of TG block mode settings

· SLCK: Selects the driven LCD panel.

Selects the LCX009

Selects the LCX005

Normal scan mode

Reverse scan mode

Note) The VCO frequency varies depending on the used panel.

VCO center frequency

LCX005 (702fh)

LCX009 (1050fh)

NTSC

PAL

11.06MHz

10.97MHz

NTSC

PAL

16.52MHz

16.41MHz

The external VCO circuit diagram is shown in the Application Circuit.

Recommended value: L value LCX005: 10µH, LCX009: 4.7µH

The HST1, HCK1 and HCK2 timing are switched by the RGT selection. The timing of the internal

sample-and-hold pulse is also switched at the same time. Connect the panel RGT pin directly, as it

does not support output.

· RGT: Switches the horizontal scan direction.

NTSC

D-PAL

SPAL

Composite input

Y/color difference input

Y/C input

· MODE1/MODE2: Sets the type of video signal input.

MODE1

MODE2

Signal input connections for each mode are noted in the RGB decoder block.

CXA1854AR

LCX009AK/AKB and LCX005BK/BKB Color Coding Diagram

The delta arrangement is used for the color coding in the LCD panels with which this IC is compatible. Note

that the shaded region within the diagram is not displayed.

LCX009AK/AKB pixel arrangement

800

827

Display area

Photo-shielding

area

dummy3

Vline225

Vline224

dummy2

Vline3

Vline2

Vline1

dummy1

dummy1 to 4

HSW1

HSW2

HSW267

HSW268

dummy5 to 8

225 228

LCX005BK/BKB pixel arrangement

521

537

dummy4

Vline218

Vline217

dummy2

Vline3

Vline2

Vline1

dummy1

HSW1

HSW3

HSW174

HSW175

dummy2 to 5

218 222

dummy3

dummy1

HSW2

Display area

Photo-shielding

area

CXA1854AR

Application Circuit NTSC (COMP and Y/C input)

1µ

47µ 0.1µ

+5V

Red

Green

330k

1µ

330k

1µ

330k

Blue

47µ

+12V

0.1µ

47µ

+5V

0.01µ

+12V

47k

10k

30p

220p

33k

3300p

3.3µ

10k

+5V

Y/C

COMP

1µ

To panel

0.01µ

COMP/Y IN

C IN

HUE

COLOR

R-BRT

B-BRT

RGB

GAM2

GAM1

BRT

CONT

R-G

B-G

AGC

PIC

B-LIM

To panel

Y/C

COMP

+5V

47k

1µ

0.01µ

47k

0.1µ

1.7k

0.01µ

20pF

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

005

009

B-YIN

R-YIN

COUT

HUE/RST

COLOR

XVXO

R-BRT

B-BRT

RGB-GAIN

GAMMA2

GAMMA1

BRIGHT

CONTRAST

CIN

R-GAIN

B-GAIN

TEST5

HCK1

HCK2

HST1

TEST4

CLR

VCK1

VCK2

VST1

TEST3

SLCK

TEST0

TEST1

SYNCIN

YIN

AGCADJ

AGCTC

PICT

GND1

MODE1

MODE2

EXT-R

EXT-G

EXT-B

RPD

CKI

CKO

TEST2

REG

BLKLIM

FB B

B OUT

FB G

G OUT

FB R

R OUT

GND 2

TEST8

TEST7

TEST6

RGT

40 39 38 37 36 35 34 33

9 10 11 12 13 14 15 16

CXA1854AR

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

Used crystal: KINSEKI CX-5F
Frequency deviation: within ±30ppm,
frequency temperature characteristics: within ±30ppm
3.579545MHz, load capacity: 16pF

Vari-cap diode: 1T369 (SONY)

L value: 10µH when using the LCX005

4.7µH when using the LCX009

CXA1854AR

Application Circuit PAL (COMP and Y/C input)

HUE

COLOR

R-BRT

B-BRT

RGB

GAM2

GAM1

BRT

CONT

R-G

B-G

AGC

PIC

B-LIM

1µ

47µ 0.1µ

+5V

Red

Green

330k

1µ

330k

1µ

330k

Blue

47µ

+12V

1µ

0.1µ

47µ

+5V

0.01µ

+VCC2

+12V

47k

10k

30p

220p

33k

3300p

3.3µ

10k

+5V

1µ

+5V

COMP/Y IN

C IN

To panel

Y/C

COMP

47k

Y/C

COMP

To panel

0.01µ

47k

1.7k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

16pF

005

009

0.1µ

B-YIN

R-YIN

COUT

HUE/RST

COLOR

XVXO

R-BRT

B-BRT

RGB-GAIN

GAMMA2

GAMMA1

BRIGHT

CONTRAST

CIN

R-GAIN

B-GAIN

TEST5

HCK1

HCK2

HST1

TEST4

CLR

VCK1

VCK2

VST1

TEST3

SLCK

TEST0

TEST1

SYNCIN

YIN

AGCADJ

AGCTC

PICT

GND1

MODE1

MODE2

EXT-R

EXT-G

EXT-B

RPD

CKI

CKO

TEST2

REG

BLKLIM

FB B

B OUT

FB G

G OUT

FB R

R OUT

GND 2

TEST8

TEST7

TEST6

RGT

40 39 38 37 36 35 34 33

9 10 11 12 13 14 15 16

CXA1854AR

Used crystal: KINSEKI CX-5F
Frequency deviation: within ±30ppm,
frequency temperature characteristics: within ±30ppm
4.433619MHz, load capacity: 16pF

Vari-cap diode: 1T369 (SONY)

L value: 10µH when using the LCX005

4.7µH when using the LCX009

CXA1854AR

Application Circuit Y/color difference input (NTSC/PAL)

1µ

47µ 0.1µ

+5V

Red

Green

330k

1µ

330k

1µ

330k

Blue

47µ

+12V

1µ

0.1µ

47µ

+5V

0.01µ

+VCC2

+12V

47k

10k

30p

220p

33k

3300p

3.3µ

10k

+5V

PAL

NTSC

1µ

+5V

Y IN

HUE

COLOR

R-BRT

B-BRT

RGB

GAM2

GAM1

BRT

CONT

R-G

B-G

AGC

PIC

B-LIM

To panel

B-YIN

R-YIN

1µ

1.7k

To panel

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

47k

0.01µ

0.1µ

005

009

47k

B-YIN

R-YIN

COUT

HUE/RST

COLOR

XVXO

R-BRT

B-BRT

RGB-GAIN

GAMMA2

GAMMA1

BRIGHT

CONTRAST

CIN

R-GAIN

B-GAIN

TEST5

HCK1

HCK2

HST1

TEST4

CLR

VCK1

VCK2

VST1

TEST3

SLCK

TEST0

TEST1

SYNCIN

YIN

AGCADJ

AGCTC

PICT

GND1

MODE1

MODE2

EXT-R

EXT-G

EXT-B

RPD

CKI

CKO

TEST2

REG

BLKLIM

FB B

B OUT

FB G

G OUT

FB R

R OUT

GND 2

TEST8

TEST7

TEST6

RGT

40 39 38 37 36 35 34 33

9 10 11 12 13 14 15 16

CXA1854AR

Vari-cap diode: 1T369 (SONY)

L value: 10µH when using the LCX005

4.7µH when using the LCX009

CXA1854AR

RGT: H (Normal scan) Composite In

CLK

SYNC

(BLK)

HST

HCK1

HCK2

FRP

(Internal pulse)

VCK1

VCK2

CLR

(PAL)

653

663

673

683

693

4.7µ

s (52fh)

13fh

18.5fh

4.7µ

s (52fh)

4.5µ

s (50fh)

2.0µ

s (22fh)

EVEN FIELD

3.0µ

s (33fh)

702

0.5µ

s (6fh)

23.5fh

ODD FIELD

ODD LINE

LCX005 Horizontal Direction Timing Chart (NTSC, PAL)

Note)

During Y/C input, the HST timing is delayed 6fh from the above timing.

The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.

FRP polarity is not specified.

CXA1854AR

653

663

673

683

693

4.7µ

s (52fh)

13fh

18.0fh

4.7µ

s (52fh)

4.5µ

s (50fh)

RGT: H (Normal scan) Composite In

2.0µ

s (22fh)

3.0µ

s (33fh)

22fh

0.5µ

s (6fh)

ODD FIELD

EVEN FIELD

702

CLK

SYNC

(BLK)

HST

HCK1

HCK2

FRP

(Internal pulse)

VCK1

VCK2

CLR

(PAL)

EVEN LINE

LCX005 Horizontal Direction Timing Chart (NTSC, PAL)

Note)

During Y/C input, the HST timing is delayed 6fh from the above timing.

The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.

FRP polarity is not specified.

CXA1854AR

CLK

SYNC

(BLK)

HST

HCK1

HCK2

FRP

(Internal pulse)

VCK1

VCK2

CLR

(PAL)

653

663

673

683

693

4.7µ

s (52fh)

18.0fh

4.5µ

s (50fh)

RGT: L (Reverse scan) Composite In

2.0µ

s (22fh)

4.7µ

s (52fh)

EVEN FIELD

3.0µ

s (34fh)

23fh

0.5µ

s (5fh)

ODD FIELD

702

13fh

ODD LINE

LCX005 Horizontal Direction Timing Chart (NTSC, PAL)

Note)

During Y/C input, the HST timing is delayed 6fh from the above timing.

The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.

FRP polarity is not specified.

CXA1854AR

CLK

SYNC

(BLK)

HST

HCK1

HCK2

FRP

(Internal pulse)

VCK1

VCK2

CLR

(PAL)

653

663

673

683

693

4.7µ

s (52fh)

13fh

18.5fh

4.5µ

s (50fh)

RGT: L (Reverse scan) Composite In

2.0µ

s (22fh)

4.7µ

s (52fh)

EVEN FIELD

3.0µ

s (34fh)

24.5fh

0.5µ

s (5fh)

ODD FIELD

702

EVEN LINE

LCX005 Horizontal Direction Timing Chart (NTSC, PAL)

Note)

During Y/C input, the HST timing is delayed 6fh from the above timing.

The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.

FRP polarity is not specified.

CXA1854AR

328

2.5H

14.5H

600

25H

(VD)

SYNC

(BLK)

VST

VCK1

VCK2

FRP

(Internal pulse)

HST

CLR

FRP

(Internal pulse)

FLD

(Internal pulse)

VRST

(Internal pulse)

2.5H

288

25H

314

Display start

6, 8 decimation

EVEN FIELD

ODD FIELD

14H

Display start

(1F inversion)

LCX005 Vertical Direction Timing Chart (PAL)

Note) The second and fourth rows of the timing chart "VD" and "BLK" are pulses indicated as a reference and are not pulses output from pins.

CXA1854AR

SYNC

(BLK)

VCK1

VCK2

HST

FRP

(Internal pulse)

CLR

(PAL)

971

981

991

1001

1011

1021

1031

1041

101

111

1050

4.7µ

s (78fh)

2.0µ

s (33fh)

4.5µ

s (73fh)

4.7µ

s (78fh)

20.5fh

12fh

43.5fh

3.0µ

s (50fh)

0.5µ

s (8fh)

EVEN FIELD

ODD FIELD

HCK1

HCK2

CLK

RGT: H (Normal scan) Composite In

ODD LINE

LCX009 Horizontal Direction Timing Chart (NTSC, PAL)

Note)

During Y/C input, the HST timing is delayed 6fh from the above timing.

The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.

FRP polarity is not specified.

CXA1854AR

SYNC

(BLK)

VCK1

VCK2

HST

FRP

(Internal pulse)

CLR

(PAL)

971

981

991

1001

1011

1021

1031

1041

101

111

1050

4.7µ

s (78fh)

2.0µ

s (33fh)

4.5µ

s (73fh)

4.7µ

s (78fh)

19fh

12fh

43.0fh

3.0µ

s (50fh)

0.5µ

s (8fh)

ODD FIELD

EVEN FIELD

HCK1

HCK2

CLK

RGT: H (Normal scan) Composite In

EVEN LINE

LCX009 Horizontal Direction Timing Chart (NTSC, PAL)

Note)

During Y/C input, the HST timing is delayed 6fh from the above timing.

The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.

FRP polarity is not specified.

CXA1854AR

SYNC

(BLK)

VCK1

VCK2

HST

FRP

(Internal pulse)

CLR

(PAL)

971

981

991

1001

1011

1021

1031

1041

101

111

1050

4.7µ

s (78fh)

2.0µ

s (33fh)

4.5µ

s (73fh)

4.7µ

s (78fh)

20fh

12fh

43.0fh

3.0µ

s (51fh)

0.5µ

s (7fh)

EVEN FIELD

ODD FIELD

HCK1

HCK2

CLK

RGT: L (Reverse scan) Composite In

ODD LINE

LCX009 Horizontal Direction Timing Chart (NTSC, PAL)

Note)

During Y/C input, the HST timing is delayed 6fh from the above timing.

The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.

FRP polarity is not specified.

CXA1854AR

SYNC

(BLK)

VCK1

VCK2

HST

FRP

(Internal pulse)

CLR

(PAL)

971

981

991

1001

1011

1021

1031

1041

101

111

1050

4.7µ

s (78fh)

2.0µ

s (33fh)

4.5µ

s (73fh)

4.7µ

s (78fh)

21.5fh

12fh

43.0fh

3.0µ

s (51fh)

0.5µ

s (7fh)

EVEN FIELD

ODD FIELD

HCK1

HCK2

CLK

RGT: L (Reverse scan) Composite In

EVEN LINE

LCX009 Horizontal Direction Timing Chart (NTSC, PAL)

Note)

During Y/C input, the HST timing is delayed 6fh from the above timing.

The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.

FRP polarity is not specified.

CXA1854AR

2.5H

10.5H

5.5H

600

25H

(VD)

SYNC

(BLK)

VST

VCK1

VCK2

FRP

(Internal pulse)

HST

CLR

FRP

(Internal pulse)

FLD

(Internal pulse)

VRST

(Internal pulse)

2.5H

288

25H

314

324

10.0H

6.0H

6, 8 decimation

EVEN FIELD

ODD FIELD

Display start

(1F inversion)

LCX009 Vertical Direction Timing Chart (PAL)

Note) The second and fourth rows of the timing chart "VD" and "BLK" are pulses indicated as a reference and are not pulses output from pins.

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA1854AR