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Электронный компонент: CXA1946CR

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Description
The CXA1946CR is a serial control electronic
volume IC designed for use in audio systems.
Features
Loudness
Volume control (0dB to 87dB in 1dB step,
dB)
Balance
Tone control (15 steps, 2 bands, 16dB to +16dB)
Fader
(2dB-step to 20dB, 25dB, 35dB, 45dB, 60dB,
dB)
Input selector (4 channels)
Gain can be set for each input channel (common for channels 3 and 4)
Serial data control (DATA, CLK, CE)
Single 8V power supply
Zero-cross detection circuit (with timer)
Power-off mute
Volume control and tone control input/output pins are separate.
Absolute Maximum Ratings
Supply voltage
V
CC
13
V
Operating temperature
Topr
40 to +85
C
Storage temperature
Tstg
65 to +150
C
Allowable power dissipation
P
D
LQFP
180
mW (Ta = 85C)
Operating Conditions
Supply voltage
V
CC
6 to 12
V
1
CXA1946CR
E97516A7Y
Electronic Volume
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
48 pin LQFP (Plastic)
For the availability of this product, please contact the sales office.
2
CXA1946CR
Block Diagram and Pin Configuration
GA
IN
1
3
4
LD
LC
1
L
DHC1
IN
A
O
1
VR
I
N
1
VO
U
T
1
TI
N
1
T
CHC1
T
C
LC
11
T
C
LC
12
TC
O
1
FD
I
N
1
GA
IN
2
3
4
LD
LC
2
L
DHC2
IN
A
O
2
VR
I
N
2
VO
U
T
2
TI
N
2
T
CHC2
T
C
LC
21
T
C
LC
22
TC
O
2
FD
I
N
2
GAIN12
GAIN11
IN14
IN13
IN12
IN11
IN21
IN22
IN23
IN24
GAIN21
GAIN22
FNTO1
REO1
CE
CLK
DGND
GND
V
CC
VCT
DATA
TIMER
REO2
FNTO2
LOUD
VCTBUFF
VCTBUFF
VCTBUFF
VCTBUFF
VCTBUFF
VCTBUFF
SHIFT REGISTER
LATCH
100k
100k
LATCH CONTROL
8dB STEP
VOLUME
1dB STEP
VOLUME
TONE
FADER
VOLUME
8dB STEP
VOLUME
1dB STEP
TONE
FADER
LOUD
I
N
PU
T
SW
I
N
PU
T
SW
ZCDET
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
36
35
34
31
32
33
40
39
38
37
41
42
43
44
45
46
47
48
2
3
4
5
6
7
8
9
10
11
12
1
3
CXA1946CR
Pin Description
Pin
No.
Symbol
I/O resistance
Pin voltage
Equivalent circuit
Description
1
36
GAIN234
GAIN134
VCT
Sets gain for IN3 and IN4.
36
1
GND
V
CC
2
35
LDLC2
LDLC1
6.18k
VCT
Sets loudness low cut-off
frequency.
35
2
V
CC
GND
3
34
LDHC2
LDHC1
8.92k
VCT
Sets loudness high cut-off
frequency.
34
3
GND
V
CC
4
33
INAO2
INAO1
--
VCT
Input selector output
4
33
GND
V
CC
~
4
CXA1946CR
5
32
VRIN2
VRIN1
9.5k
VCT
Volume input
32
5
GND
V
CC
6
31
VOUT2
VOUT1
--
VCT
Volume output
31
6
V
CC
GND
7
30
TIN2
TIN1
19k
VCT
Tone input
30
7
GND
V
CC
8
29
TCHC2
TCHC1
5k
VCT
Sets tone high frequency.
29
8
GND
V
CC
Pin
No.
Symbol
I/O resistance
Pin voltage
Equivalent circuit
Description
5
CXA1946CR
9
28
TCLC21
TCLC11
8k
VCT
Sets tone low frequency.
28
9
GND
V
CC
10
27
TCLC22
TCLC12
8k
VCT
Sets tone low frequency.
27
10
V
CC
GND
11
26
TCO2
TCO1
--
VCT
Tone control output
26
11
GND
V
CC
12
25
FDIN2
FDIN1
24k
VCT
Fader input
25
12
GND
V
CC
Pin
No.
Symbol
I/O resistance
Pin voltage
Equivalent circuit
Description
6
CXA1946CR
13
24
FNTO2
FNTO1
--
VCT
Front output
24
GND
13
V
CC
14
23
REO2
REO1
--
VCT
Rear output
23
V
CC
GND
14
15
TIMER
--
--
Sets timer.
GND
15
V
CC
16
DATA
--
Serial data input
GND
16
V
CC
Pin
No.
Symbol
I/O resistance
Pin voltage
Equivalent circuit
Description
~
7
CXA1946CR
21
CLK
Serial clock input
17
VCT
--
VCT
Center electric potential
18
V
CC
V
CC
+ power supply
19
GND
GND
GND
20
DGND
--
Digital GND
GND
21
V
CC
22
CE
Latch enable input
22
GND
V
CC
37
48
GAIN12
GAIN22
Sets gain for IN2.
48
37
V
CC
GND
--
Pin
No.
Symbol
I/O resistance
Pin voltage
Equivalent circuit
Description
--
VCT
~
~
~
8
CXA1946CR
38
47
GAIN11
GAIN21
Sets gain for IN1.
47
38
GND
V
CC
39
40
41
42
43
44
45
46
IN14
IN13
IN12
IN11
IN21
IN22
IN23
IN24
50k
VCT
Signal input
40
39
41
42
44
45
46
43
GND
V
CC
Pin
No.
Symbol
I/O resistance
Pin voltage
Equivalent circuit
Description
~
9
CXA1946CR
Data Format
(a) Data allocation
FAST BIT
LAST BIT
MSB
LSB
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
NOP
ISW
LOUD
VRC1
VRF1
VRC2
VRF2
TONE BASS
TONE TREBLE
FADER
FADER SELECT
10
CXA1946CR
(b) Setting table
NOP
Setting value
D1
D2
--
0
0
ISW
Setting value
D3
D4
IN14/IN24
IN13/IN23
IN12/IN22
IN11/IN21
1
1
0
0
1
0
1
0
VRC1/VRC2
Setting value
D6/D13
D7/D14
0
8
16
24
32
40
48
56
64
72
80
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
D8/D15
1
1
0
0
1
1
0
0
1
1
0
0
0
D9/D16
1
0
1
0
1
0
1
0
1
0
1
0
0
VRF1/VRF2
Setting value
D10/D17
D11/D18
0
1
2
3
4
5
6
7
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
D12/D19
1
0
1
0
1
0
1
0
LOUD
Setting value
D5
ON
OFF
1
0
11
CXA1946CR
TONE BASS/TREBLE
Setting value
D20/D24
D21/D25
14
12
10
8
6
4
2
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
D22/D26
1
0
1
0
1
0
1
0
FADER
Setting value
D28
D29
60
45
35
25
20
18
16
14
12
10
8
6
4
2
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D30
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D31
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
BOOST/CUT
Setting value
D23/D27
BOOST
CUT
1
0
FADER SELECT
RESET
Reset is performed automatically when power is first supplied to the IC; there is no reset pin.
The following table shows the respective statuses of various settings after a reset has been performed.
However, from the time when power is first supplied until the first data transfer, keep CE high by pulling it up
to Vcc, etc.
Setting value
D32
Attenuation of front signal
Attenuation of rear signal
1
0
MODE
Setting value
INPUT
VRC1
VRF1
VRC2
VRF2
LOUD
TONE BASS
TONE TREBLE
FADER
1
7dB
7dB
OFF
0dB
0dB
0dB, REAR
12
CXA1946CR
Electrical Characteristics
(Unless otherwise specified, Vcc = 8V, Ta = 25C)
Item
Symbol
Measurement conditions
Min.
Typ.
Max.
Unit
Current consumption
Total harmonic distortion
Output noise voltage
Maximum output voltage
Separation
Volume maximum attenuation
Low
High
Bass max. boost gain
Bass max. cut gain
Treble max. boost gain
Treble max. cut gain
Low
High
Input voltage range
Loudness
Input voltage
I
CC
THD
Vn
Vom
CS
ATTm
Glb
Glh
Gbb
Gbc
Gtb
Gtc
Vsl
Vsh
Vin
No signal
1kHz, 5dBm output
input shorted, A weight
1kHz
1kHz
1kHz
100Hz, VRC = 16dB
10kHz, VRC = 16dB
DATA, CLK, CE
IN11 to 14, IN21 to 24, VRIN1, VRIN2,
TIN1, TIN2, FDIN1, FDIN2
--
--
--
8
72
85
7
5
14
14
14
14
0
3
1
20
0.005
7
--
90
90
8
6
16
16
16
16
--
--
--
25
0.01
10
--
--
--
9
7
18
18
18
18
1.5
6
V
CC
1
mA
%
Vrms
dBm
dB
dB
dB
dB
dB
dB
dB
dB
V
V
V
13
CXA1946CR
Electrical Characteristics Measurement Circuit
FNTO1
REO1
CE
CLK
DGND
GND
V
CC
VCT
DATA
TIMER
REO2
FNTO2
B
10k
V24
AC
FD
I
N
1
TC
O
1
T
C
LC
12
T
C
LC
11
T
CHC1
TI
N
1
VO
U
T
1
VR
I
N
1
IN
A
O
1
L
DHC1
LD
LC
1
GA
IN
1
3
4
FD
I
N
2
TC
O
2
T
C
LC
22
T
C
LC
21
T
CHC2
TI
N
2
VO
U
T
2
VR
I
N
2
IN
A
O
2
L
DHC2
LD
LC
2
GA
IN
2
3
4
GAIN12
GAIN11
IN14
IN13
IN12
IN11
IN21
IN22
IN23
IN24
GAIN21
GAIN22
0.
0027
B
A
V6
AC
B
A
10
0.
0022
0.
047
10k
10k
10k
0.39
10
0.
39
10
0.
0027
10
10k
10k
0.
0022
0.
047
10k
S6
OF
F
ON
10k
10k
1k
10k
0.01
V1
V
EE
3 to 6V
V
CC
3 to 6V
B
A
1k
V2
1k
V3
10k
10k
1k
V5
AC
S1
ON
OFF
1k
OP AMP
1k
220p
VCT-50mV
S3
S2
B
A
V7
AC
10
S5-1
S4
B
A
V8
AC
10
S5-2
V23
AC
V22
AC
V21
AC
V11
AC
V12
AC
V13
AC
V14
AC
B
A
B
A
B
A
B
A
B
A
B
A
B
A
S14
10k
S13
10k
S12
10k
S11
10k
S21
10k
S22
10k
S23
10k
S24
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
1
A
14
CXA1946CR
Application Circuit 1
0.39
0.0027
10
10
0.39
10
0.0027
0.047
10
0.0022
33
0.01
10
0.047
10
0.0022
FNTO1
REO1
CE
CLK
DGND
GND
V
CC
VCT
DATA
TIMER
REO2
FNTO2
FD
I
N
1
TC
O
1
T
C
LC
12
T
C
LC
11
T
CHC1
TI
N
1
VO
U
T
1
VR
I
N
1
IN
A
O
1
L
DHC1
LD
LC
1
GA
IN
1
3
4
FD
I
N
2
TC
O
2
T
C
LC
22
T
C
LC
21
T
CHC2
TI
N
2
VO
U
T
2
VR
I
N
2
IN
A
O
2
L
DHC2
LD
LC
2
GA
IN
2
3
4
GAIN12
GAIN11
IN14
IN13
IN12
IN11
IN21
IN22
IN23
IN24
GAIN21
GAIN22
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
1
10
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
15
CXA1946CR
Application Circuit 2
0.39
0.
0027
10
10
0.39
0.
0027
0.
047
10
0.0022
33
0.01
0.
047
10
0.0022
FNTO1
REO1
CE
CLK
DGND
GND
V
CC
VCT
DATA
TIMER
REO2
FNTO2
FD
I
N
1
TC
O
1
T
C
LC
12
T
C
LC
11
T
CHC1
TI
N
1
VO
U
T
1
VR
I
N
1
IN
A
O
1
L
DHC1
LD
LC
1
GA
IN
1
3
4
FD
I
N
2
TC
O
2
T
C
LC
22
T
C
LC
21
T
CHC2
TI
N
2
VO
U
T
2
VR
I
N
2
IN
A
O
2
L
DHC2
LD
LC
2
GA
IN
2
3
4
GAIN12
GAIN11
IN14
IN13
IN12
IN11
IN21
IN22
IN23
IN24
GAIN21
GAIN22
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
1
10
10
10
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
16
CXA1946CR
0
25
20
15
10
5
Response [dB]
10
100
1k
10k
100k
Frequency [Hz]
Loudness characteristics
VRC = 0dB
VRC = 8dB
VRC = 16dB
VRC = 24dB
20
20
16
12
12
16
Response [dB]
10
100
1k
10k
100k
Frequency [Hz]
Tone control characteristics
8
4
0
4
8
16dB
0dB
+16dB
17
CXA1946CR
Description of Operation
The CXA1946CR is a serial control electronic volume IC designed for use in audio systems.
The internal circuit of the IC consists of the following blocks:
1. Input selector
2. Volume
3. Loudness
4. Tone control
5. Fader
6. VCT buffer
7. Serial data I/O
8. Zero-cross detector (with timer)
9. Power-off mute
The operation of each block and notes on their use are described below.
Note that when the circuits for channels 1 and 2 are identical, the suffix "X" is added to pin names and device
names in order to distinguish between the two channels.
1. Input selector
There are two channels (stereo), each with four systems of input pins; the input selector selects one of
those input systems.
The gain between the input pins and the output pin of the input selector can be set independently for each
input system, except the gain for inputs 3 and 4 is common.
Determine the gain for each system through the settings of the feedback circuit constants as shown in Figs.
1 and 2. When each input gain is set to
1, short INAOX and GAIN
1,GAIN
2,GAIN
34.
The input impedance is 50k
(typ.) for each input.
The output impedance for INAO1 and INAO2 is low impedance (roughly 0
). The gain is not affected by the
load impedance.
Fig. 1. Input Selector (1)
50k
INX4
50k
INX3
50k
INX2
50k
INX1
VCT
GAINX2
GAINX1
GAINX34
INAOX
18
CXA1946CR
Fig. 2. Input Selector (2)
2. Volume
The volume circuit consists of two sections, an 8dB/step section and a 1dB/step section, as shown in Fig. 3.
This circuit also serves as a balance control because the volume for channel 1 and channel 2 can be set
independently.
To mute the output signal, send
dB data.
The input impedance is 9.5k
(typ.) for VRIN1 and VRIN2.
The output impedance for VOUT1 and VOUT2 is low impedance (roughly 0
). The volume step width and
gain are not affected by the load impedance.
3. Loudness
The configuration of the loudness circuit is shown in Fig. 3. C
LDHCX
and C
LDLCX
are connected externally,
and the loudness frequency characteristics are determined by these constants. The relationships between
C
LDHCX
/C
LDLCX
and the frequency characteristics are as follows:
1/f
L
= 2
C
LDLCX
R
1
1/f
H
= 2
C
LDHCX
R
2
The loudness characteristics are not affected by the load impedance of VOUT1 and VOUT2.
Loudness is turned on and off by serial data bit D5.
Fig. 3. Volume and Loudness
50k
INX4
50k
INX3
50k
INX2
50k
INX1
VCT
GAINX2
GAINX1
GAINX34
INAOX
VRINX (input impedance 9.5k
)
20k
Total 40k
ON
LOUD
R1
6.18k
25.7k
R2
8.92k
4.98k
20k
C
LDHCX
0.0022
C
LDLCX
0.047
LDHCX
LDLCX
VOUTX
Loudness
Volume
OFF
f
H
f
L
Loudness frequency
characteristics
19
CXA1946CR
4. Tone control
The configuration of the tone control circuit is shown in Fig. 4. C
TCLCX2
and C
TCHCX
are connected
externally, and the tone control frequency characteristics can be changed by changing these constants.
The relationships between C
TCLCX2
/C
TCHCX
and the frequency characteristics are as follows:
1/f
L
= 2
C
TCLCX2
(R
3
//R
4
)
1/f
H
= 2
C
TCHCX
R
5
The maximum bass boost and cut can be made smaller than in the Application Circuit by connecting an
external resistance to the TCLCX1 pin in series, or else connecting an external resistance to C
TCLCX2
in
parallel. (See Fig. 5.) Furthermore, the maximum treble boost and cut can be made smaller than in the
Application Circuit by connecting an external resistance to C
TCHCX
in series. (See Fig. 6.) However, when
these methods are used, variations in the absolute value of the CXA1946C internal resistance (20% max.)
and in the external resistance will cause variations in the tone control characteristics. Set these constants
after studying all considerations carefully. Note that when the method illustrated in the Application Circuit is
used, variations in the internal resistance of the CXA1946C have no effect on the tone control
characteristics.
The input impedance is 19k
(typ.) for TIN1 and TIN2.
The output impedance for TCO1 and TCO2 is low impedance (roughly 0
). The tone step width and gain
are not affected by the load impedance.
Fig. 4. Tone Control
TCOX
14.1k
14.1k
12k
TCLCX1
TCLCX2
C
TCLCX2
0.39
R4
8k
BASS
CUT
ON
OFF
ON
OFF
BOOST
14.1k
14.1k
12k
10k
10k
10k
10k
R5
5k
CUT
ON
OFF
ON
OFF
BOOST
TREBLE
TCHCX
C
TCHCX
0.0027
R3
8k
f
H
f
L
Tone control frequency
characteristics
input impedance
19k
TINX
20
CXA1946CR
Fig. 5. Method for Reducing Bass Boost/Cut
Fig. 6. Method for Reducing Treble Boost/Cut
5. Fader
The configuration of the fader circuit is shown in Fig. 7. The fader operates by specifying the amount of
attenuation for either the front or rear output signal and by specifying which output signal (front or rear) is to
be attenuated.
The input impedance is 24k
(typ.) for FDIN1 and FDIN2.
The output impedance for FNTO1, FNTO2, REO1, and REO2 is low impedance (roughly 0
). The gain and
fader step width are not affected by the load impedance.
Fig. 7. Fader
R4
8k
TCLCX1
TCLCX2
C
TCLCX2
R3
8k
(B)
RexB
R4
8k
TCLCX1
TCLCX2
C
TCLCX2
R3
8k
TINX
(A)
RexA
R3
5k
10k
10k
10k
10k
TCHCX
C
TCHCX
RexC
FDINX (input impedance 24k
)
FNTOX
Center
ATT
Center
ATT
REOX
21
CXA1946CR
6. VCT buffer
The internal circuit for the VCT pin is shown in Fig. 8.
This circuit generates the electric potential for the center between Vcc and GND (Vcc/2). The IC internal
operation reference potential is equal to the output potential of VCT buffer. The impedance for the VCT pin
(Pin 17) is high since it is connected to a bypass capacitor. Add an external buffer when using the electric
potential of the VCT pin as the external reference potential for the CXA1946.
Fig. 8. VCT Buffer
7. Serial data I/O
The serial data has a 32-bit structure as indicated in the specifications. Data input is conducted using three
inputs: DATA, CLK, and CE. DATA is shifted in the CXA1946C internal shift register at the rising edge of
CLK. The data in the shift register is latched at the falling edge of CE. Refer to this specification for details
on the timing.
The CXA1946C does not have a reset (initialize) pin. The internal shift register and latch are reset
automatically when power is first supplied to the IC. To execute a reset at other times, send the data
(statuses after reset ) shown in the item "RESET" of this specification to the CXA1946C.
8. Zero-cross detector (with timer)
Using the zero-cross detector, the internal latch data is overwritten the first time the input signal becomes
roughly 0 after serial data is sent (after CE goes low). This operation reduces noise when overwriting data.
Although there are usually no problems when a normal audio signal is input, in rare cases there may be
nothing except a large-amplitude input signal of the high band, causing the slew rate to become abnormally
high; the zero-cross detection signal is not output in such a case because the zero-cross detector response
speed is too slow. Another rare situation would be that the zero-cross detection signal is output very
infrequently because the input signal frequency is extremely low. In these types of instances, it is
conceivable that the internal latch data will not be overwritten after data is sent, or that it will take much time
until the data is overwritten. Therefore, to an external observer it will appear that the data is not being
overwritten regardless of the fact that data is being sent.
As a countermeasure, the IC is designed to permit the internal latch data to be forcibly overwritten if the
zero-cross detection signal is not output within a certain waiting period after the data is sent (after CE goes
low). This function is called the "timer." If the zero-cross detection signal is output within a certain waiting
period, the internal latch data is overwritten in synchronization with the zero-cross of the input signal.
The waiting period mentioned above can be changed according to the value of the external capacitor
connected to the TIMER pin. When the value of the capacitor is 0.01F, the waiting period is approximately
500s.
9. Power-off mute
When Vcc goes below 5V, the output stage bias of the fader output pins FNTO1, FNTO2, REO1, and
REO2 is turned off and the pins go to high impedance. This operation prevents popping noises caused by
the output pin potential deviating from Vcc/2 when the power is turned off.
V
CC
100k
100k
VCT
10
22
CXA1946CR
Connections and Characteristics of Each Block
In the Application Circuit, the signal path goes from the input selector to the volume (+loudness) to the tone
control to the fader. The sequence of the blocks in the signal path can be changed because the I/O pins for
each block are independent of each other. For example, it is possible to switch the sequence of the volume
circuit and the tone control so that the signal path goes from the input selector to the tone control to the volume
(+loudness) to the fader. When this connection method is used, the noise voltage in the fader output can be
reduced in actual use because the noise and signal up to the tone control are attenuated by the volume.
However, because the maximum output amplitude of the tone control circuit is limited by the supply voltage,
care should be given to the setting of the input signal level.
Although blocks in the Application Circuit are linked either by coupling capacitors or by direct connection, it is
also possible to insert external circuits between blocks. In this case, the gain will change according to the input
impedance of the following block and the impedance of the external circuit. In addition, the input impedance of
each block can vary by 20% due to the characteristics of the IC. Consequently, the overall gain also varies.
Give careful consideration to the effects of this variation when setting the constants. The step widths (control
characteristics) of the volume, tone control, and fader are not affected.
Timing Chart
t
1
t
ck
t
su
t
h
t
2
t
L
t
ce
CE
CLK
DATA
CE
t
1
0.5s
t
2
0.5s
t
ck
1.0s
t
su
0.5s
t
h
0.5s
t
L
t
T
+ 0.5s
(t
T
is the maximum value for the timer operation time)
t
ce
4.0s
D1
D2
D30
D31
D32
Invalid
Timer Waiting Period Setting Chart (Vcc = 6 to 12V, operating temperature = 35C to 85C)
TIMER pin
capacitance C
Waiting peroid
Min.
Typ.
Max.
C = 100pF
C = 0.001F
C = 0.01F
C = 0.1F
C = 1F
C = 10F
3s
30s
300s
3ms
30ms
300ms
5s
50s
500s
5ms
50ms
500ms
9s
90s
900s
9ms
90ms
900ms
23
CXA1946CR
Package Outline
Unit: mm
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY / PHENOL RESIN
SOLDER PLATING
42 ALLOY
PACKAGE STRUCTURE
48PIN LQFP (PLASTIC)
9.0 0.2
7.0 0.1
1
12
13
24
25
36
37
48
(0.22)
0.18 0.03
+ 0.08
0.5 0.08
(8.0)
0.5
0.2
0.127 0.02
+ 0.05
0.1 0.1
0.5
0.2
A
1.5 0.1
+ 0.2
0 to 10
DETAIL A
0.2g
LQFP-48P-L01
QFP048-P-0707-A
0.1
NOTE: Dimension "
" does not include mold protrusion.