--1--

E99213

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Absolute Maximum Ratings (Ta=25 °C, GND=0 V)

· Supply voltage

/R/G/B

· Operating temperature

Topr

20 to +75

°C

· Storage temperature

Tstg

65 to +150

°C

· Allowable power dissipation

2.05

Recommended Operating Conditions

Supply voltage

/R/G/B

12±0.5

5±0.5

Description

The CXA2067S is a bipolar IC developed for high-

resolution computer displays.

Features

· Wide-band amplifier: 170 MHz@3 dB (Typ)

· Input dynamic range: 1.0 Vp-p (typ)

· High gain preamplifier (17 dB)

· R, G and B in a single package (SDIP 30 pins)

· I

C bus control

Contrast control

Sub contrast control

Brightness control

OSD contrast control

Cut-off control: 4 channels of DAC output

2 blanking level modes

(0.5 V fixed, pedestal 0.3 V)

· Sync separator for sync-on-green

· Blanking mixing function

· OSC mixing function

· Video interval detection function

· VBLK sync DAC refresh system

· 12 V power supply interlocked power saving

function

Applications

High-resolution computer displays

Structure

Bipolar silicon monolithic IC

Preamplifier for High-Resolution Computer Display

30 pin SDIP (Plastic)

CXA2067S

--2--

CXA2067S

LPF

SDA

SCL

COF R

COF G

COF B

COF RGB

RIN

GIN

SYNC IN

BIN

CLP

OSD-R

OSD-G

OSD-B

CSYNC/VDET

S/H-R

ROUT

GND-R

S/H-G

GOUT

GND-G

S/H-B

BOUT

GND-B

BLKING

OSDSW

Rch

Bch

OSD YS
GENERATOR

GAIN
CONTROL
AMP

GAIN CONTROL DATA

SYNC SEP/VDET

VDET
COMPARATOR

SYNC
SEPARATOR

SVSW

SUB

CONTRAST

OSD SW

BLANKING

MODE

BLANKING PULSE

BRIGHTNESS

OSD GAIN (R)

OSD PULSE (13PIN)

YS PULSE (17PIN)

To each MODE SW

I C BUS

DECORDER

BLANKING
BUFFER AMP

Same as R channel

Gch

12V

D/A CONVERTOR

CONTRAST

SUB CONTRAST (R)

SUB CONTRAST (G)

SUB CONTRAST (B)

OSD GAIN (R)

OSD GAIN (G)

OSD GAIN (B)

BRIGHTNESS (RGB)

CUTOFF (R)

CUTOFF (G)

CUTOFF (B)

CUTOFF (RGB)

Block Diagram

--3--

CXA2067S

Pin Description

SDA

SCL

COF R

COF G

COF B

COF RGB

RIN

GIN

BIN

1.7 V

(Clamp)

5 V

10k

100

14k

300

C bus standard SDA

(serial data) input/output.

VILMAX=1.5 V

VIHMIN=3.5 V

VOLMAX=0.4 V

C bus standard SCL

(serial clock) input/output.

VILMAX=1.5 V

VIHMIN=3.5 V

DAC output for cut-off

adjustment.

Output DC is 1 to 4 V.

R, G and B signal inputs.

Input via a capacitor.

5 V power supply.

Symbol

Equivalent circuit

Description

No.

voltage

--4--

CXA2067S

SYNC IN

CLP

OSD-R

OSD-G

OSD-B

2.8 V

12 V

100

150

10k

Sync-on-green signal input.

Input via a capacitor.

Clamp pulse (positive polarity)

input.

VILMAX=0.8 V

VIHMIN=2.8 V

OSD control inputs.

VILMAX=0.8 V

VIHMIN=2.8 V

12 V power supply. (B channel)

YS (OSD BLK) control input.

VILMAX=0.8 V

VIHMIN=2.8 V

Symbol

Equivalent circuit

Description

No.

voltage

--5--

CXA2067S

BLKING

GND-B

GND-G

GND-R

BOUT

GOUT

ROUT

S/H-B

S/H-G

S/H-R

0 V

12 V

10k

30k

R/G/B

310

R/G/B V

R/G/B

300

Blanking pulse input.

Set the V blanking pulse width

to 300 µs or more.

VILMAX=0.8 V

VIHMIN=2.8 V

Ground.

R, G and B outputs.

Brightness sample-and-hold.

Connect to GND via a capacitor.

12 V power supply. (G channel)

12 V power supply. (R channel)

Symbol

Equivalent circuit

Description

No.

voltage

--7--

CXA2067S

Definitions of I

C Bus Register

Slave Address

SLAVE RECEIVER : 40 (HEX)

Register Table

SUB ADDRESS

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

CONTRAST

BLK MODE

BRIGHTNESS

CUT OFF R

CUT OFF G

CUT OFF B

VDET LEVEL

OSD GAIN

CUT OFF RGB

SUB CONTRAST R

SUB CONTRAST G

SUB CONTRAST B

VDET OFF

SVSW

VSOFF

Note)

: don't care

Sub Address CONTRAST (8):

Performs the gain control for R, G and B channels in common.

0000

Control is performed by the multiplication with SUB CONTRAST. The white

balance is adjusted by SUB CONTRAST and the luminance is adjusted by

CONTRAST.

0 : Gain minimum (30 dB or less)

255 : Gain maximum (+17 dB)

Sub Address BLK MODE (1):

Switches the blanking level.

0001

0 : Pedestal0.3 V

1 : 0.3 V fixed

Sub Address BRIGHTNESS (6): Performs the black level control for R, G and B channels in common.

0001

0 : Black level minimum (0.9 V)

63 : Black level maximum (2.8 V)

Sub Address CUT OFF R (8):

Performs the Pin 3 (COF R) output voltage control.

0010

0 : Output voltage minimum (1 V)

255 : Output voltage maximum (4 V)

Sub Address CUT OFF G (8):

Performs the Pin 4 (COF G) output voltage control.

0011

0 : Output voltage minimum (1 V)

255 : Output voltage maximum (4 V)

Sub Address CUT OFF B (8):

Performs the Pin 5 (COF B) output voltage control.

0100

0 : Output voltage minimum (1 V)

255 : Output voltage maximum (4 V)

--8--

CXA2067S

Sub Address VDET LEVEL (2):

Controls the signal detection (VDET) slice level.

0101

0 : Slice level minimum (RIN or GIN or BIN=30 mV)

1 : Slice level maximum (RIN or GIN or BIN=220 mV)

Sub Address OSD GAIN (6):

Performs the OSD gain control for R, G and B channels in common.

0110

Control is performed by the multiplication with SUB CONTRAST (upper 6

bits) so that the video white balance and tracking are obtained.

0 : Gain minimum (0 Vp-p)

63 : Gain maximum (5 Vp-p)

Sub Address CUT OFF RGB (8): Performs the Pin 6 (COF RGB) output voltage.

0110

0 : Output voltage minimum (1 V)

255 : Output voltage maximum (4 V)

Sub Address SUB CONTRAST R (8): Performs the R channel gain control.

0111

Control is performed by the multiplication with CONTRAST. Use for

the white balance adjustment.

0 : Gain minimum (30 dB or less)

255 : Gain maximum (+17 dB)

Sub Address SUB CONTRAST G (8): Performs the G channel gain control.

1000

Control is performed by the multiplication with CONTRAST. Use for

the white balance adjustment.

0 : Gain minimum (30 dB or less)

255 : Gain maximum (+17 dB)

Sub Address SUB CONTRAST B (8): Performs the B channel gain control.

1001

Control is performed by the multiplication with CONTRAST. Use for

the white balance adjustment.

0 : Gain minimum (30 dB or less)

255 : Gain maximum (+17 dB)

Sub Address VDET OFF (1):

Performs the Pin 30 output control.

1010

0 : Output ON

1 : Output OFF

Sub Address SV SW (1):

Switches the Pin 30 output signal (sync separator/video detector).

1010

0 : Sync separator output

1 : Video detector output

Sub Address VS OFF (1):

Performs the control of VBLK sync DAC refresh function.

1010

0 : Function operation ON

1 : Function operation OFF

--9--

CXA2067S

C Bus Logic System

No.

Item

High level input voltage

Low level input voltage

Low level output voltage with 3 mA

SDA current inflow

Maximum clock frequency

Minimum waiting time for data change

Minimum waiting time for data

transmission start

Low level clock pulse width

High level clock pulse width

Minimum waiting time for start

preparation

Minimum data hold time

Minimum data preparation time

Rise time

Fall time

Minimum waiting time for stop

preparation

Symbol

SCL

BUF

: STA

LOW

HIGH

: STA

: DAT

: STO

Min.

3.0

4.0

4.7

4.0

4.7

250

4.7

Typ.

Max.

5.0

1.5

0.4

400

300

Unit

kHz

µs

--10--

CXA2067S

Electrical Characteristics

No.

Measurement item

Current consumption

(5 V)

Current consumption

(12 V)

Current consumption

(12 V OFF)

Frequency response

(50 MHz)

Frequency response

(100 MHz)

Contrast control 1

Contrast control 2

Sub contrast

control

Symbol

F50

F100

GCONT1

GCONT2

GSUB

Measurement contents

(5 V) pin inflow current

RGB signal input: None

R/G/B (12 V) pin inflow current

RGB signal input: None

pin inflow current for 12 V OFF

RGB signal input: None

Input the continuous 1 MHz, 50 MHz and 100

MHz sine waves (0.7 Vp-p). Measure the

output amplitude gain difference at this time.

Vout (50 MHz)

Gain difference [dB]=20 log

Vout (1 MHz)

Vout (100 MHz)

Gain difference [dB]=20 log

Vout (1 MHz)

Measure the output signal amplitude Vout

level when a 0.7 Vp-p video signal is input.

GCONT1 : Contrast=SubContrast=FF

GCONT2 : Contrast=00/SubContrast=FF

Measure the output signal amplitude Vout

level when a 0.7 Vp-p video signal is input.

Contrast=FF/SubContrast=00

Min.

Typ.

Max.

Unit

115

140

29.5

55.5

1.5

1.9

3.0

5.6

6.2

Vp-p

100 mVp-p

0.7Vp-p

GND

CLP potential (Approx. 1.7 V)

RGB input signal (RGB input pins)

0.7Vp-p

Input signal

0.7Vp-p

Input signal

--11--

CXA2067S

Min.

Typ.

Max.

Unit

4.5

Vp-p

150 mVp-p

0.4

0.7

2.2

2.6

0.3

0.6

0.3

0.6

No.

Measurement item

OSD gain control

Brightness control

BLK control

(BLK MODE=0)

BLK control

(BLK MODE=1)

Sync separator

output rise delay

Sync separator

output fall delay

VDET output

rise delay

VDET output

fall delay

Symbol

GOSD1

GOSD2

VBRT1

VBRT2

VBLK1

VBLK2

SDLYR

SDLYF

DDLYR

DDLYF

Measurement contents

Measure the OSD level of the output

signal when the OSD pulse is input.

GOSD1 : OSD=3F/SubContrast=FF

GOSD2 : OSD=00/SubContrast=FF

Measure the black level of the RGB output

signal.

VBRT1 : Brightness=00

VBRT2 : Brightness=3F

Measure the BLK level of the output signal

when the BLK pulse is input.

RGB output signal

OSD interval

OSD
level

GND

Black level

RGB output signal

GND

BLK level (VBLK1)

BLK level (VBLK2)

Vth=50%

Rise Delay

Fall
Delay

Vth=50%

Rise
Delay

Fall
Delay

0.7Vp-p

--12--

CXA2067S

Min.

Typ.

Max.

Unit

1.3

3.9

3.85

Vp-p

No.

Measurement item

DAC

output voltage

(COFF=00)

DAC

output voltage

(COFF=FF)

VDET output

amplitude

Symbol

VCUT1

VCUT2

VDET

Measurement contents

Measure the DAC output voltage (Pin 6)

for COFF=00/FF.

Input the crosshatch signal of

DotClock=100 MHz/0.7 Vp-p and measure

the VDET output amplitude.

SW SW=1/VDET LEVEL=0

0.7Vp-p

Input signal

10ns

--13--

CXA2067S

Electrical Characteristics Measurement Circuit

SYNC SEP/VDET Output

0.1

SDA

SCL

COF R

COF G

COF B

COF RGB

RIN

GIN

SYNC IN

BIN

CLP

OSD-R

OSD-G

OSD-B

CSYNC/VDET

S/H-R

ROUT

GND-R

S/H-G

GOUT

GND-G

S/H-B

BOUT

GND-B

BLKING

12V

0.1

12V

0.1

12V

220

I C BUS

DAC Output

0.1

Rch Output

Gch Output

Bch Output

--14--

CXA2067S

Electrical Characteristics Measurement Circuit (Frequency response)

SYNC SEP/VDET Output

0.1

SDA

SCL

COF R

COF G

COF B

COF RGB

RIN

GIN

SYNC IN

BIN

CLP

OSD-R

OSD-G

OSD-B

CSYNC/VDET

S/H-R

ROUT

GND-R

S/H-G

GOUT

GND-G

S/H-B

BOUT

GND-B

BLKING

12V

0.1

12V

0.1

12V

220

I C BUS

DAC Output

0.1

Rch Output

Gch Output

Bch Output

0.1

--15--

CXA2067S

The VBLK signal is extracted form the composite BLK signal input to Pin 18. The DAC data rewrite for each control is simultane

ously performed,

synchronizing to the VBLK signal. The received I

C bus data is held by the latch till the next VBLK signal comes. Therefore, the timing of I

C bus data

transmission from the microcomputer is free. The V blanking pulse width input to Pin 18 should be 300

s or more.

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VBLK Sync DAC Refresh System

--16--

CXA2067S

Application Circuit

SYNC SEP/VDET Output

0.1

SDA

SCL

COF R

COF G

COF B

COF RGB

RIN

GIN

SYNC IN

BIN

CLP

OSD-R

OSD-G

OSD-B

CSYNC/VDET

S/H-R

ROUT

GND-R

S/H-G

GOUT

GND-G

S/H-B

BOUT

GND-B

BLKING

12V

0.1

12V

0.1

12V

220

I C BUS

DAC Output

0.1

Rch Output

Gch Output

Bch Output

YS input

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

--17--

CXA2067S

Notes on Operation

1. The ROUT, GOUT and BOUT outputs should be received in the high impedance state.

2. The wiring from ROUT, GOUT and BOUT to the power amplifier should be as short as possible.

3. For the decoupling capacitors for V

and V

R/G/B, the ceramic capacitor and the electrolysis capacitor

should be connected in parallel as closely to the IC as possible.

4. The clamp capacitors for RIN, GIN, BIN, S/H R, S/H G and S/H B should be connected as close to the IC

as possible.

5. The signals to RIN, GIN and BIN should be input via a clamp capacitor with the low impedance.

6. Set the output OFF when the VDET output is not used (The cross talk may deteriorate).

SONY CODE

EIAJ CODE

JEDEC CODE

30PIN SDIP (PLASTIC)

26.9 0.1

+ 0.4

1.778

.
1

.
5

.
1

.
3

0° to 15°

0.5 ± 0.1

0.9 ± 0.15

.
0

I
N

.
5

I
N

.
7

.
1

.
4

SDIP-30P-01

SDIP030-P-0400

PACKAGE STRUCTURE

MOLDING COMPOUND

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN

PLATING

COPPER ALLOY

1.8g

SOLDER/PALLADIUM

1.All mat surface type.

Two kinds of package surface:

2.All mirror surface type.

Package Outline Unit : mm

CXA2067S

--18--

Sony Corporation

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA2067S

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA2067S