--1--

E96Y05B81

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Absolute Maximum Ratings (Ta=25 °C)

· Supply voltage

· Operating temperature

Topr

20 to +75

°C

· Storage temperature

Tstg

65 to +150

°C

· Allowable power dissipation

1300

Operating Conditions

Supply voltage

9±0.5

Description

The CXA2069Q is a 7-input, 3-output audio/video

switch featuring I

C bus compatibility for TVs. This

IC has input pins that are compatible with S2

protocol.

Features

· 4 inputs that are compatible with S2 protocol

· Serial control with I

C bus

· 7 inputs, 3 outputs

· The desired inputs can be selected independently

for each of the 3 outputs

· Wide band video amplifier (20 MHz, 3 dB)

· Y/C MIX circuit

· Slave address can be changed (90H/92H)

· Audio muting from external pin

· High impedance maintained by I

C bus lines (SDA,

SCL) even when power is OFF

· Wide audio dynamic range (3 Vrms typ.)

Applications

Audio/video switch featuring I

C bus compatibility

for TVs

Structure

Bipolar silicon monolithic IC

S2-Compatible 7-Input 3-Output Audio/Video Switch

64 pin QFP (Plastic)

CXA2069Q

--2--

CXA2069Q

Block Diagram

6dB

VOUT1

YIN1

YOUT1

TRAP1

COUT1

CIN1

V/YOUT2

TRAP2

COUT2

VOUT3

YOUT3

COUT3

BIAS

VGND

BIAS

6dB

0dB

6dB

0dB

6dB

AGND

LOUT1

ROUT1

LOUT2

ROUT2

LOUT3

ROUT3

Logic

DC OUT

SCL

SDA

ADR

S-1

S-2

S-3

S-4

S2-1

S2-2

S2-3

S2-4

MUTE

LTV

LV1

LV2

LV3

LV4

LV5

LV6

RTV

RV1

RV2

RV3

RV4

RV5

RV6

Audio system is attenuated by 6dB at input,
and a total gain is 0dB (LOUT1 and ROUT1
can be changed to 6dB).

--3--

CXA2069Q

Pin Configuration

-
4

-
3

-1

S-1

S-2

-2

CIN

BIA

YIN

V/Y

--4--

CXA2069Q

Pin Description

Symbol

Equivalent circuit

Description

No.

voltage

62, 2

9, 16

23, 29

59, 64

4, 11

18, 25

31, 61

YIN1

CIN1

LTV, LV1

LV2, LV3

LV4, LV5

LV6, RTV

RV1, RV2

RV3, RV4

RV5, RV6

VOUT1

VOUT3

4.0 V

4.5 V

3.9 V

150

3µA

150

3µA

150

27k

20k

15k

33k

27k

23.5k

30k

250

Video signal inputs.

Input composite video signals.

Y/C separation signal inputs.

Input luminance signals.

The YIN1 pin inputs the signal

obtained by Y/C separating the

VOUT1 pin output.

Y/C separation signal inputs.

Input chrominance signals.

The CIN1 pin inputs the signal

obtained by Y/C separating the

VOUT1 pin output.

Audio signal inputs.

Video signal outputs.

Output composite video signals.

--5--

CXA2069Q

Symbol

Equivalent circuit

Description

No.

voltage

V/YOUT2

YOUT1

YOUT3

COUT1

COUT2

COUT3

LOUT1

LOUT2

LOUT3

ROUT1

ROUT2

ROUT3

S2-1

S2-2

S2-3

S2-4

3.8 V

3.3 V

3.8 V

4.5 V

4.5V

20k

147

100k

Video signal output.

Either composite video signal output

or luminance signal output can be

selected by I

C bus control.

Video signal outputs.

Output luminance signals.

Video signal outputs.

Output chrominance signals.

Audio signal outputs.

Zo=50

(within DC ±2 mA)

Detects the S2-compatible DC

superimposed onto the C signal.

4 : 3 video signal at 1.3 V or less

4 : 3 letter-box signal at 1.3 V or more

to 2.5 V or less

16 : 9 picture squeezed signal at 2.5 V

or more

This pin is pulled down to GND by a

100 k

resistor, so the 4 : 3 video

signal is selected when open.

--6--

CXA2069Q

Symbol

Equivalent circuit

Description

No.

voltage

S-1

S-2

S-3

S-4

ADR

SCL

SDA

50k

100k

50k

147

72k

28k

10.5k

Composite video/S selector.

The detection results are written

to the status register.

S signal at 3.5 V or less

Composite video signal at 3.5 V

or more

This pin is pulled up to 5 V by a 100 k

resistor, so the composite video signal

is selected when open.

Selects the slave address

for the I

C bus.

90H at 1.5 V or less

92H at 2.5 V or more

90H when open.

C bus signal input

max=1.5 V

min=3.0 V

C bus signal input

max=1.5 V

min=3.0 V

max=0.4 V

--7--

CXA2069Q

Symbol

Equivalent circuit

Description

No.

voltage

DC_OUT

TRAP1

TRAP2

MUTE

BIAS

3.8 V

4.5 V

100

147

72k

28k

147

20k

Outputs the S2-compatible DC

superimposed onto the COUT3 output.

The DC is superimposed by connecting

this pin to the COUT3 output via a

capacitor.

Control is performed by the I

C bus.

When 0 V is output, Q1 is ON and the

impedance is 5 k

S2 protocol output impedance of

10 ±3 k

is realized by attaching

external resistance of 4.7 k

DC_OUT (bus)

Output DC

4.5 V

0 V

1.9 V

4.5 V

Connects trap circuit for subcarrier.

Audio signal output mute.

Mute OFF at 1.5 V or less

Mute ON at 2.5 V or more

Mute OFF when open.

Internal reference bias (V

/2).

Connect to GND via a capacitor.

28k

--8--

CXA2069Q

Electrical Characteristics

(Ta=25 °C V

=9 V)

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

Current consumption

No signal, no load

Video system (Measurement circuit ; Fig. 1)

Gain

Frequency response

characteristics

Frequency response

characteristics (Y/C mix)

Input dynamic range

Cross talk

GVv

FBWv1

FBWv2

Ddv

Vctv

f=100 kHz, 0.3 Vp-p input

f=100 kHz, input frequency where output

amplitude is 3 dB with 0.3 Vp-p output

serving as 0 dB

f=100 kHz, maximum with

distortion < 1.0 %

f=4.43 MHz, 1 Vp-p input

5.9

6.4

6.9

MHz

1.4

Vp-p

Audio system (Measurement circuits ; Fig. 2 to Fig. 5)

Gain

Frequency response

characteristics

Total harmonic

distortion

Input dynamic range

Cross talk

Ripple rejection ratio

Output DC offset

Residual noise

S/N ratio

FBW

THD

Vct

Voff

S/N

f=1 kHz, 1 Vp-p input, 5.7 k

resistor inserted to input

f=1 kHz, input frequency where output

amplitude is 3 dB with 1 Vp-p output

serving as 0 dB

f=1 kHz, 2.2 Vp-p input, where 400 Hz

HPF+80 kHz LPF are inserted

f=1 kHz, maximum with distortion < 0.3 %

f=1 kHz, 1 Vp-p input

f=100 Hz, 0.3 Vp-p applied to V

Offset voltage between input and output

When 400 Hz HPF+30 kHz LPF

are inserted

f=1 kHz, 1 Vrms input

=400 Hz, f

=30kHz

kHz

0.03

0.05

2.8

3.0

Vrms

µVrms

100

--9--

CXA2069Q

Logic system

High level

input voltage

Low level

input voltage

Low level

output voltage

High level

input current

Low level

input current

Maximum clock

frequency

Minimum waiting time

for data change

Minimum waiting time

for data transfer start

Low level clock

pulse width

High level clock

pulse width

Minimum waiting time

for start preparation

Minimum data

hold time

Minimum data

preparation time

Rise time

Fall time

Minimum waiting time

for stop preparation

SCL

BUF

HD;STA

LOW

HIGH

SU;STA

HD;DAT

SU;DAT

SU;STO

With SDA 3 mA current supplied

=4.5V

=0.4V

3.0

5.0

1.5

0.4

µA

100

kHz

4.7

µs

4.0

µs

4.7

µs

4.0

µs

4.7

µs

300

250

µs

300

4.7

µs

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

--10--

CXA2069Q

.
4

.
1

1µ

ADR

RV5

LV5

S-4

S2-4

RV4

LV4

S-3

S2-3

LOUT1

VOUT1

ROUT1

TRAP1

YOUT1

VGND

COUT1

LV6

RV6

LTV

RTV

CXA2069Q

.
1

10µ

22µ

µcon

10µ

10k

10µ

10k

10µ

10k

10µ

10k

10µ

10k

1µ

600

0.47µ

1µ

600

1µ

600

0.47µ

1µ

600

.
4

.
1

.
4

.
1

.
4

Measurement point

600

0.47µ

1µ

600

0.1µ

1µ

600

0.47µ

1µ

600

0.47µ

Input signal

-
1

-
2

I
N

I
A

I
N

/
Y

Signal is input from one of the following pins: 1, 3, 5, 8, 10, 12, 15, 17, 19, 22, 24, 26, 30, 60 and 63.
Output signal is measured from one of the following pins: 37, 39, 41, 44, 47, 53, 56 and 58.

.
4

.
1

1µ

ADR

RV5

LV5

S-4

S2-4

RV4

LV4

S-3

S2-3

LOUT1

VOUT1

ROUT1

TRAP1

YOUT1

VGND

COUT1

LV6

RV6

LTV

RTV

CXA2069Q

.
1

10µ

22µ

µcon

10µ

10k

10µ

10k

10µ

10k

10µ

10k

10µ

10k

1µ

600

0.47µ

1µ

600

1µ

600

0.47µ

1µ

600

.
4

.
1

.
4

.
1

.
4

Measurement point

600

0.47µ

1µ

600

0.1µ

1µ

600

0.47µ

1µ

600

0.47µ

Input signal

.
7

5.7k

I
N

I
A

I
N

/
Y

-
1

-
2

5.7k

Signal is input from one of the following pins: 2, 4, 9, 11, 16, 18, 23, 25, 29, 31, 59, 61, 62 and 64.
Output signal is measured from one of the following pins: 38, 40, 43, 45, 52 and 54.

Fig. 1 Video system (gain, frequency response characteristics, input dynamic range, cross talk) measurement circuit

Fig. 2 Audio system (gain, frequency response characteristics,

total harmonic distortion, input dynamic range, cross talk) measurement circuit

--11--

CXA2069Q

.
4

.
1

1µ

ADR

RV5

LV5

S-4

S2-4

RV4

LV4

S-3

S2-3

LOUT1

VOUT1

ROUT1

TRAP1

YOUT1

VGND

COUT1

LV6

RV6

LTV

RTV

CXA2069Q

.
1

10µ

µcon

10µ

10k

10µ

10k

10µ

10k

10µ

10k

10µ

10k

1µ

600

0.47µ

1µ

600

1µ

600

0.47µ

1µ

600

.
4

.
1

.
4

.
1

.
4

Measurement point

600

0.47µ

1µ

600

0.1µ

1µ

600

0.47µ

1µ

600

0.47µ

,

0

.
3

-
p

I
N

I
A

I
N

/
Y

-
1

-
2

A f=100Hz, 0.3Vp-p signal is applied to Vcc and the output signals from Pins 38, 40, 43, 45, 52 and 54 are measured.

.
4

.
1

1µ

ADR

RV5

LV5

S-4

S2-4

RV4

LV4

S-3

S2-3

LOUT1

VOUT1

ROUT1

TRAP1

YOUT1

VGND

COUT1

LV6

RV6

LTV

RTV

CXA2069Q

.
1

10µ

22µ

µcon

10µ

10k

10µ

10k

10µ

10k

10µ

10k

10µ

10k

1µ

600

0.47µ

1µ

600

1µ

600

0.47µ

1µ

600

.
4

.
1

.
4

.
1

.
4

Measurement point

600

0.47µ

1µ

600

0.1µ

1µ

600

0.47µ

1µ

600

0.47µ

.
7

5.7k

Measurement point

I
N

I
A

I
N

/
Y

-
1

-
2

Fig. 3 Audio system (ripple rejection ratio) measurement circuit

Fig. 4 Audio system (output DC offset voltage) measurement circuit

--12--

CXA2069Q

.
4

.
1

1µ

ADR

RV5

LV5

S-4

S2-4

RV4

LV4

S-3

S2-3

LOUT1

VOUT1

ROUT1

TRAP1

YOUT1

VGND

COUT1

LV6

RV6

LTV

RTV

CXA2069Q

.
1

10µ

22µ

µcon

10µ

10k

10µ

10k

10µ

10k

10µ

10k

10µ

10k

1µ

600

0.47µ

1µ

600

1µ

600

0.47µ

1µ

600

.
4

.
1

.
4

.
1

.
4

Measurement point

600

0.47µ

1µ

600

0.1µ

1µ

600

0.47µ

1µ

600

0.47µ

40dB

4.5V

I
N

I
A

I
N

/
Y

-
1

-
2

Fig. 5 Audio system (residual noise) measurement circuit

--13--

CXA2069Q

Application Circuit

0.4

7µ

1µ

0.4

7µ

1µ

0.1

1µ

0.4

7µ

1µ

0.4

7µ

1µ

0.1

1µ

0.4

7µ

1µ

0.4

7µ

1µ

0.1

1µ

.
4

.
1

.
4

-
4

-
3

.
4

.
1

I
L

.
4

0µ

.
1

I
D

t
p

I
D

t
p

I
D

i
n

I
D

i
n

I
D

i
n

VID

utp

VID

CIN

BIA

YIN

V/Y

-1

S-1

S-2

-2

r
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t
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Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility fo

any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same

--14--

CXA2069Q

C BUS Control Signal

Fig. 6 I

C BUS Control Signal Timing Chart

Description of Operation

The CXA2069Q is a TV I

C bus-compatible AV switch IC. The video system and the stereo audio system

both have 7 inputs and 3 outputs each. 4 of the 7 video system inputs support S2 and S protocols.

The desired inputs can be independently assigned to each output (in the audio system, the left and right

channels are processed as one unit) by I

C bus control. However, the same input is assigned to both the

video and audio system output 3.

C BUS Registers

1) I

C BUS

The I

C bus (inter-IC bus) is an inter-IC bus system developed by Philips. Two lines (SDAserial data,

SCLserial clock) provide control over start, stop, data transfer, synchronization, and collision

avoidance. The IC outputs are either open collector or open drain, forming a bus line in the wired OR

format.

S : Start condition ; SDA is set "Low" when SCL is "High"

P : Stop condition ; SDA is set "High" when SCL is "High"

A : Acknowledge ; signal sent from the slave

Data is transmitted by MSB-first. One data unit consists of 8 bits, to which the acknowledge signal, which

indicates that the data has been accepted by the slave, is attached at the end. Normally, the slave

receives data at the rising edge of SCL and the master

IC changes data at the falling edge of SCL.

Slave : An IC that is placed under the control of the master.

In a normal system, all devices excluding the central microcomputer are slaves.

Master : A central microcomputer or other controlling IC.

BUF

LOW

;

STA

;

DAT

HIGH

;

DAT

;

STA

;

STO

SDA

SCL

SDA

MSB

LSB

MSB

LSB

SCL

--15--

CXA2069Q

2) Control Registers

The CXA2069Q control is exercised by writing 3-byte data into the three 8-bit control registers which

control the output selector circuits for the 3 outputs.

S ; Start condition

A ; Acknowledge

P ; Stop condition

O Control register structure (DATA1 to DATA3)

· All registers are set to "0" during IC power on.

· "

" indicates undefined.

Slave address

DATA1

DATA2

DATA3

Slave add.

DATA1

DATA2

DATA3

ADR

R/W

A-GAIN

S/COMP1

V-IN1

A-IN1

V/YOUT S/COMP2

V-IN2

A-IN2

S/COMP3

AV-IN3

DC OUT

R/W (1) : Read/write mode

0 : Control data write

1 : Status register read

ADR (1) : This bit sets the slave address set by the address pin.

0 : 90H

1 : 92H

A-GAIN (1) : LOUT1/ROUT1 output gain selector

0 : 0 dB output

1 : 6 dB output

S/COMP1 to S/COMP3 (1 each) : S terminal input/composite signal input selectors

By setting S/COMP1 to "0", when composite signal input is selected, YOUT1/COUT1 output the

inputs from YIN1/CIN1 during video 1 output.

0 : Composite signal inputs (TV, V1 to V6 inputs)

1 : S terminal inputs (Y1/C1 to Y4/C4 inputs)

V/YOUT (1) : This bit selects the output to Pin 44 (V/YOUT2).

0 : VOUT (composite signal) output

1 : YOUT (luminance signal) output

V-IN1 to V-IN2 (3 each) : These bits select the input signals output to each video output.

V-IN1 corresponds to the VOUT1 and YOUT1/COUT1 outputs, and V-IN2 to the VOUT2 and

YOUT2/COUT2 outputs.

0 : Mute

4 : Selects the V3 and Y3/C3 inputs

1 : Selects the TV input

5 : Selects the V4 and Y4/C4 inputs

2 : Selects the V1 and Y1/C1 inputs

6 : Selects the V5 input

3 : Selects the V2 and Y2/C2 inputs

7 : Selects the V6 input

--16--

CXA2069Q

A-IN1 to A-IN2 (3 each) : These bits select the input signals output to each audio output.

A-IN1 corresponds to the LOUT1/ROUT1 outputs, and A-IN2 to the LOUT2/ROUT2 outputs.

0 : Mute

4 : Selects the LV3/RV3 inputs

1 : Selects the LTV/RTV inputs

5 : Selects the LV4/RV4 inputs

2 : Selects the LV1/RV1 inputs

6 : Selects the LV5/RV5 inputs

3 : Selects the LV2/RV2 inputs

7 : Selects the LV6/RV6 inputs

AV-IN3 (3) : This bit selects the input signals output to output 3.

Both the video output and the audio output are selected at the same time only for AV-IN3.

0 : Mute

4 : Selects the V3, Y3/C3 and LV3/RV3 inputs

1 : Selects the TV and LTV/RTV inputs

5 : Selects the V4, Y4/C4 and LV4/RV4 inputs

2 : Selects the V1, Y1/C1 and LV1/RV1 inputs 6 : Selects the V5 and LV5/RV5 inputs

3 : Selects the V2, Y2/C2 and LV2/RV2 inputs 7 : Selects the V6 and LV6/RV6 inputs

DC OUT (2) : These bits set the DC voltage output from Pin 35 (DC OUT).

0 : 4.5 V

1 : 0 V

2 : 1.9 V

3 : 4.5 V

3) Status Registers

· When reading two bytes

· When reading one byte

S ; Start condition

A ; Acknowledge

NA ; No acknowledge

P ; Stop condition

When communication is to be terminated in the status register reading mode, the "no-acknowledge"

signal is needed to assure that the master does not issue the acknowledge signal to the slave.

It is possible to read only DATA1 of the status register by sending the no-acknowledge signal after

DATA1.

O Status register structure (DATA1 to DATA2)

Slave address

DATA1

DATA2

Slave address

DATA1

Slave add.

DATA1

DATA2

ADR

S1SEL

S2SEL

S3SEL

S4SEL

S-C1

S-C2

S1SEL

S2SEL

S3SEL

S4SEL

S-C3

S-C4

--17--

CXA2069Q

S1SEL to S4SEL (1 each) : S-1 to S-4 pin status

0 ; S-1 to S-4 pins are not grounded.

1 ; S-1 to S-4 pins are grounded.

S1SEL to S4SEL are actually determined by

comparing the S-1 to S-4 pin DC voltages with

3.5 V.

S-C1, S-C2, S-C3, S-C4 (2 each) : S2-1, S2-2, S2-3 and S2-4 pin status

0 ; 4 : 3 video signal

1 ; 4 : 3 letter-box signal

2 ; 16 : 9 video squeezed signal

3 ; No signal

S-C1 to S-C4 are actually determined by

comparing the S2-1 to S2-4 pin DC voltages

with two threshold. However, when the S-1 to

S-4 pins are open, the outputs are fixed to "3".

4) Power-on Reset

The CXA2069Q has an internal power-on reset function that sets each control register to "0" during IC

power ON.

The power-on reset V

has hysteresis.

S-1 to S-4 pin DC voltage

3.5 V or more

3.5 V or less

S1SEL to S4SEL

S2-1 to S2-4 pin DC voltage

1.3 V or less

1.3 V or more to 2.5 V or less

2.5 V or more

S-1 to S-4 OPEN

S-C1 to S-C4

4.5V

5.6V

Power-on reset

released

--18--

CXA2069Q

Video system frequency response characteristics

Frequency [Hz]

i
d

t
e

i
n

t
/
o

t
p

t

g

i
n

[
d

]

10M

100M

Audio system frequency response characteristics

Frequency [Hz]

i
o

t
e

i
n

t
/
o

t
p

t

g

i
n

[
d

]

10k

100k

Audio system distortion vs. Input amplitude

Input amplitude [Vrms]

t
a

l

h

r
m

i
c

i
s

t
o

r
t
i
o

[
%

]

0.1

0.01

0.002

f=1kHz
400Hz HPF, 80kHz LPF

100k

Y1/C1 to Y4/C4

VOUT1 to VOUT3

L/RTV, L/R1 to L/R6

LOUT1 (6dB)

LOUT2 and
LOUT 3 outputs

LOUT1 output (0dB gain)

TV, V1 to V6

VOUT1 to VOUT3

Y1 to Y4

YOUT1 to YOUT3

C1 to C4

COUT1 to COUT3

L/RTV, L/R1 to L/R6

LOUT1 (0dB)

L/RTV, L/R1 to L/R6

LOUT2 to LOUT3

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA2069Q

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA2069Q