CXA2161R

C Bus Compatible Audio Video (AV) Switch & Electronic Volume Control

Description

The Sony CXA2161R is an Audio/Video switch

designed primarily for application in Digital Set Top

Boxes. It provides video and audio routing from the

digital encoder source to the TV and VCR scart (peri-

television) connectors. In addition, the TV audio

output has a programmable volume control. The chip

is programmed by means of an I

C interface and can

operate from a single or dual power supply.

Target specifications: Canal+, BSkyB, TPS, NorDig,

and ECCA Euro-Box

Features

Supply

· Single: 0V, +5V, +12V

· Dual:

0V, 5V, +5V and +12V

(Low number of external parts required)

Video

· 2 scart switching (VCR, TV)

· VCR input supports RGB mode

· Integrated 75

drivers for direct video connection

· Y/C mixer with trap for RF modulators

· Switchable clamps on inputs

· Adjustable gain on RGB outputs

· Video output shutdown for low power modes

· Fast blanking switch

· Slow blanking switch for TV and VCR output

· SVHS switch on VCR output

· Y/C auxiliary input

Audio

· Four stereo audio inputs

· Volume control (56dB to +6dB in 2dB steps)

· Additional switchable gain on audio DAC inputs

· Audio overlay facility

· Volume bypass for TV and Phono outputs

· Mono switching on TV, VCR outputs

· High drive capability (600

loads possible)

· Switchable audio limiter function

· Switchable Mono output for RF modulators

· Audio output disable

C and Logic

· Fast mode compatible I

C bus

· Function monitor with loop through

· Interrupt output for function monitor

· Logic output pin

· Sync detector for Y/CVBS inputs

Applications

· Digital Set Top Box

· Integrated digital television

Structure

Bipolar silicon monolithic IC

Absolute Maximum Ratings (Ta = 25°C)

unless stated

· Supply voltage

· Storage temperature

Tstg

65 to +150

°C

· Allowable power dissipation

1.1

(when mounted on the board)

Operating Conditions

· Single supply

12 ± 0.6

5 ± 0.25

· Dual supply

5 ± 0.25

12 ± 0.6

· Operating temperature

Topr

20 to +75

°C

E00202-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

56 pin LQFP (Plastic)

CXA2161R

Block Diagram

(1) Video and Digital Section

Note) All video outputs contain 75

drivers, except VOUT_7 (Pin 38).

0/6/12V

FBLK_SW

VIDEO SWITCH1 (TV)

RGB Gain Control
(+1, 2, 3dB)

VIDEO SWITCH2 (VCR)

DC Restore

DC Restore/Tip

DC Restore/C bias

C bias

DC Restore/C bias

C bias

Clamp Cntl

Tip

Bias

Mute

Sync
Detect

DC Restore

Monitor

3.3V or 5V
Fast Mode
Compatible

Logic

Interrupt
Control

Output
disable

Output
disable &
Bi-drection
Control

Output
disable

MIX_SW

TV_FBLK

FBLK_IN1

+3.5V

FBLK_IN2

VIN_1

VIN_2

VIN_3

VIN_4

VIN_5

VIN_6

VIN_7

VIN_13

VIN_8

VIN_9

VIN_10

VIN_11

VIN_12

SYNC_ID

AUD_BIAS

VID_BIAS

+5V/12V_V

5V_GNDA

+5V_DIG

GND_DIG

+5V_VOUT

GND_VID

+5V_VID

+12V_DIG

SDA

SCL

FNC_VCR

DIG

VCR

DIG BLUE

VCR BLUE

DIG GREEN/CVBS

VCR GREEN

DIG RED/CHROMA

DIG CHROMA

VCR RED/CHROMA

AUX CHROMA

DIG CVBS/LUMA

VCR CVBS/LUMA

TV CVBS

AUX Y/CVBS

VCR

Typical Connection

VOUT_1
TV BLUE

VOUT_2
TV GREEN

VCR

RF MOD

MICRO

VOUT_3
TV RED/C

VOUT_4
TV CVBS/Y

VOUT_5
VCR CHROMA

VOUT_6
VCR CVBS/Y

TRAP

VOUT_7
(CVBS)

FNC_TV

INTRUPT

LOGIC

CXA2161R

(2) Audio section

l

B

(
T

)

I
O

I
T

(
T

)

/
0

/
+

/
0

/
+

I
O

I
T

(
V

)

I
N

(
D

I
G

)

l
a

t
o

I
N

(
V

)

I
N

(
T

/
O

)

I
N

(
A

)

I
N

(
D

I
G

)

I
N

(
V

)

I
N

(
T

/
O

)

I
N

(
A

)

r
l
a

/
o

f
f

i
x

r
l
a

/
o

f
f

i
a

t
e

i
m

i
t
e

.
2

r
m

t
p

i
s

l
e

i
m

i
t
e

.
2

r
m

l
u

t
r
o

t
o

l

B

(
P

)

i
t
c

/
L

i
t
c

/
L

i
t
c

l

B

(
T

)

l

B

(
P

)

CXA2161R

Pin Configuration

VOUT_4

+5V_VOUT

VOUT_3

VOUT_2

VOUT_1

+5V_VID

VID_BIAS

VIN_1

VIN_3

VIN_5

VIN_6

VIN_8

VIN_9

VIN_12

I
N

I
D

I
N

l
N

I
N

I
G

I
N

I
G

I
N

I
D

I
N

I
C

l
N

ROUT1

LOUT1

RTV

LTV

+5V/12V_V

RIN_1

LIN_1

5V_GNDA

RIN_2

LIN_2

AUD_BIAS

RIN_3

LIN_3

+12V_DIG

CXA2161R

Electrical Characteristics

Nominal conditions (Ta = 25°C)

+12 supply, no signal, no load

+5 supply, no signal, no load

+12 supply, no signal, no load

+5 supply, no signal, no load

5 supply, no signal, no load

Current consumption
(Single ended supply)

Current consumption
(Dual supply)

CC1

CC2

CC3

CC4

CC5

115

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

Video System

Nominal conditions single supply (Ta = 25°C, +5V/12V_V

A = +12V, 5V_GNDA = 0V,

+5V_VID = +5V, +5V_VOUT = +5V, +5V_DIG = +5V, GND_VID = 0V)

Sync tip clamp voltage at
input

Chrominance bias input
voltage

RGB dc restore input
voltage

Sync tip clamp voltage at
output

Chrominance bias output
voltage

RGB dc restore output
voltage

Gain (Vout1 to 6)

Gain (Vout1, 2, 3)

Gain (Vout7) Mixer off

Gain (Vout7) Mixer on

Bandwidth (Vout1 to 6)

Bandwidth (Vout7)
Mixer on No trap
components

Input dynamic range

Output dynamic range

Vclmp1

Cbias1

Cbias2

RGB1

Vclmp2

Cbias3

RGB2

GVv

RGB1

RGB2

RGB3

V3dB

DRVI

DRVO

5.5

6.5

7.5

8.5

5.5

1.4

2.8

2.4

2.35

2.4

0.3

1.8

0.6

6.0

7.0

8.0

9.0

6.0

5.75

6.5

7.5

8.5

9.5

6.5

MHz

Vp-p

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

Vin3, Vin8, Vin9, Vin10, Vin11, Vin12
inputs. (Vin3 set to CVBS mode) (Fig. 1)

Vin5, Vin7 inputs. Clamps set to
Chrominance bias mode. (Fig. 1)

Vin6, Vin13 inputs. (Fig. 1)

Vin1, Vin2, Vin3, Vin4, Vin5, Vin7 inputs.
(Vin3 & Vin5 set to RGB mode) (Fig. 1)

Vout4, Vout6 outputs (Fig. 1)

Vout3, Vout5 outputs (Fig. 1)

Vout1, Vout2, Vout3 outputs (Fig. 1)

f = 200kHz, 0.3Vp-p input ,
RGB Gain = 0dB (Fig. 2)

f = 200kHz, 0.3Vp-p input ,
RGB Gain = +1dB (Fig. 2)

f = 200kHz, 0.3Vp-p input ,
RGB Gain = +2dB (Fig. 2)

f = 200kHz, 0.3Vp-p input ,
RGB Gain = +3dB (Fig. 2)

f = 200kHz, 0.3Vp-p input (Fig. 2)

0.3Vp-p input, frequency where output
level is 3dB with 200kHz serving as 0dB
(Fig. 2)

200kHz input applied to any video (Fig. 2)

CXA2161R

Cross talk

S/N ratio

Non-linearity

Differential gain

Differential phase

Vctv

S/N

Lin

deg

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

f = 4.43MHz, 1Vp-p input (Fig. 2)

Ratio of 0.7Vp-p white video signal to
black line noise. Weighted using CCIR
567. HPF@5kHz, LPF@5MHz. (Fig. 2)

V1 = Pin voltage + 0.5V,
V2 = Pin voltage + 1V

At output, non-linearity = 1

100

(Fig. 2)

1.7Vp-p 5-step modulated staircase.
(Chrominance & Burst are 150mVp-p,
4.43MHz) (Fig. 2)

As above.

I
n

t

p

i
n

l
u

Audio System

Unless otherwise stated: input coupling capacitor 1µF; output coupling capacitor 10µF; load 10k

Nominal conditions single supply (Ta = 25°C, +5V/12V_V

A = +12V, 5V_GNDA = 0V, +5V_VID = +5V,

+5V_VOUT = +5V, +5V_DIG = +5V, GND_VID = 0V)

Nominal conditions dual supply (Ta = 25°C, +5V/12V_V

A = +5V, 5V_GNDA = 5V, +5V_VID = +5V,

+5V_VOUT = +5V, +5V_DIG = +5V, GND_VID = 0V)

Input/output pin voltage
(Single supply)

Input/output pin voltage
(Dual supply)

Output pin voltage when
disabled (Dual supply)

Input

Rin1 or Lin1

APIN1

APIN2

APIN3

0.5

2.5

5.5

8.5

0.5

3.5

6.5

9.5

0.5

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

No signal, no load (Fig. 3)

f = 1kHz, 0.5Vrms input. TV volume set to
0dB, RIN_1/LIN_1 amplifier = 6dB (Fig. 4)

f = 1kHz, 0.5Vrms input. TV volume set to
0dB, RIN_1/LIN_1 amplifier = 3dB (Fig. 4)

f = 1kHz, 0.5Vrms input. TV volume set to
0dB, RIN_1/LIN_1 amplifier = 0dB (Fig. 4)

f = 1kHz, 0.5Vrms input. TV volume set to
0dB, RIN_1/LIN_1 amplifier = +3dB (Fig. 4)

f = 1kHz, 1Vrms input. TV volume set to
0dB, RIN_1/LIN_1 amplifier = 6dB (Fig .4)

Output

TV or
Phono

VCR

Gain

CXA2161R

Rin1 + Lin1

Rin2, 3, 4 or
Lin2, 3, 4

Rin1 + Lin1

Rin2 + Lin2
Rin3 + Lin3
Rin4 + Lin4

Rin2, 3, 4
Lin2, 3, 4

Rin2 + Lin2
Rin3 + Lin3
Rin4 + Lin4

Rin3

Lin3

Audio frequency response

Frequency bandwidth

Distortion

Input dynamic range
Rin1, 2, 3, 4/Lin1, 2, 3, 4

Cross talk
(Channel separation)

DC offset

Input impedance
Rin1, 2, 3, 4/Lin1, 2, 3, 4

Output impedance

Phase difference

S/N ratio

A10

A11

A12

A13

A14

BWA1

THD

Vct

Voff

Zin1

Zout

Vpda

S/N

0.5

5.5

0.5

0.3

2.5

0.005

2.9

120

0.05

0.5

4.5

0.5

0.3

0.2

MHz

Vrms

deg

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

f = 1kHz, 0.5Vrms stereo input. TV volume
set to 0dB, RIN_1/LIN_1 amplifier = 6dB.
TV mono switch on. (Fig. 4)

f = 1kHz, 1Vrms stereo input. TV volume
set to 0dB, RIN_1/LIN_1 amplifier = 6dB.
(Note 1) (Fig. 4)

f = 1kHz, 1Vrms input, TV volume set to
0dB (Fig. 4)

f = 1kHz, 1Vrms stereo input. RIN_1/LIN_1
amplifier = 6dB. VCR mono switch on.
(Fig 4)

f = 1kHz, 1Vrms stereo input. TV volume
set to 0dB (Note 2) (Fig 4)

f = 1kHz, 1Vrms input (Fig 4)

f = 1kHz, 1Vrms stereo input. VCR mono
switch on. (Fig 4)

f = 1kHz, 1Vrms input, Lin3 has no signal
Audio overlay enabled with 11dB
attenuation at input RIN_3 (Fig 4)

f = 1kHz, 1Vrms input
Audio overlay enabled. (Fig 4)

0.3Vp-p input. Output/input gain at 30kHz
with 1kHz serving as 0dB (Fig 4)

0.3Vp-p input; frequency where output
level is 3dB with 1kHz serving as 0dB.
No load attached (Fig 4)

f = 1kHz, 0.5Vrms, unweighted response;
LPF@400Hz, HPF@80kHz (Fig 4)

f = 1kHz, RIN_1/LIN_1 input amplifier set
to 6dB. Dual supply mode used. (Fig 4)

f = 1kHz, 1Vrms input on one input,
measure on any other audio output (Fig 4)

Offset voltage between input and output

(excluding any external series resistor)

f = 1kHz, 1Vrms input to two channels.
Phase difference of stereo output measured

f = 1kHz, 1Vrms input (at 0dB volume).
HPF@20Hz, LPF@20kHz. (Fig 4)

TV
(mono mix)

MONO

TV or
Phono

VCR
(mono mix)

MONO

VCR

VCR
(mono mix)

RTV,
ROUT1,
Phono_R

LTV,
LOUT1,
Phono_L

Note 1) Mono switch set to mix of Rin1 & Lin1 inputs.

Note 2) Mono switch set to mix of RTV & LTV after volume control.

CXA2161R

Electronic Volume Control

Volume attenuation step

Mute
TV I/P MUTE or
VCR I/P MUTE

Audio limiter level

EVC

Amute

Alimit

1.6

6.5

2.4

Vp-p

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

f = 1kHz, 0.5Vrms input. Set by I

C (Fig 4)

f = 1kHz, 1Vrms input (Fig 4)

f = 1kHz, 2.5Vrms input. Measure TVp-p
output with limiter switched on. (Fig 4)

Digital Characteristics

C Interface

The I

C interface is compliant with Philips I

C Fast Mode specification (date April 1995). The interface is also

capable of interfacing to +3.3V or +5V logic levels.

Symbol

Item

Condition

Min.

Typ.

Max.

Unit

HYST

SCL

BUF

HD;STA

LOW

HIGH

SU;SDA

HD;DAT

SU;DAT

SU;STO

High level input voltage

Low level input voltage

Low level output voltage

Hysteresis of schmitt trigger input

Spike suppression

Fall time for SDA line

SCL clock frequency

Bus free time between a stop and
start

Hold time (repeated start condition)

Low period of SCL clock

High period of SCL clock

Setup time for a repeated start
condition

Data hold time

Data setup time

Setup time for stop condition

With SDA, 3mA current supplied

With SDA, 6mA current supplied

400pF bus load

C Bus line requirement

2.3

1.3

0.6

1.3

0.6

100

0.6

0.5

5.5

1.5

0.4

0.6

300

400

0.9

kHz

µs

BUF

HD;STA

LOW

HIGH

SU;DAT

SU;STA

SU;DAT

SU;STO

HD;STA

CXA2161R

Fig. 2. Video System

(Gain, Dynamic Range, Bandwidth, Differential Gain, Differential Phase, Crosstalk, Linearity,

Sync Detection)

Signal applied to Pins 1, 3, 4, 5, 6, 7, 50, 51, 52, 53, 54, 55, 56

Output signal measured from Pins 38, 39, 41, 43, 45, 46, 47

Notes) 1. All supplies de-coupled close to supply pins 14, 15, 24, 44, 48 with 10nF and 10µF capacitors.

2. For tests requiring video measuring equipment with 75

input impedance, an external video line

driver or buffer is used.

3. For video crosstalk tests all video inputs are terminated with 37.5

100nF

68k

+5V

100nF

+5V

+12V

+5V

SCL SDA

Measurement
Point

Input
Signal

22k

150

CXA2161R

Fig. 4. Audio System

(Single Supply -- Gain, Bandwidth, Signal to Noise, Electronic Volume, Zero Cross Detection, Limiter)

(Dual Supply -- Distortion, Dynamic Range, Crosstalk)

Signal applied to Pins 16, 17, 19, 20, 22, 23, 29, 42

Output signal measured from Pins 25, 26, 27, 28, 30, 31, 32

Notes) 1. Single audio supply configuration shown. Operate switches for dual supply configuration.

2. All supplies de-coupled close to supply pins 14, 15, 21, 24, 44, 48 with 10nF and 10µF capacitors.

100nF

+5V

+12V

+5V

+12V

+5V

SCL SDA

Measurement
Point

Input
Signal

10k

CXA2161R

C Control Data Format

Slave address A

DATA1

DATA2

DATA3

DATA4

DATAn

S: Start condition

A: Acknowledge

P: Stop condition

Address = 90H

C Data Structure (write mode)

Address

Data1

Data2

Data3

Data4

Data5

Data6

Data7

RIN1/LIN1

GAIN CONTROL

MONO

SWITCH

TV AUD

MUTE

TV INPUT

MUTE

TV VOL

BYPASS

OUTPUT

LIMIT

LOGIC
LEVEL

TV MONO SWITCH

VCR MONO SWITCH

FNC LEVEL

VCR VIDEO SWITCH

VCR INPUT

MUTE

SYNC SEL

VIN5

CLAMP

VIN7

CLAMP

VIN3

CLAMP

MIXER

CONTROL

ZCD

VOUT5

ENABLE

VOUT6

ENABLE

VOUT5

ENABLE

VOUT4

ENABLE

VOUT3

ENABLE

VOUT2

ENABLE

VOUT1

RGB GAIN

TV VIDEO SWITCH

FNC

DIR

FAST BLANK

TV AUDIO SELECT

VCR AUDIO SELECT

VOLUME CONTROL

0 = Write

TV AUD

MUTE

PHONO

BYPASS

OVERLAY

ENABLE

Address

Data

NOT

USED

NOT

USED

ZERO

CROSS

STATUS

P.O.D.

NOT

USED

SYNC

DETECT

FNC_VCR

1 = Read

C Data Structure (read mode)

Note) ZCD

= Zero Cross Detect

P.O.D. = Power on Detect

CXA2161R

Video I

C Write Structure

Video Switch 1: TV Output [Data 5 Bits 0, 1, 2]

Switch setting

Blue

Vout1

Green

Vout2

R/C

Vout3

CVBS/Y

Vout4

Comment

0 xxxxx000

1 xxxxx001

2 xxxxx010

3 xxxxx011

4 xxxxx100

5 xxxxx101

6 xxxxx110

7 xxxxx111

Encoder
Blue
VIN1

Bias

VCR Blue
VIN2

Bias

Encoder
Blue
VIN1

Bias

Encoder
Green
VIN3

Bias

VCR Green
VIN4

Bias

Encoder
Green
VIN3

Bias

Encoder
Red
VIN5

Encoder
Chrominance
VIN6

VCR
Chrominance/Red
VIN7

Bias

Encoder
Chrominance
VIN5

Encoder
Red
VIN5

Aux
Chrominance
VIN13

Bias

Encoder
CVBS
VIN8

Encoder
Luminance
VIN9

VCR CVBS/Y
VIN10

TV CVBS
VIN11

Encoder
Luminance
VIN3

Aux
CVBS
VIN12

Aux
CVBS/Y
VIN12

Bias

Digital encoder RGB or
CVBS

Digital encoder Y/C

VCR Y/C or RGB

Digital encoder Y/C

Encoder RGB and Aux CVBS

Aux Y/C or CVBS

Video mute (Power on default)

After power on all TV outputs are off (high impedance output) and muted.

TV RGB GAIN Control [Data 5 Bits 3, 4]

C setting RGB GAIN

Extra gain/dB

0 xxx00xxx

1 xxx01xxx

2 xxx10xxx

3 xxx11xxx

0 (Power on default)

CXA2161R

Video Switch 2: VCR Output [Data 5 Bits 5, 6, 7]

Switch setting

Chrominance

Vout5

CVBS/Y

Vout6

Comment

000xxxxx

001xxxxx

010xxxxx

011xxxxx

100xxxxx

101xxxxx

110xxxxx

111xxxxx

Encoder Chrominance
VIN5

Encoder Chrominance
VIN6

VCR Chrominance
VIN7

Bias

Encoder Chrominance
VIN5

Bias

Aux Chrominance
VIN13

Bias

Encoder CVBS/Y
VIN8

Encoder CVBS/Y
VIN9

VCR CVBS/Y
VIN10

TV CVBS
VIN11

Encoder Luminance
VIN3

Aux CVBS
VIN12

Aux CVBS/Y
VIN12

Bias

Digital encoder Y/C

Digital encoder Y/C or CVBS

VCR Y/C

TV CVBS

Encoder Y/C

Aux CVBS

Aux Y/C or CVBS

Video mute (Power on default)

After power on VCR outputs are off (high impedance) and muted.

MIXER CONTROL [Data 6 Bits 0, 1]

C setting

Mixer Output Vout7

xxxxxx00

xxxxxx01

xxxxxx10

xxxxxx11

No mix, Vout7 = Vout4 (CVBS)

Mix of Vout4 (Y) + Vout3 (C)

No mix, Vout7 = Vin8 (CVBS)

No mix, Vout7 = Vout4 (CVBS)

(Power on default)

Input Clamp Control VIN3 Clamp [Data 6 Bit 2]

xxxxx0xx = GREEN input on VIN3. DC restore clamp active. (Power on default.)

xxxxx1xx = CVBS input on VIN3. Sync tip clamp active.

Input Clamp Control VIN7 Clamp [Data 6 Bit 3]

xxxx0xxx = CHROMINANCE input on VIN7. Chrominance bias applied. (Power on default.)

xxxx1xxx = RED input on VIN7. DC restore clamp applied.

Input Clamp Control VIN5 Clamp [Data 6 Bit 4]

xxx0xxxx = RED input on VIN5. DC restore clamp applied. (Power on default.)

xxx1xxxx = CHROMINANCE input on VIN5. Chrominance bias applied.

CXA2161R

Sync Select Control for RGB DC Restore Circuits SYNC_SEL [Data 6 Bits 5, 6]

When the TV output is set to RGB + Y/CVBS mode. Then it is necessary to select the input that contains the

sync information for the RGB signal. This will normally be the digital encoder CVBS or VCR CVBS input.

C setting SYNC SEL

Input with sync

x00xxxxx

x01xxxxx

x10xxxxx

x11xxxxx

VIN8 (Power on default)

VIN9

VIN10

VIN12

Standby Mode Control [Data 7 Bits 0, 1, 2, 3, 4, 5]

The video outputs VOUT1, 2, 3, 4, 5, 6 can be individually turned off using data byte 7.

0 = Video output off. (Power on default)

1 = Video output on.

Note) When switched off, the video outputs are in a high impedance state. With a normal 150

load, the

outputs will be pulled to 0V.

Bi-directional Line Control on VCR Scart. Vout5_0V [Data 7 Bit 6]

x0xxxxxx = Vout5 active. Connected to input specified in VCR switch table.

x1xxxxxx = Vout5 set to 0V (Power on default)

6dB

Vout5
0V

VCR Scart

Pin 15
Red in
Chrominance In
Chrominance Out

Vout5
Chrominance out

Red in

Chrominance in

VIN_7

I = 6mA
(When set to 0V mode)

Fig 5. Bi-directional Line to VCR

As Pin 15 on the VCR scart can be bi-directional, either chrominance output or red/chrominance input, it is

necessary for output Vout5 to be individually controlled. When the VCR inputs red/chrominance signals, the

output Vout5 is set to 0V giving the required line impedance of 75

CXA2161R

C Audio Signal Control

Channel Select TV (Phono), VCR [Data 2, 3 Bits 1, 2]

Switch setting

RTV, Phono_R, ROUT1

LTV, Phono_L, LOUT1

xxxxx00x

xxxxx01x

xxxxx10x

xxxxx11x

Rin1

Rin2

Rin3

Rin4

Lin1

Lin2

Lin3

Lin4

After power on Rin4/Lin4 are selected.

Mono Switch TV [Data 2 Bits 3, 4, 5]

Switch setting

Connection to R channel
output

Connection to L channel
output

xx000xxx

xx001xxx

xx010xxx

xx011xxx

xx100xxx

xx101xxx

xx110xxx

xx111xxx

(R + L mix)

Comment

Normal

Mono mix

Channel swap

Right channel only

Left channel only

Normal

Normal (power on default)

Mono Switch VCR [Data 3 Bits 3, 4, 5]

Switch setting

Connection to R channel
output

Connection to L channel
output

xx000xxx

xx001xxx

xx010xxx

xx011xxx

xx100xxx

xx101xxx

xx110xxx

xx111xxx

(R + L mix)

Comment

Normal

Mono mix

Channel swap

Right channel only

Left channel only

Normal

All audio outputs disabled
(RTV, LTV, PHONO_R,
PHONO_L, MONO, ROUT1,
LOUT1)
(power on default)

CXA2161R

PHONO BYPASS [Data 2 Bit 0]

xxxxxxx0 = Phono outputs connected after volume control block. (Power on default)

xxxxxxx1 = Phono outputs connected before volume control block.

TV VOL BYPASS [Data 2 Bit 6]

x0xxxxxx = TV outputs connected after volume control block. (Power on default)

x1xxxxxx = TV outputs connected before volume control block.

MONO SWITCH [Data 2 Bit 7]

0xxxxxxx = Mono output connected to mix of TV R + L channels. (Power on default)

1xxxxxxx = Mono output connected to mix of RIN1 + LIN1 inputs.

VOLUME CONTROL [Data 1 Bits 1, 2, 3, 4, 5]

Setting

Volume gain

xx00000x

xx00001x

xx00010x

xx00011x

xx00100x

xx00101x

xx00110x

xx00111x

xx01000x

xx01001x

xx01010x

xx01011x

xx11111x

+6dB

+4dB

+2dB

0dB (power on default)

2dB

4dB

6dB

8dB

10dB

12dB

14dB

16dB

56dB

AUDIO RIN1/LIN1 GAIN [Data 1 Bits 6, 7]

Setting

Input attenuation

00xxxxxx

01xxxxxx

10xxxxxx

11xxxxxx

6dB (Power on default) (Note 1)

3dB

+0dB

+3dB

Note 1) The power on default is 6dB. As the output amplifiers have a nominal +6dB gain the overall input to

output gain is 0dB.

CXA2161R

OVERLAY ENABLE [Data3 Bit 0]

xxxxxxx0 = Overlay off (Power on default)

xxxxxxx1 = Overlay on: Rin3 and Lin3 are mixed and added to Rin1, Lin1 channels. Rin1 and Lin1 are attenuated

by 16dB before mixing with the tone.

TV Mute and Zero Cross Operation

When the zero cross is switched on (ZCD = 1), volume control changes are only implemented when the audio

signal passes though the zero cross point. Similarly, when a mute instruction is sent, the TV outputs are only

muted when the signal passes the zero cross point. This eliminates any click noise.

There are two TV audio mute control bits in the bus map. By having two bits it allows the TV outputs to be muted,

the TV channel changed and then un-muted all in one I

C write operation. The normal structure for a click free

audio channel change is as follows:

Data 1: Mute the TV audio output with the ZCD switched on.

Data 2: Change the TV audio source.

Data 3: Un-mute the TV audio output again with the ZCD switched on.

Operation of the Mute circuit

TV Aud Mute [Data 1 Bit 0]

[Data 3 Bit 7]

ZCD [Data 7 Bit 7]

TV, Phono and Mono output

Un-mute immediately

Un-mute on next zero cross

Mute immediately

Mute on next zero cross

After power on TV Audio Mute = 1 and ZCD are set to 1.

TV INPUT MUTE [Data 4 Bit 7]

0xxxxxxx = The input to the TV switch is not muted.

1xxxxxxx = The input to the TV switch is muted. (power on default)

VCR INPUT MUTE [Data 6 Bit 7]

0xxxxxxx = The input to the VCR switch is not muted.

1xxxxxxx = The input to the VCR switch is muted. (power on default)

OUTPUT LIMIT [Data 3 Bit 6]

This will limit the output level of the volume control block to 2.2Vrms maximum.

0xxxxxxx = The volume control outputs are not limited. (power on default)

1xxxxxxx = The volume control outputs are limited to 2.2Vrms.

CXA2161R

Fast Blanking Operation (Pin 16 on SCART), FBLK

The fast blanking signal instructs the TV to select either the external CVBS information or the external RGB

information. This is used to superimpose an on screen display (OSD) presentation (normally RGB) upon a

CVBS background. Fast blanking information has the same nominal phase as the RGB and CVBS signal, and

is defined as follows,

Fast blanking output at scart,

1. CVBS mode: Scart pin voltage = 0 to 0.4V

2. RGB mode: Scart pin voltage = 1 to 3.0V

The threshold voltage is approximately 0.75V at the scart input.

Fast Blanking I

C Control

In the CXA2161R, there are two fast blanking inputs, one associated with the digital encoder input (FBLK_IN1)

and another associated with the VCR RGB/CVBS input (FBLK_IN2). These can be selected and switched to the

output using an I

C instruction. In addition, the fast blank output pin can be set to a constant 0V or +3.5V by

means of the I

C control. Hence there are four possible states. These are set according to the following table.

FAST_BLANK [Data 4 Bits 0, 1]

C setting BLANK_LEVEL

Fast blank output pin voltage

xxxxxx00

xxxxxx01

xxxxxx10

xxxxxx11

0V (Power on default)

Same level as Fast Blank in 1 (0/+3.5V)

Same level as Fast Blank in 2 (0/+3.5V)

+3.5V

Fast Blank Output Interface

The Fast Blanking output pin is connected to the scart via a 75

resistor.

TV_FBLK

0V/+3.5V

Scart line 16

CXA2161R

Fig. 6. Fast Blanking Output Interface

CXA2161R

Function Switching Operation (Pin 8 on scart)

The function switch facility is designed to read the status of the SCART function Pin 8 from the VCR scart

connector and store this in the status register. Both, VCR and TV function lines can be set to outputs and

controlled by I

C. The TV function line has two modes, the first being control via I

C and secondly the follow

mode where the output will follow the same state as the VCR input.

Setting the Direction for the Function Lines

The input and control for the function lines is set by the FNC_DIR and FNC_FOLLOW bits.

FNC_FOLLOW

[Data 4 Bit 3]

FNC_DIR

[Data 4 Bit 2]

VCR Pin 8

TV Pin 8

Input

(Level stored in read register)

Output

Controlled by FNC_LEVEL

Input

(Level stored in read register)

Output

Controlled by FNC_LEVEL

Output

Holds previous level

Output

Follows same level as VCR input

Output

(Both set to same voltage controlled by FNC_LEVEL)

FNC_LEVEL [Data 4 Bits 4, 5]

These bits set the voltage at the (TV_FNC or VCR_FNC) outputs. The output is determined by the table above.

C control FNC_LEVEL

Voltage at output

xx00xxxx

xx01xxxx

xx10xxxx

xx11xxxx

< 2V

> 4.5V, < 7V

< 2V

> 9.5V

Mode

Internal TV

External scart input 16:9 mode

Internal TV

External scart input 4:3 mode

Note) After power on the output is internal TV mode ie. 0V at the pin.

FNC_VCR

+12V_DIG

Inside TV

< 2V

> 9.5V

> 4.5 < 7V

10k

Scart Pin 8

FNC_TV

10k

Fig. 7. TV Function Switch Output

CXA2161R

Logic and Interrupt Output

These open collector output pins can be used for an interrupt line to a microprocessor or as a general purpose

logic output.

Interrupt Output

The INTRUPT pin will become a current sink for approximately 2µs when the VCR input function line changes

from:

a) 0 to 6V, 6 to 0V b) 0 to 12V, 12 to 0V c) 6 to 12V, 12 to 6V

This pin will normally be connected to +5V through a 10k

resistor.

Logic Output

The logic output level can be changed using the logic output bit in the I

C register, LOGIC_LEVEL.

LOGIC LEVEL [Data 4 Bit 6]

x0xxxxxx = Current sink mode resulting in < 0.4V saturation voltage on logic pin. (Power on default)

x1xxxxxx = Open collector/high output impedance on logic pin.

Imax during current sink = 1mA

External resistors

10k

To Microprocessor

+3 to 14V

INTRUPT

LOGIC

10k

Fig. 8. INTRUPT and Logic Line Interface

CXA2161R

Read Mode Status Register

The following information can be read from the status register:

FNC VCR [Bits 0, 1]

The status register bits 0, 1 hold the level of the input function line

Input pin voltage

FNC_VCR

Data 8

0 to +2V (default)

+4.5 to +7V

+9.5 to +12V

(Internal)

(16:9 External)

(4:3 External)

SYNC DETECT [Bit 2]

Once a valid sync signal is detected on the input selected by SYNC_SELECT this bit is set to 1. The bit is

reset to 0 every time the SYNC_SELECT is changed. It is assumed that when a video input is in-active then

the input level will be 0V with minimum noise.

POD (Power on Detect) [Bit 4]

This bit is set to 1 after power on. It is then changed to 0 after the first I

C read. It is used to detect if the supply

has been corrupted. If the POR bit is read as 1 at any time then the IC should be re-initialized to the correct I

settings.

Zero Cross Status [Bit 5]

This audio function is used to determine if an input audio signal has passed the zero cross point. For dual

supply operation the zero cross point is 0V. For Single supply, the zero cross point is approximately 6V.

Input signal

Bias voltage

Zero cross point

Fig. 9. Zero Cross Point

0 = No zero cross detected

1 = Signal has passed through zero cross point.

SCART mode

CXA2161R

Description of Operation

Video Section

Inputs and Outputs

The video section comprises of thirteen (13) high impedance inputs switched through to seven (7) video

outputs. An internal +6dB amplifier is connected to each output. The amplifier is required to compensate for the

6dB attenuation that occurs at the 75

series output resistor. The outputs VOUT_1 to VOUT_6 are capable of

driving 150

loads. Output VOUT_7 is designed to interface to an RF Modulator but requires an external buffer

to drive a 75

load.

Composite/Luminance Inputs

The 4 composite (or luminance) inputs are ac coupled to the input pins. The signals are first sync tip clamped

to a set level. These clamps are permanently active, therefore these inputs should only be used for signals

with a sync.

2.4V

1Vp-p

= +5V

Input signal

0.3V

2Vp-p

= +5V

Output signal

Fig. 10. CVBS/Y Waveforms

RGB Inputs

The RGB inputs are ac coupled to the input pins. The inputs have a dc restore circuit, which is used to set the

blanking level to a fixed voltage. The clamps are controlled by the timing signal provided by the sync detect

circuit. It is necessary to select the correct luma or CVBS signal associated with the RGB inputs for the sync

select circuit. It is assumed that a sync signal will not be present on any of the RGB input signals. For inputs

that can be either red or chrominance then the clamp can be switched between the dc restore mode (for red

input) and average level bias (for chrominance). The RGB signals are fed through additional amplifiers that

are controlled via I

C. These allow the nominal 0.7Vp-p signal to be increased to 0.8Vp-p, 0.9Vp-p or 1Vp-p.

When the TV output is in Y/C mode, the RGB gain should be set to 0dB to prevent over amplification of the

chrominance output.

2.4V

0.7Vp-p

= +5V

Input signal

0.6V

1.4Vp-p

= +5V

Output signal

Fig. 11. RGB Waveforms

CXA2161R

Sync Detection Circuit

The clamp signals, used to restore the RGB level, are generated from the sync detect circuit. By using the

SYNC_SELECT control bits, the 4 different CVBS/Y inputs may be selected. Once selected, the clamped

signal is compared with a threshold voltage 65mV above the tip level. If the signal is less than this threshold it

is not passed to the next block. If greater than the threshold, it is passed to the discrimination circuit that

checks that the duty cycle is greater than 91%. The discrimination block also contains a time constant which,

when a sync is detected, holds the status line high for at least 11 video lines. If a valid sync signal is detected

the SYNC_DETECT bit in the read register is set to 1.

Comparator

Duty
Discrimination

LOGIC

I
G

/
Y

I
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/
Y

i
n

t

c

l
a

t
i
m

i
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SYNC_SELECT

Status register
SYNC_DETECT bit

Sync detect circuit

External R/C

SYNC_ID

GND_VID

+5V_VID

68k

0.1

Fig. 12. Sync Detection Circuit

Chrominance Inputs

The chrominance signals are ac coupled to the input pins. The inputs have a fixed dc bias that sets the

average level to approximately 3V for VIN_5 & VIN_7 and 2.35V for VIN_6 & VIN_13. For inputs that can also

be RED signals the input circuit can be switched to the dc restore mode.

Typical waveforms:

2.35 or 3V

0.7Vp-p

= +5V

Chrominance input pin voltage

1.8V

1.4Vp-p

= +5V

Chrominance output pin voltage

Fig. 13. Chrominance Waveforms

CXA2161R

Y/C Mixer

A Y/C mixer can be used for mixing Luminance and Chrominance signals for use with an external RF modulator

connected to VOUT_7. The Y/C mixer is controlled via the I

C data bus. The signal may be a mix of the TV Y/C

signals or simply the TV CVBS signal. It is also possible to select the CVBS signal from the digital encoder.

The circuit is shown in Fig 14. with a trap circuit used to give 6dB attenuation at 4.43MHz of the Luminance

signal. The output VOUT_7 cannot drive loads higher than 20k

resistive. If it is necessary to drive a 75

load with this output then an external emitter follower arrangement should be used.

6dB

0, 1, 2
or 3dB

VIN_8 = CVBS

R/C

CVBS/Y

VOUT_3

VOUT_4

VOUT_7

TRAP

Mixer
switch

For recommended values:
see application circuit

6dB

Fig. 14. Internal Y/C Mixer Circuit

Switching the Video Outputs Off

Each video output can be individually turned off using the I

C. When turned off, the output is set to a high

impedance state and hence the current consumption and power dissipation is reduced. After power on, all the

video outputs are set to the high impedance state.

CXA2161R

Audio Section

Inputs and Outputs

The audio system consists of 4 stereo inputs, 2 stereo outputs and separate mono and Phono outputs. The

stereo outputs can be connected to any one of the 4 stereo inputs. All audio inputs have a 6dB attenuator

except RIN_1 and LIN_1. Therefore, the net gain of the audio system from input to output is 0dB, as an

amplifier having +6dB of gain follows the internal switch. The stereo input RIN_1/LIN_1 has extra switchable

gain as this input is typically connected to an audio DAC with full scale of 1Vrms or less.

The output impedance of each audio amplifier is near zero, and may be directly coupled to the scart in the

case of a dual supply but must be ac coupled through a capacitor (typically 10µF) for the single supply case.

The outputs are capable of driving 600

loads. The user may add additional low pass filters to the outputs.

TV Output Switching

The TV audio section is composed of an audio switch followed by a volume control stage. The volume is

adjustable from +6dB to 56dB in 2dB steps. The volume control block includes a switchable limiter function to

prevent the output signals exceeding 2.2Vrms. When activated, the output signals from the volume control

block will be clamped to 2.2Vrms. A mono switch that allows the mixed R + L signal to be switched to the R

and L output channels follows the volume control section. The mono switch is also capable of routing the R

signal onto both R and L channel and similarly the L signal to the R and L output channels. This may be used if

the audio channels consist of two different languages. It is also capable of swapping the R and L channels.

TV Mute

This I

C mute function acts only on the TV, Phono and mono audio circuits. Audio mute will be implemented

after an audio zero cross detection to reduce click noise if ZCD = 1.

Zero Cross Detector (ZCD)

The zero cross detector reduces the effect of click noise when implementing a volume change or an audio

mute. The volume change or mute instruction sent by I

C will only be implemented when a minimal (ie zero

cross) signal amplitude is detected.

It can be seen from the I

C write format that the same mute bit occurs in DATA1 and DATA3. This allows the

software to action a mute, then after a delay (1/Audio_freq (min)) make any suitable changes to the audio

source and then un-mute the output buffer. Such a period provides ample time to allow any audio signals to

pass the zero cross point before the signal source is changed.

VCR Output Switching

The outputs ROUT1, LOUT1 have a fixed gain of 0dB from the input. If any attenuation is required then it is

possible to insert a series resistance on the input. Again, this output has a mono switching block that allows

the mixed R + L to be inserted on both output channels.

CXA2161R

Phono outputs

There is a stereo Phono output that carries the same signal as the TV output. This is typically used for

connection to a hi-fi. The signal level of the Phono outputs is normally the same as the TV outputs however it is

possible to bypass the volume section and set the Phono outputs to a fixed level. If any attenuation is required

then this can be done externally.

Mono Output

The mono output for the RF modulator has two settings. The first is a mix of the TV R + L channels. In this

case, the output signal will have the same volume control as the RTV/LTV outputs. The second setting is a mix

of the audio DAC inputs (RIN_1 + LIN_1). In this setting the output will always have fixed volume and if the

tone overlay is used, this will appear on the output.

Audio Overlay

The inputs RIN_3, LIN_3 may be used for a normal stereo audio input or alternatively to overlay an external

audio source onto the TV outputs. This may be a tone or voice. The R and L inputs are mixed and then added

equally to the RIN_1 and LIN_1 inputs. The I

C control bit Audio overlay enable is used to switch on this facility

and control the attenuator block on RIN_3 which is set to give an extra 5dB of attenuation when switched on. If

two tones are used then it is up to the user to switch them individually before the A/V switch. When the tone

overlay is activated, the signals RIN_1, LIN_1 are attenuated by approximately 16dB before mixing.

Audio Disable

All the audio outputs may be disabled using the Audio Output Disable function in the VCR mono switching

block [Data Byte 3 Bits 3, 4, 5 set to 111]. This disable mode is different from the normal mute as it can be

used for power reduction in stand by modes.

CXA2161R

Application in Set Top Box

VIN_1

VOUT_1

VOUT_2

R/C

VOUT_3

CVBS/Y

VOUT_4

TV_FBLK

TV_FNC

FAST BLANKING
FUNCTION SWITCH

VOUT_5

CVBS/Y

VOUT_6

CVBS

VOUT_7

VIN_3

VIN_5

VIN_8

CVBS

VIN_6

VIN_9
FBLK_IN1

FAST BLANKING

VIN_2

VIN_11

CVBS

VIN_12

CVBS/Y

VIN_13

VIN_4

VIN_7

R/C

VIN_10
FBLK_IN2
VCR_FNC

CVBS/Y

FAST BLANKING

FUNCTION SWITCH

Digtal
Encoder

VCR

RF
MOD.

AUX

Inputs

Outputs

CXA2161R
A/V switch

Fig. 21. Video Application with 6 Output Digital Encoder

VIN_1

VOUT_1

VOUT_2

R/C

VOUT_3

CVBS/Y

VOUT_4

TV_FBLK

TV_FNC

FAST BLANKING
FUNCTION SWITCH

VOUT_5

CVBS/Y

VOUT_6

CVBS

VOUT_7

VIN_3

G/CVBS

VIN_5

R/C

VIN_8
FBLK_IN1

CVBS/Y

FAST BLANKING

VIN_6
VIN_9

CVBS/Y

VIN_2

VIN_11

CVBS

VIN12

CVBS/Y

VIN13

VIN_4

VIN_7

R/C

VIN_10
FBLK_IN2
VCR_FNC

CVBS/Y

FAST BLANKING

FUNCTION SWITCH

Digtal
Encoder

VCR

Analogue
Sat.

VCR

RF
MOD.

AUX

Inputs

Outputs

CXA2161R
A/V switch

Fig. 22. Video Application with 4 Output Digital Encoder

CXA2161R

Application Circuit 1

Single Ended Supply

I
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_IN

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D/C

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VIN

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DIG

_IN

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VID

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DIG

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RIN

VIN

I
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Application circuits shown are typical

examples illustrating the operation of

the devices. Sony cannot assume

responsibility for any problems arising

out of the use of these circuits or for

any infringement of third party patent

and other right due to same.

CXA2161R

Application Circuit 2

Dual Supply

I
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I
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RIN

VIN

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Application circuits shown are typical

examples illustrating the operation of

the devices. Sony cannot assume

responsibility for any problems arising

out of the use of these circuits or for

any infringement of third party patent

and other right due to same.

CXA2161R

Notes on operation

1) Supply de-coupling capacitors, 10nF and 10µF in parallel should be inserted as close as possible to the

supply Pins 14, 15, 24 and 44. When using the dual supply configuration apply the capacitors to Pin 21 in

addition to the listed supply pins.

2) For best results with dual supply configuration, two +5V supplies should be used, audio (Pin 24) and

video/digital (Pins 14, 44 and 49).

3) To minimize crosstalk, attention should be given to the routing of audio and video to the IC inputs. PCB track

lengths should be kept as short as possible and preferably, audio placed on a separate layer to the video.

4) Attention should be given to the electrolytic capacitors on the output pins. In single supply configuration the

audio pin dc bias voltage will be approximately 6.0V, therefore the positive terminal of the capacitors should

be orientated towards the device pin.

5) To minimise stray capacitance the 75

series resistor on video outputs VOUT_1 to VOUT_6 should be

mounted as close as possible to the device Pins 47, 46, 45, 44, 41 and 39.

6) When driving video loads with impedance of 75

, video output VOUT_7 (Pin 38) must be connected to the

load via a buffer or line driver. This buffer should be located close to the output (Pin 38).

7) In dual supply mode, series protection resistors may be added on Audio outputs which are connected Scart

connectors.

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