CXA2543R

Decoder/Driver/Timing Generator for Color LCD Panels

Description

The CXA2543R is an IC designed exclusively to

drive the color LCD panel DCX501BK and LCX018AK.

This IC greatly reduces the number of circuits and

parts required to drive LCD panels by incorporating

RGB decoder functions for video signals, driver

functions, and a timing generator for driving panels

onto a single chip.

This chip has a built-in serial interface circuit and

electronic attenuators which allow various mode

settings and adjustments to be performed through

direct control from an external microcomputer, etc.

Features

· Color LCD panel DCX501BK and LCX018AK driver

· Supports NTSC and PAL signals

· Supports 16:9 wide display

· Supports composite inputs, Y/C inputs and Y/color

difference inputs

· Serial interface circuit

· Electronic attenuators (D/A converter)

· BPF, trap and delay line

· Sharpness function

· 2-point

correction circuit

· R, G, B signal delay time adjustment circuit

· Polarity inversion circuit (line inverted mode)

· Supports external RGB input

· Supports AC drive for LCD panel during no signal

Applications

· Compact LCD monitors

· LCD viewfinders

· Compact liquid crystal projectors, etc.

Structure

Bipolar CMOS IC

Absolute Maximum Ratings (Ta = 25°C)

· Supply voltage

1 GND1

2 GND2

3 GND3

1 V

4.5

1 V

4.5

· Analog input pin voltage VINA

0.3 to V

· Digital input pin voltage VIND 0.3 to V

1 + 0.3 V

· Operating temperature Topr

15 to +75

°C

· Storage temperature

Tstg

40 to +125

°C

· Allowable power dissipation

(Ta

75°C) 350 mW

Operating conditions

Supply voltage V

1 GND1

4.25 to 5.25

2 GND2

11.0 to 13.5

3 GND3

11.0 to 13.5

1 V

2.7 to 3.6

1 V

2.7 to 3.6

With substrate Size: 30

1.6mm

Material: Glass fabric base epoxy

E98403-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

64 pin LQFP (Plastic)

CXA2543R

Block Diagram

POL SW

SUB-
BRIGHT

GAMMA

DEMOD

LPF

CONTRAST

EXT SW

BRIGHT

S/H

INT/EXT

VXO

HUE

KILLER

FILT ADJ

COLOR CONT

BPF

PIC CONT

DL1

TRAP

CLAMP

ACC AMP

H. FILTER

Buf

REG.

R G B

+12V

GND1

+4.5V

Buf

PAL
SW

EXT COLOR
& BALANCE

HUE

COLOR

CONTRAST

R-BRT

B-BRT

-1

-2

SERIAL
BUS I/F

VGATE

VTST

VPAL

VWIN

WIDE

PALSW

D/A

HCNT
H-PULSE

HAFC
PLL-COUNTER
& DECODER

HGATE
H-SKEW DET

CLP
BGP
SBLK

V SEP

+3V

MATRIX

Buf

POL SW

PSIG-
BRIGHT

PSIG-BRT

APC

ACC DET

GND3

GND2

SYNC SEP

FRP

COLOR

PAL ID

CLAMP

XEN

VCK1

VCK2

VST

XVST

FLD IN

PCG

XPCG

HCK1

HCK2

HST

XHST

.
S

I
N

.
F

I
L

I
N

SIG. CENTER

B-Y IN

R-Y IN

BLK LIM

APC

VXO OUT

VXO IN

V REG

C IN

TEST3

Y IN

PIC

PWRST

F0 ADJ

C OUT

I
G

BRIGHT

CXA2543R

Pin Description

No.

TRAP

GND1

SYNC IN

H.FIL OUT

S.SEP IN

EXT R

EXT G

EXT B

VD IN

TEST1

TEST2

RPD

CKI

CKO

XHST

HST

HCK2

HCK1

XPCG

PCG

FLD IN

XVST

VST

VCK2

VCK1

XEN

Symbol

External trap connection

Analog (4.5V) GND

Video input for sync separation

Video output for sync input

Sync separation circuit input

External digital input R

External digital input G

External digital input B

External vertical sync input

Test (Leave this pin open.)

Phase comparator output

Digital (3V) GND for oscillation cell

Oscillation cell input

Oscillation cell output

Digital 3V power supply

XH start pulse output (HST reversed polarity)

H start pulse output

H clock pulse 2 output

H clock pulse 1 output

XPCG pulse output (PCG reversed polarity)

PCG pulse output

HD pulse output

Field identification input

XV start pulse output (VST reversed polarity)

V start pulse output

V clock pulse 2 output

V clock pulse 1 output

XEN pulse output (EN reversed polarity)

EN pulse output

Digital (3V) GND

VD pulse output

I/O

Description

Input pin
for open
status

(H: Pull up)

CXA2543R

SCLK

DATA

LOAD

RGT

FB PSIG

GND3

PSIG

B OUT

FB B

GND2

G OUT

FB G

R OUT

FB R

SIG.CENTER

B-Y IN

R-Y IN

C OUT

BLK LIM

APC

VXO OUT

VXO IN

V REG

C IN

TEST3

Y IN

PIC

F0 ADJ

PWRST

Serial interface clock input

Serial interface data input

Serial interface load input

Switches between Normal scan (H) and Reverse scan (L)

PSIG signal DC voltage feedback circuit capacitor connection

Analog (12V) GND for PSIG

PSIG output

Analog 12V power supply for PSIG

B signal output

B signal DC voltage feedback circuit capacitor connection

Analog (12V) GND

G signal output

G signal DC voltage feedback circuit capacitor connection

R signal output

R signal DC voltage feedback circuit capacitor connection

Analog 12V power supply

Analog 4.5V power supply

R, G, B and PSIG output DC voltage adjustment

B-Y demodulator input (or B-Y color difference signal input)

R-Y demodulator input (or R-Y color difference signal input)

Chroma signal output

Black peak limiter level adjustment

APC detective filter connection

VXO output

VXO input

Constant voltage capacitor connection

Chroma signal input

Test (Connect to GND.)

Y signal input

Y signal frequency response adjustment

Internal filter adjusting resistor connection

System reset

(H: Pull up)

No.

Symbol

I/O

Description

Input pin
for open
status

CXA2543R

EXT-R

EXT-G

EXT-B

FB B

FB PSIG

FB G

FB GR

B OUT

G OUT

R OUT

External digital signal inputs.
There are two threshold
values: Vth1 (= 1.0V) and
Vth2 (= 2.0V). When one of
the RGB signals exceeds
Vth1, all of the RGB outputs
go to black level; when an
input exceeds Vth2, only the
corresponding output goes to
white level.

300

GND1

30µA

50k 2.7V

Smoothing capacitor
connection for the feedback
circuit of R, G, B and PSIG
output DC level control.
Use a low-leakage capacitor
because of high impedance.

GND2

RGB signal outputs.

GND2

40µA

2.0V

GND3

Analog (12V) GND for the PSIG circuit.

PSIG signal outputs.

GND3

PSIG

12V

12V power supply for the PSIG
circuit.

GND2

Analog (12V) GND.

No.

Symbol

Pin voltage

Equivalent circuit

Description

CXA2543R

B-Y IN

R-Y IN

Color difference demodulation
circuit inputs.
Color difference signal is input
when using Y/color difference
input. At this time, the
standard signal input level is
0.3Vp-p and the clamp level is
approximately 2.8V. Pin 53
signal is input in other modes
(except D-PAL

). At this time,

the DC level is approximately
1.6V.

500

GND1

10k

30µA

50µA

500

SIG.
CENTER

6.0V

RGB output DC voltage
control.
When used with a V

2 and

3 of 12V or more, apply

6V from an external source.

GND2

150k

300

150k

C OUT

1.6V

Color adjusted chroma signal
output.
The burst level is 180mVp-p
(typ.).
(540mVp-p during D-PAL.)
Leave this pin open when
using Y/color difference input.

GND1

350µA

BLK LIM

Sets the RGB output
amplitude (black-black) clip
level and the blanking black
level for during wide display.

GND1

50k

D-PAL is a demodulation method that uses an external delay line during demodulation;

S-PAL is a demodulation method that internally processes chroma demodulation.

12V

4.5V

12V power supply.

4.5V power supply.

No.

Symbol

Pin voltage

Equivalent circuit

Description

CXA2543R

Setting Conditions for Measuring Electrical Characteristics

Use the electrical characteristics measurement circuit on page 30 when measuring electrical characteristics.

Also, the TG (timing generator) block must be initialized by performing Settings 1 and 2 below.

Setting 1. System reset

After turning on the power, set SW64 to ON and start up V64 from GND in order to activate the TG block

system reset. (See Fig. 1-1.)

The serial bus will be set to default values.

Setting 2. Horizontal AFC adjustment

Input SIG5 (VL = 0mV) to (A) and adjust V14 so that WL and WH of the TP12 output waveform are the

same. (See Fig. 1-2.)

Note) When measuring a band of 2MHz or more for Y signal frequency response or sharpness response

among the items being measured, the measurement must be made with sample-and-hold timing (serial

bus) set to through (sample-and- hold not performed).

V64 (PWRST)

> 10µs

SIG5

TP12

WL = WH

Fig. 1-1. System reset

Fig. 1-2. Horizontal AFC adjustment

CXA2543R

Electrical Characteristics -- DC Characteristics

Unless otherwise specified, Settings 1 and 2 and the following setting conditions are required.

1 = 4.5V, V

2 = 12.0V, V

3 = 12.0V, GND1 = GND2 = GND3 = 0V, V

1 = 3.0V, V

1 = V

2 = 0V, Ta = 25°C

SW54, SW62, SW64 = ON

SW6, SW7, SW8, SW59 = A

SW51, SW52 = B

V54 = 0V, V62 = 2.2V

Set the serial bus registers to the "Serial Bus Register Initial Settings". Unspecified the serial bus registers

should be set to default settings.

Input SIG4 to (A) and SIG2 (0dB) to (B).
Measure the I

1 current value.

COMP input mode

Input SIG4 to (A) and SIG2 (0dB) to (B).
Measure the I

1 current value.

Y/C input mode

Input SIG4 to (A), (D) and (E).
Measure the I

1 current value.

SW51, SW52 = A, SW59 = B

Y/color difference input mode

Input SIG4 to (A) and SIG2 (0dB) to (B).
Measure the I

2 current value.

PSIG load capacity CLP = 0pF

Input SIG4 to (A) and SIG2 (0dB) to (B).
Adjust PSIG-BRT of the serial bus and measure the
I

2 current value when TP39 output is set to 5Vp-p.

PSIG load capacity CLP = 10000pF

Input SIG4 to (A) and SIG2 (0dB) to (B).
Measure the I

current value.

DCX501 and LCX018 (4:3) mode

Input SIG4 to (A) and SIG2 (0dB) to (B).
Measure the I

current value.

LCX018 (16:9) mode

7.5

8.3

10.5

12.5

Item

Power supply characteristics

Current
consumption
V

2, 3

Current
consumption V

Symbol

Conditions

Min.

Typ.

Max.

Unit

CXA2543R

Digital block input pin

0.3V

VIL

Digital block I/O characteristics

Low level input voltage

High level input voltage

Input current

CKI pin low input current

CKI pin high input current

High level output voltage
Output pins except
CKO and RPD

Low level output voltage
Output pins except
CKO and RPD

High level output voltage
CKO pin

Low level output voltage
CKO pin

High level output voltage
RPD pin

Low level output voltage
RPD pin

Output off leak current
RPD pin

Digital block input pin

0.7V

VIH

Input pin with pull-up resistor

VIN = V

145

µA

II1

VIN = V

µA

II2

VIN = V

µA

II3

IOH = 1mA

2.8

VOH1

IOL = 1mA

0.3

VOL1

IOH = 3mA

0.5V

VOH2

IOL = 3mA

0.5V

VOL2

Digital block input pins: SCLK, DATA, LOAD, VDIN, RGT, FLDIN, CKI

Input pins with pull-up resistors: SCLK, DATA, LOAD, VDIN, RGT, FLDIN

Output pins except CKO and RPD: XHST, HST, HCK1, HCK2, XPCG, PCG, HD, XVST, VST, VCK1, VCK2,

XEN, EN, VD

IOH = 0.5mA

1.2

VOH3

IOL = 0.7mA

1.0

VOL3

High impedance status
VOUT = V

or VOUT = V

µA

IOFF

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

CXA2543R

Electrical Characteristics -- AC Characteristics

Unless otherwise specified, Settings 1 and 2 and the following setting conditions are required.
V

1 = 4.5V, V

2 = 12.0V, V

3 = 12.0V, GND1 = GND2 = GND3 = 0V, V

1 = 3.0V, V

1 = V

2 = 0V, Ta = 25°C

SW54, SW62, SW64 = ON
SW6, SW7, SW8 = A
SW51, SW52, SW59 = B
V54 = 0V, V62 = 2.2V
Set the serial bus registers to the "Serial Bus Register Initial Values". Unspecified serial bus registers should
be set to default settings.
Unless otherwise specified, measure the non-inverted outputs for TP41, TP44 and TP46.

Input SIG2 (0dB) to (A). Using a spectrum
analyzer, measure the input and the 3.58MHz or
4.43MHz component of TP44, and obtain
CRLEKY = 150mV

CLK/20

using their

difference

CLK.

5.0

2.5

3.0

5.0

MHz

GCNTTP

GCNTMN

FCYYC

FCYCMN

FCYCMP

Y signal block

Video maximum
gain

Contrast
characteristics TYP

Contrast
characteristics MIN

Y signal frequency
response 1

Y signal frequency
response 2

GSHP1X

FCL

GSHP1N

GSHP2X

GSHP2N

Picture quality
adjustment
variable amount 1
(Y/C input)

Picture quality
adjustment
variable amount 2
(composite input)

CRLEKY

Carrier leak
(residual carrier)

Y/C input

Composite input
(NTSC)

Composite input
(PAL)

TDYYC

TDYCMN

TDYCMP

250

570

350

670

450

770

Y signal I/O delay
time

Y/C input

Composite input
(NTSC)

Composite input
(PAL)

Input SIG9 (VL = 150mV) to
(A). Measure the delay time
from the 2T pulse peak of
the input signal to the peak
of the non-inverted output at
TP44.

Input SIG4 to (A) and measure the ratio between the output
amplitude (white-black) and input amplitude at TP44.

Assume the output amplitude at
TP44 when SIG7 (0dB, no burst,
100kHz) is input to (A) as 0dB.
Vary the frequency of the input
signal to obtain the frequency with
an output amplitude of 3dB.
V62 = 1.5V

Assume the output amplitude at TP44 when SIG7
(0dB, no burst, 100kHz) is input to (A) as 0dB.
Vary the frequency of the input signal to obtain the
frequency with an output amplitude of 3dB.
V62 = 1.5V, Load 500pF

Assume the output amplitude at TP44 when SIG7
(100kHz) is input to (A) as 0dB. Set SIG7 to 2.5MHz
and measure GSHP1X and GSHP1N as the
amounts by which the output amplitude at TP44
changes when V62 = 4V and 0V, respectively.

Assume the output amplitude at TP44 when SIG7
(100kHz) is input to (A) as 0dB. Set SIG7 to 2.0MHz
and measure GSHP2X and GSHP2N as the
amounts by which the output amplitude at TP44
changes when V62 = 4V and 0V, respectively.

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

CXA2543R

Input SIG5 (VL = 150mV) to (A) and
SIG2 (level variable, 3.58MHz
burst/chroma phase = 180°, or 4.43MHz
burst/chroma phase = ±135°) to (B), and
measure the output amplitude at TP44.
Gradually reduce the SIG3 amplitude
level and measure the level at which the
killer operation is activated.
SW59 = A

±500

ACC1

ACC2

FAPCN

FAPCP

GCOLMX

GCOLMN

ACKN

ACKP

Chroma signal block

ACC amplitude
characteristics 1

ACC amplitude
characteristics 2

APC pull-in range

Color adjustment
characteristics
MAX

Color adjustment
characteristics
MIN

deg

HUEMX

HUEMN

HUE adjustment
range
MAX

HUE adjustment
range
MIN

Killer operation
input level

NTSC

PAL

NTSC

PAL

NTSC

PAL

NTSC

PAL

Input SIG5 (VL = 150mV) to (A) and
SIG2 (0dB/+6dB/20dB, 3.58MHz
burst/chroma phase = 180°, or 4.43MHz
burst/chroma phase = ±135°) to (B).
Measure the output amplitude at TP53,
assuming the output corresponding to
0dB, +6dB and 20dB as V0, V1 and V2,
respectively.
ACC1 = 20 log (V1/V0)
ACC2 = 20 log (V2/V0)
SW59 = A

Input SIG5 (VL = 150mV) to (A) and
SIG2 (0dB, 3.58MHz burst/chroma
phase = 180°, or 4.43MHz burst/chroma
phase = ±135°) to (B). Changing the
SIG2 burst frequency, measure the
frequency f1 at which the TP44 output
appears (the killer mode is canceled).
NTSC: FAPCN = f1 3579545Hz
PAL: FAPCP = f1 4433619Hz
SW59 = A

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,
3.58MHz burst/chroma phase = 180°) to (B).
Assume the chroma output amplitude when serial
bus register COLOR = 80H, 0FFH and 0H as V0,
V1 and V2, respectively.
GCOLMX = 20 log (V1/V0)
GCOLMN = 20 log (V2/V0)
SW59 = A

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,
burst/chroma phase variable) to (B). Assume the
phase at which the output amplitude at TP44
reaches a minimum when serial bus register HUE
= 80H, 0FFH and 0H as

1 and

respectively.
HUEMX =

HUEMN =

SW59 = A

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

CXA2543R

Demodulation
output amplitude
ratio (NTSC)

Demodulation
output amplitude
ratio (PAL)

Demodulation
output phase
difference (PAL)

Color difference
balance

RBN

VGBN

VRBN

GBN

VRBP

VGBP

0.25

0.53

230

109

0.32

0.63

242

119

0.39

0.73

254

deg

0.33

0.65

0.40

0.75

0.47

0.85

deg

RBP

GBP

232

244

100

256

deg

GEXCMX

GEXCMN

Color difference
input color
adjustment
characteristics
MAX

Color difference
input color
adjustment
characteristics
MIN

Color difference
input balance
adjustment R

Color difference
input balance
adjustment B

VEXCBL

0.8

1.0

1.2

GEXRMX

GEXRMN

GEXBMX

GEXBMN

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,
3.58MHz) to (B) and change the chroma phase.
Assume the maximum amplitude at TP41 as VB,
the maximum amplitude at TP44 as VG, and the
maximum amplitude at TP46 as VR.
VRBN = VR/VB, VGBN = VG/VB
SW59 = A

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,
3.58MHz) to (B) and change the chroma phase.
Assume the phase at which the amplitude at
TP41, TP44 and TP46 reaches a maximum as

G and

R, respectively.

RBN =

GBN =

SW59 = A

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,
4.43MHz) to (B) and change the chroma phase.
Assume the maximum amplitude at TP41 as VB,
the maximum amplitude at TP44 as VG, and the
maximum amplitude at TP46 as VR.
VRBP = VR/VB, VGBP = VG/VB
SW59 = A

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,
4.43MHz) to (B) and change the chroma phase.
Assume the phase at which the amplitude at
TP41, TP44 and TP46 reaches a maximum as

G and

R, respectively.

RBP =

GBP =

SW59 = A

Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB,
100kHz, no burst) to (D). Assume the output
amplitude at TP41 (100kHz) when serial bus
register COLOR = 80H as VC0, when COLOR =
0H as VC2, and when SIG1 is set to -10dB and
COLOR = 0FFH as VC1.
GEXCMX = 20 log (VC1/VC0) + 10
GEXCMN = 20 log (VC2/VC0)
SW51, SW52 = A

Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB,
100kHz, no burst) to (D) and (E). Assume the
output amplitude at TP41 (100kHz) as VB and
the output amplitude at TP46 (100kHz) as VR.
VEXCBL = VR/VB
SW51, SW52 = A

Input SIG5 (VL = 150mV) to (A) and SIG1 (6dB,
100kHz, no burst) to (D) and (E). Assume the
output amplitude at TP46 (100kHz) and TP41
(100kHz) when serial bus register HUE = 80H as
VR0 and VB0, respectively, when HUE = 0FFH
as VR1 and VB1, respectively, and when HUE =
0H as VR2 and VB2, respectively.
GEXRMX = 20 log (VR1/VR0)
GEXRMN = 20 log (VR2/VR0)
GEXBMX = 20 log (VB1/VB0)
GEXBMN = 20 log (VB2/VB0)
SW51, SW52 = A

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

Demodulation
output phase
difference (NTSC)

CXA2543R

VEXGBN

0.22

0.25

0.28

0.47

0.53

0.58

VEXGRN

5.85

9.0

6.00

6.15

100

5.2

4.0

Vp-p

G-Y matrix
characteristics
(NTSC)

Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB,
100kHz, no burst) to (D). Assume the output
amplitude at TP41 (100kHz) as VEXB and the
output amplitude at TP44 (100kHz) as VEXBG.
VEXGBN = VEXBG/VEXB
SW51, SW52 = A

Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB,
100kHz, no burst) to (E). Assume the output
amplitude at TP46 (100kHz) as VEXR and the
output amplitude at TP44 (100kHz) as VEXRG.
VEXGRN = VEXRG/VEXR
SW51, SW52 = A

VEXGBP

0.16

0.19

0.22

0.48

0.53

0.58

VEXGRP

G-Y matrix
characteristics
(PAL)

Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB,
100kHz, no burst) to (D). Assume the output
amplitude at TP41 (100kHz) as VEXB and the
output amplitude at TP44 (100kHz) as VEXBG.
VEXGBP = VEXBG/VEXB
SW51, SW52 = A

Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB,
100kHz, no burst) to (E). Assume the output
amplitude at TP46 (100kHz) as VEXR and the
output amplitude at TP44 (100kHz) as VEXRG.
VEXGRP = VEXRG/VEXR
SW51, SW52 = A

VOUT

VLIMMX

VLIMMN

BRTMX

BRTMN

Input SIG5 (VL = 0mV) to (A). Adjust serial bus
register BRIGHT so that the output (black-black)
at TP44 is 9Vp-p and measure the DC voltage at
TP39, TP41, TP44 and TP46.

Input SIG5 (VL = 0mV) to (A). Adjust serial bus
register BRIGHT so that the output (black-black) at
TP44 is 9Vp-p, measure the DC voltage at TP39,
TP41, TP44 and TP46, and obtain the maximum
difference between each of these values.

Input SIG3 to (A). Vary V54 and measure the maximum
value VLIMMX and minimum value VLIMMN of the
voltage range (black-black) over which the black limiter
operates for the TP39, TP41, TP44 and TP46 outputs.
Assume the value whenV54 = 0V as VLIMMX, and
when V54 = 4.5V as VLIMMN.

Input SIG5 (VL = 0mV) to (A) and measure the
output (black-black) at TP41, TP44 and TP46
when serial bus register BRIGHT = 0H.

Input SIG5 (VL = 0mV) to (A) and measure the
output (black-black) at TP41, TP44 and TP46
when serial bus register BRIGHT = 0FFH.

RGB signal output block

RGB signal and
PSIG output DC
voltage

RGB signal and
PSIG output DC
voltage difference

RGB and PSIG
output limiter
operation voltage

Amount of change
in brightness

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

CXA2543R

1.5

Vp-p

9.0

Vp-p

±1.5

±2.0

PSIGMX

PSIGMN

Input SIG5 (VL = 0mV) to (A) and measure the
output (black-black) at TP39 when serial bus
register PSIG-BRT = 0H.

Input SIG5 (VL = 0mV) to (A) and measure the
output (black-black) at TP39 when serial bus
register PSIG-BRT = 0FFH.

Amount of change
in PSIG

SBBRT

Input SIG5 (VL = 0mV) to (A) and measure the difference
between the outputs (black-black) at TP41 and TP46 and
the output (black-black) at TP44 when serial bus registers
R-BRT = B-BRT = 0H and when R-BRT = B-BRT = 0FFH.

Amount of change
in sub-brightness

0.5

GRGB

Input SIG4 to (A) and obtain the level difference between
the maximum and minimum non-inverted output
amplitudes (white-black) at TP41, TP44 and TP46.

Difference in gain
between RGB
output signals

0.5

GINV

Input SIG4 to (A) and obtain the level difference between
the non-inverted output amplitudes (white-black) and the
inverted output amplitudes at TP41, TP44 and TP46.

Difference in RGB
output inverted/non-
inverted gain

300

VBL

Input SIG4 to (A) and obtain the level difference between
the maximum and minimum black levels of both the inverted
and non-inverted outputs at TP41, TP44 and TP46.

Input SIG8 to (A). Adjust the non-inverted output
black level at TP44 to 6.0 - 4.5V with serial bus
register BRIGHT and the non-inverted output
amplitude (white-black) at TP44 to 3.5V with
serial bus register CONTRAST. Measure VG1,
VG2 and VG3.
G

1 = 20 log (VG1/0.0357)

2 = 20 log (VG2/0.0357)

3 = 20 log (VG3/0.0357)

(See Fig. 5 for definitions of VG1, VG2 and VG3.)

Input SIG8 to (A) and adjust serial bus register
BRIGHT so that the output at TP44 is 9Vp-p
(black-black). Read the point where the gain of
the non-inverted output at TP44 changes when
serial bus register

1 = 0H and 0FFH from the

input signal IRE level.
V

1MN when

1 = 0H, and V

1MX when

1 =

0FFH.

2 = 0H and 0FFH from the

input signal IRE level.
V

2MN when

2 = 0H, and V

2MX when

2 =

0FFH.

Difference in black
level potential between
RGB output signals

gain

1 adjustment

variable range

2 adjustment

variable range

23.0

26.0

29.0

12.0

15.0

18.0

21.0

25.0

1MN

1MX

2MN

2MX

IRE

100

IRE

100

IRE

Input SIG4 to (A) and adjust serial bus register
PSIG-BRT so that the output at TP39 is 9Vp-p
(black-black). Measure the time it takes to change
to an amplitude of 9Vp-p.
tPSIGH: rising edge, tPSIGL: falling edge

PSIG transition
time

PSIGH

PSIGL

1.5

3.0

µs

1.5

3.0

µs

Input SIG5 (VL = 350mV) to (A) and measure the voltage (white-
white) at which the white limiter activates for inverted output and
non-inverted output at TP41, TP44 and TP46, respectively.

RGB output white
limiter operation
voltage

VWLIM

1.3

1.5

1.7

Input SIG5 (VL = 0mV) to (A) and adjust V54 so that
the output at TP44 is 9Vp-p (black-black). Measure the
DC voltage at TP41, TP44 and TP46 and obtain the
difference versus the RGB output voltage VOUT.

Black limiter DC
voltage difference

VBLIM

100

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

CXA2543R

TDSYL

TDSYH

HPLLN

HPLLP

430

630

830

4.7

5.0

5.3

µs

±500

NTSC

PAL

100

ATBPF

ATRAPN

ATRAPP

DEMLPF

WSSEP

VSSEP

0.8

1.0

1.3

MHz

2.0

µs

NTSC 1.5MHz

PAL

2.0MHz

NTSC 5.5MHz

PAL

6.8MHz

NTSC

PAL

Amount of BPF
attenuation

Amount of TRAP
attenuation

R-Y, B-Y and LPF
characteristics

Input sync signal
width sensitivity

Sync separation
input sensitivity

Sync separation
output delay time

Horizontal pull-in
range

Sync separation, TG block

Filter characteristics

Assume the chroma amplitude at TP53
when SIG5 (VL = 0mV) is input to (A)
and SIG1 (0dB at input center frequency
(3.58Hz or 4.43Hz)) is input to (B) as
0dB. Obtain the amount by which the
output at TP53 is attenuated when the
frequencies noted on the right are input.
SW59 = A

Input SIG2 (0dB, 3.58Hz and 4.43Hz) to (A)
and measure the output at TP44. Assume
the amplitude at TP44 during Y/C input
mode as 0dB, and obtain the amount of
attenuation during COMP input mode.

Assume the amplitude of the 100kHz component of the output at
TP44 when SIG5 (VL = 150mV) is input to (A) and SIG1 (0dB,
3.58Hz + 100kHz) is input to (B) as 0dB. Obtain the frequency
which attenuates the beat component of the output by 3dB when
the SIG1 frequency is increased with respect to 3.58MHz.
SW59 = A

Input SIG5 (VL = 0mV, VS = 143mV, WS variable) to (A) and
confirm that it is synchronized with the HD output at TP23.
Gradually narrow the WS of SIG5 from 4.7µs and obtain the WS
at which synchronization with the HD output at TP23 is lost.

Input SIG5 (VL = 0mV, WS = 4.7µs, VS = variable) to (A) and
confirm that it is synchronized with the HD output at TP23.
Gradually reduce the VS of SIG5 from 143mV and obtain the VS
at which synchronization with the HD output at TP23 is lost.

Input SIG5 (VL = 0mV, WS = 4.7µs, VS = 143mV) to (A) and
measure the delay time with the RPD output at TP12. TDSYL is
from the falling edge of the input HSYNC to the falling edge of the
RPD output at TP12, and TDSYH is from the falling edge of the
input HSYNC to the rising edge of the RPD output at TP12.

Input SIG5 (VL = 0mV, WS = 4.7µs, VS = 143mV,
horizontal frequency variable) to (A) and confirm that it
is synchronized with the HD output at TP23. Obtain the
frequency f

at which the input and output are

synchronized by changing the horizontal frequency of
SIG5 from the non-synchronized condition.
HPLLN = f

15734

HPLLP = f

15625

VWLIM

White limiter DC
voltage difference

Input SIG5 (VL = 350mV) to (A). Measure the DC
voltage at TP41, TP44 and TP46 and obtain the
difference versus the RGB output voltage VOUT.

3.0

VDROFF

RGB output range
when FRP polarity
reverse is stopped

Input SIG8 to (A). Assume the black limiter level of
the output at TP41, TP44 and TP46 when serial bus
register BRIGHT = 0H as VDRB and the white
limiter level when BRIGHT = OFFH as VDRW.
VDROFF = VDRW VDRB

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

CXA2543R

tTLH

tTHL

DTYHC

VTEXTB

VTEXTW

TDEXTH

TDEXTL

EXTBK

EXTWT

0.8

1.0

1.2

1.8

2.0

2.2

100

150

100

150

3.5

180

Output transition
time (P12

pin)

Cross-point time
difference

HCK duty

Input SIG5 (VL = 0mV) to (A).
Measure the transition time for each output.
Load = 30pF
(See Fig. 3.)

Input SIG5 (VL = 0mV) to (A).
Measure HCK1/HCK2.
Load = 30pF
(See Fig. 4.)

Input SIG5 (VL = 0mV) to (A).
Measure the HCK1/HCK2 duty.
Load = 30pF

LOAD setup time, activated by the rising edge of
SCLK.

(See Fig. 6.)

DATA setup time, activated by the rising edge of
SCLK.

(See Fig. 6.)

LOAD hold time, activated by the rising edge of
SCLK.

(See Fig. 6.)

DATA hold time, activated by the rising edge of
SCLK.

(See Fig. 6.)

SCLK pulse width.

(See Fig. 6.)

SCLK pulse width.

(See Fig. 6.)

LOAD pulse width.

(See Fig. 6.)

150

160

µs

ts0

ts1

th0

th1

tw1L

tw1H

tw2

Serial transfer block

Data setup time

Data hold time

Minimum pulse
width

Input SIG5 (VL = 0mV) to (A) and SIG6 (VL variable) to (C).
Raise the SIG6 amplitude (VL) from 0V and assume the voltage
where the outputs at TP41, TP44 and TP46 go to black level as
VTEXTB. Then raise the amplitude further and assume the
voltage where these outputs go to white level as VTEXTW.
SW6, SW7, SW8 = B

Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 3V)
to (C). Measure the rise delay time TD1EXT and
the fall delay time TD2EXT of the outputs at
TP41, TP44 and TP46.
(See Fig. 2.)
SW6, SW7, SW8 = B

Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 1.7V)
to (C). Measure the difference from the black level
of the outputs at TP41, TP44 and TP46.
SW6, SW7, SW8 = B

Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 2.7V)
to (C). Measure the difference from the black level
of the outputs at TP41, TP44 and TP46.
SW6, SW7, SW8 = B

TEXTMIN

Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 2.7V) to (C).
Measure the minimum pulse width at which each of the
outputs at TP41, TP44 and TP46 reach the white limiter.
SW6, SW7, SW8 = B

External I/O characteristics

External RGB input
threshold voltage

Propagation delay
time between
external RGB input
and output

Output blanking
level during
external RGB input

Output white level
during external
RGB input

Minimum pulse
width during
external RGB input

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

CXA2543R

Setting 2

Power supply characteristics

Digital block I/O characteristics

Description of Electrical Characteristics Measurement Methods

Serial Bus Register Initial Values

Item

Symbol

Serial bus

Mode settings

Input

System

Aspect

S/H

HUE

COLOR

BRIGHT

CONTRAST

R-BRT

B-BRT

DAC settings

Low level input voltage

High level input voltage

Input current

CKI pin low input current

CKI pin high input current

High level output voltage

Low level output voltage

High level output voltage

Low level output voltage

High level output voltage

Low level output voltage

Output off leak current

VIL

VIH

II1

II2

II3

VOH1

VOL1

VOH2

VOL2

VOH3

VOL3

IOFF

COMP

Y/C

Y/color

difference

COMP

NTSC

Panel

LCX018

4:3

16:9

SHS1

80H

PSIG-BRT

80H

78H

80H

(: don't care, ADJ: adjustment, SET: setting)

Horizontal AFC

adjustment

Current

consumption V

Current

consumption V

2,3

Current

consumption V

CXA2543R

Y signal block

Item

Symbol

Serial bus

Mode settings

Input

System

Aspect

S/H

HUE

COLOR

BRIGHT

CONTRAST

R-BRT

B-BRT

DAC settings

Video maximum gain

Contrast

characteristics TYP

Contrast

characteristics MIN

Y signal frequency

response 1

Y signal frequency

response 2

Picture quality

adjustment variable

amount 1

Picture quality

adjustment variable

amount 2

Carrier leak

Y signal I/O delay

time

GCNTTP

GCNTMN

FCYYC

FCYCMN

FCYCMP

FCL

GSHP1X

GSHP1N

GSHP2X

GSHP2N

CRLEKY

TDYYC

TDYCMN

TDYCMP

COMP

Y/C

COMP

Y/C

COMP

Y/C

COMP

NTSC

PAL

NTSC

PAL

Panel

Through

80H

0A0H

60H

96H

0FFH

80H

PSIG-BRT

80H

(: don't care, ADJ: adjustment, SET: setting)

CXA2543R

Chroma signal block

Item

Symbol

Serial bus

Mode settings

Input

System

Aspect

S/H

HUE

COLOR

BRIGHT

CONTRAST

R-BRT

B-BRT

DAC settings

ACC amplitude

characteristics 1

ACC amplitude

characteristics 2

APC pull-in range

Color adjustment

characteristics MAX

Color adjustment

characteristics MIN

HUE adjustment

range MAX

HUE adjustment

range MIN

Killer operation

input level

Demodulation output

amplitude ratio NTSC

Demodulation output

phase difference NTSC

Demodulation output

amplitude ratio PAL

Demodulation output

phase difference PAL

ACC1

ACC2

FAPCN

FAPCP

GCOLMX

GCOLMN

HUEMX

HUEMN

ACKN

ACKP

VRBN

VGBN

RBN

GBN

VRBP

VGBP

RBP

GBP

COMP

NTSC

PAL

NTSC

PAL

NTSC

PAL

NTSC

PAL

NTSC

PAL

Panel

Through

80H

0FFH

80H

0FFH

80H

96H

60H

80H

PSIG-BRT

80H

(: don't care, ADJ: adjustment, SET: setting)

CXA2543R

Chroma signal block

RGB signal output block

Item

Symbol

Serial bus

Mode settings

Input

System

Aspect

S/H

HUE

COLOR

BRIGHT

CONTRAST

R-BRT

B-BRT

DAC settings

Color difference input

color adjustment

characteristics MAX

Color difference input

color adjustment

characteristics MIN

Color difference balance

Color difference input

balance adjustment R

Color difference input

balance adjustment B

G-Y matrix

characteristics NTSC

G-Y matrix

characteristics PAL

RGB signal and PSIG

output DC voltage

RGB signal and PSIG output

DC voltage difference

RGB and PSIG output

limiter operation voltage

Amount of change in

brightness

Amount of change in

PSIG

GEXCMX

GEXCMN

VEXCBL

GEXRMX

GEXRMN

GEXBMX

GEXBMN

VEXGBN

VEXGRN

VEXGBP

VEXGRP

VOUT

VLIMMX

VLIMMN

BRTMX

BRTMN

PSIGMX

PSIGMN

Y/color

difference

Y/color

difference

Y/color

difference

Y/color

difference

Y/color

difference

Y/color

difference

Y/color

difference

Y/color

difference

Y/color

difference

Y/color

difference

Y/color

difference

NTSC

PAL

Panel

Through

80H

0FFH

80H

0FFH

80H

96H

ADJ

0FFH

80H

PSIG-BRT

80H

64H

0FFH

(: don't care, ADJ: adjustment, SET: setting)

CXA2543R

RGB signal output block

Item

Symbol

Serial bus

Mode settings

Input

System

Aspect

S/H

HUE

COLOR

BRIGHT

CONTRAST

R-BRT

B-BRT

DAC settings

Amount of change in

sub-brightness

Difference in gain between

RGB output signals

Difference in RGB output

inverted/non-inverted gain

Difference in black

level potential between

RGB output signals

gain

1 adjustment

variable range

2 adjustment

variable range

PSIG transition time

RGB output white limiter

operation voltage

Black limiter DC

voltage difference

White limiter DC

voltage difference

RGB output range

when FRP polarity

reverse is stopped

SBBRT

GRGB

GINV

VBL

1MN

1MX

2MN

2MX

PSIGH

PSIGL

VWLIM

VBLIM

VWLIM

VDROFF

Panel

Through

80H

0B4H

80H

ADJ

60H

0B4H

SET

80H

ADJ

46H

80H

0FFH

80H

0FFH

80H

SET

80H

SET

80H

78H

0FFH

0D7H

0FFH

PSIG-BRT

80H

0FFH

80H

(: don't care, ADJ: adjustment, SET: setting)

CXA2543R

Sync separation, TG block

Filter characteristics

External I/O characteristics

Item

Symbol

Serial bus

Mode settings

Input

System

Panel

S/H

HUE

COLOR

BRIGHT

CONTRAST

R-BRT

B-BRT

DAC settings

PSIG-BRT

(: don't care, ADJ: adjustment, SET: setting)

Amount of BPF attenuation

Amount of TRAP attenuation

R-Y, B-Y and LPF characteristics

Input sync signal width sensitivity

Sync separation input sensitivity

Sync separation output

delay time

Horizontal pull-in range

Output transition time

Cross-point time difference

HCK duty

External RGB input

threshold voltage

Propagation delay time between

external RGB input and output

Output blanking level during

external RGB input

Output white level during

external RGB input

Minimum pulse width during

external RGB input

ATBPF

COMP

SET

Y/C

COMP

NTSC

PAL

NTSC

PAL

Through

80H

60H

80H

64H

80H

Through

ATRAPN

ATRAPP

DEMLPF

WSSEP

VSSEP

TDSYL

TDSYH

HPLLN

HPLLP

tTLH

tTHL

DTYHC

VTEXTB

VTEXTW

TDEXTH

TDEXTL

EXTBK

EXTWT

TEXTMIN

Aspect

CXA2543R

Electrical Characteristics Measurement Circuit

V62

TP11

TP17

0.47µ

47µ

0.1µ

0.47µ

TP44

300p

TP46

300p

TP39

10000p

0.01µ

TP53

(E)

(D)

0.068µ

15k

0.22µ

SW54

V54

1µ

47µ

0.1µ

+4.5V

(B)

15k

SW64

V64

47µ

0.1µ

TP12

33k

220p

0.01µ

3.3µ

10k

0.47µ

750

0.033µ

(C)

(A)

TP18

TP19

TP20

TP21

TP22

TP23

TP24

TP25

TP26

TP27

TP28

TP29

TP30

TP32

TP33

TP34

TP35

TP36

+12V

TP41

300p

B-Y IN

R-Y IN

C OUT

BLK LIM

APC

VXO OUT

VXO IN

V REG

C IN

TEST3

Y IN

PIC

F0 ADJ

PWRST

XEN

VCK1

VCK2

VST

XVST

FLD IN

PCG

XPCG

HCK1

HCK2

HST

XHST

.
S

I
N

.
F

I
L

I
N

I
G

SIG.CENTER

1µ

SW52

SW51

SW59

I
N

0.47µ

10k

SW6 SW7 SW8

TP10

TP9

TP60

0.01µ

V14

SW62

Used crystal: KINSEKI CX-5F

Frequency deviation: within ±30ppm, frequency temperature
characteristics: within ±30ppm, load capacity: 16pF
NTSC: 3.579545MHz
PAL: 4.433619MHz

NTSC: shorted, PAL: 18pF

Variable Capcitance Diode: 1T369 (SONY)

DCX501 mode: L value: 4.7µH, C value: 22pF
LCX018 (4:3) mode: L value: 4.7µH, C value: 22pF
LCX018 (16:9) mode: L value: 2.2µH, C value: 33pF

Trap (TDK)
NTSC: NLT4532-S3R6B
PAL: NLT4532-S4R4

Resistance value tolerance: ±2%,
temperature coefficient: ±200ppm or less

CXA2543R

Description of Operation

The CXA2543R incorporates the three functions of an RGB decoder block, an RGB driver block and a timing

generator (TG) block onto a single chip using Bi-CMOS technology.

1) RGB decoder block

· Input mode switching

The input mode can be switched between composite input, Y/C input and Y/color difference input by the

serial bus settings.

During composite input:

The composite signal is input to Pins 3, 59 and 61.

During Y/C input:

The Y signal is input to Pins 3 and 61, and the C signal to Pin 59.

During Y/color difference input: The Y signal is input to Pins 3 and 61, the B-Y signal to Pin 51, and the R-Y

signal to Pin 52.

· System switching

The input system can be switched between NTSC and PAL (DPAL using external delay lines and SPAL ) by

the serial bus settings.

· Trap, BPF

The center frequency of the built-in trap and BPF can be switched to 3.58Hz during NTSC and 4.43Hz during

PAL.

During composite input, the Y signal enters the trap circuit and the C signal enters the BPF. These signals do

not pass through the trap or BPF during Y/C input and Y/color difference input.

· ACC detection, ACC amplifier

The amplitude of the burst signal output from the ACC amplifier is detected and the ACC amplifier is

controlled to maintain the burst signal amplitude at a constant level.

· VXO, APC detection

The VXO local oscillation circuit is a crystal oscillation circuit. The phases of the input burst signal and the

VXO oscillator output are compared in the APC detection block, and the detective output is used to form a

PLL loop that controls the VXO oscillation frequency, which means that the need for adjustments is

eliminated.

· External inputs

These are digital inputs with two thresholds. When one of the RGB inputs is higher than the lower threshold

Vth1 (

1.0V), all RGB outputs go to black level. When the higher threshold Vth2 (

2.0V) is exceeded, the

output for only the signal in question goes to white level, while the other outputs remain at black level.

CXA2543R

· Sample-and-hold circuit

As LCD panels sample RGB signals simultaneously, RGB signals output from the CXA2543R must be

sampled-and-hold in sync with the LCD panel drive pulses.

S/H4

S/H2

SH2

S/H1

SH1

S/H3

SH3

SH4

HCK1

2) RGB driver block

correction

In order to support the characteristics of LCD panels, the I/O characteristics are as shown in Fig. 1. The

characteristics change as shown in Fig. 2 by adjusting the serial bus register

1, and as shown in Fig. 3 by

adjusting

Input

Output

Fig. 1

Input

Output

Fig. 2

Input

Output

Fig. 3

The sample-and-hold circuit performs sample-and-hold by receiving the SH1 to SH4 pulses from the TG

block. Since LCD panels perform color coding using an RGB delta arrangement, each horizontal line must

be compensated by 1.5 dots. This relationship is reversed during right/left inversion. This compensation

timing is also generated by the TG block. The sample-and-hold timing changes according to the phase

relationship with the HCK1 pulse, so the timing should be set to SHS1, 2 or 3 in accordance with the actual

board.

RGT = H (normal)

RGT = L (inverted)

SHS1

SH1

SH2

SH3

SH4

Through

SHS2

SHS3

SHS1

SH1

SH2

SH3

SH4

Through

SHS2

SHS3

LCX018

RGT = H (normal)

RGT = L (inverted)

SHS1

SH1

SH2

SH3

SH4

Through

SHS2

SHS3

SHS1

SH1

SH2

SH3

SH4

Through

SHS2

SHS3

SH1: R signal SH pulse

SH2: G signal SH pulse

SH3: B signal SH pulse

SH4: RGB signal SH pulse

DCX501

CXA2543R

· RGB output

RGB outputs (Pins 41, 44, and 46) are inverted each horizontal line by the FRP pulse supplied from the TG

block as shown in the figure below. Feedback is applied so that the center voltage (Vsig center) of the output

signal matches the reference voltage (V

2 + GND2)/2 (or the voltage input to SIG CENTER (Pin 50)). In

addition, the white level output is clipped by the Vsig center ±0.7V, and the black level output is clipped by

the limiter operation point that is adjusted at the BLKLIM (Pin 54).

Video IN

FRP

RGB OUT

Black level limiter

White level limiter

Black level limiter

Vsig center

3) TG block

· PLL and AFC circuits

The TG block contains a PLL circuit phase comparator and frequency division counter, and a PLL circuit can

be comprised by connecting an external VCO circuit.

The PLL error detection signal is generated at the following timing. The phase comparison output of the

entire bottom of HSYNC and the internal frequency division counter becomes RPD. RPD output is converted

to DC error with the lag-lead filter, and then it changes the capacitance of variable capacitance diode to

stabilize the oscillation frequency at 1066f

in the DCX501BK and LCX018AK (4:3) mode, 1417f

in the

LCX018AK (16:9) mode. The PLL of this system is adjusted by setting the the reverse bias voltage of the

varicap diode (V14) so that the point at which RPD changes is at the center of the window depicted in the

figure below.

H SYNC

RPD

WL = WH

· H position

The horizontal display position can be set at 2f

intervals in 32 different ways by the serial bus settings.

The picture center is set at the internal default value, but because there is a difference between the RGB

signal and the drive pulse delays on the actual board, the picture center may not match the design center. In

this case, adjust with the serial bus.

CXA2543R

· Right/left inversion

The LCD panel is arranged in a delta arrangement, where identical signal lines are offset by 1.5 dots from

adjoining lines. For this reason, a 1.5-bit offset is attached to the horizontal start pulse (HST) between odd

lines and even lines. HCK and S/H are also 1.5-bit offset.

When the panel is driven by left scan (Reverse scan), this offset relationship is inverted for even and odd

lines. Moreover, since the dot arrangement is asymmetrical, the HST position is also changed.

RGT = H: Right scan mode

RGT = L: Left scan mode

H SCANNER

Left scan

(Reverse scan)

Right scan

(Normal scan)

Display area

LCD panel

· WIDE mode (DCX501BK mode)

Setting the WIDE mode by switching the aspect with the serial bus shifts the unit to WIDE mode. In the

DCX501BK mode, the aspect ratio is converted through pulse eliminator processing, allowing 16:9 quasi-WIDE

display. During WIDE mode, vertical pulse eliminator scanning of 1/4 for NTSC or 1/2 and 1/4 for PAL are

performed, and the video signal is compressed to achieve a 16:9 aspect ratio. In addition, in areas outside

the display area, black is displayed in the 28 lines, respectively at the top and bottom of this display area by

performing high-speed scanning

The method of black display is a writing method by PSIG. By setting PSIG level during high-speed scanning

to black display level and writing this black display level at the PCG timing, reliable black display is realized

within the limited V blanking period.

During this period, HST is masked and video signal input is limited.

See the attached sheets for detailed timing.

Display area

Black display area

Vertical high-speed scanning

Vertical pulse eliminator scanning

16:9 display

4:3 display

225 LINES

169 LINES

28 LINES

DCX501BK

CXA2543R

· AC driving of LCD panels during no signal

HST, XHST, HCK1, HCK2, VST, XVST, VCK1, VCK2, PCG, XPCG, EN, XEN, HD, VD, and FRP are made

to run freely so that the LCD panel is AC driven even when there is no composite sync from the SYNC IN pin.

During this time, the HSYNC separation circuit stops and the PLL counter is made to run freely. In addition,

the VSYNC separation circuit is also stopped, so the auxiliary V counter is used to create the reference pulse

for generating VD, VST and XVST.

The cycle of this v counter is designed to be 525/2H for NTSC and 625/2H for PAL. However, when there is

no vertical sync signal for 5 fields, the no signal state is assumed and the free running VD, VST and XVST

pulses are generated from the next field.

In addition, RPD is kept at high impedance when there is no signal in order to prevent the AFC circuit from

causing errors due to phase comparison.

During high-speed scanning

During normal-speed scanning

Double-speed scanning

Stop

1H cycle

HST

VCKn

FRP
(Internal pulse)

PCG

CXA2543R

Description of Serial Control Operation

1) Control method

Control data consists of 16 bits of data which is loaded one bit at a time at the rising edge of SCLK. This
loading operation starts from the falling edge of LOAD and is completed at the next rising edge. (D13 to D15
are dummy data.)

Digital block control data is established by the vertical sync signal and the LOAD "H". If data is transferred
multiple times for the same item, the data immediately before the vertical sync signal is valid.
Analog (electronic attenuator) block control data becomes valid each time the LOAD signal is input.

D15 D14 D13 D12 D11 D10 D9

DATA

SCLK

LOAD

Serial transfer timing

2) Serial data map

The serial data map is as follows.

D15

PCG width

EN width

PCG position

EN position

D14

D13

D12

D11

D10

S/H phase

HD-POSITION

H-POSITION

HUE

COLOR

BRIGHT

CONTRAST

R-BRT

B-BRT

PSIG-BRT

VD
polarity

HD
polarity

Supported
panel

External

V SYNC

FRP
polarity

SYNC
GEN

FRP256

inversion

Mode

PAL
decima
-tion

Aspect

Up/down

inversion

Y/color
difference
clamp

FIELD
determi
-nation

System

Input
switching

Note) Any data transfer performed when addresses D8, D9, D10, D11, D12 = 1, 1, 1, 1, 1 (shadowed portion)

will result in test mode regardless of other data settings.

Do not transfer data with these addresses set this way.

TEST

CXA2543R

3) Serial data mode settings (X: don't care)

· Input switching

Composite input (default)

Y/C input

Y/color difference input

· System switching

NTSC (default)

D-PAL

S-PAL

· Supported panel switching

DCX501BK (default)

LCX018AK

· Aspect switching

4:3 (default)

16:9

· Sample-and-hold timing switching

SHS1 (default)

SHS2

SHS3

Through (sample-and-hold not performed)

· HD output polarity switching

Negative polarity (default)

Positive polarity

· VD output polarity switching

Negative polarity (default)

Positive polarity

· Y/color difference clamp position switching

This switches the position at which the R-Y and B-Y input signals are clamped during Y/color difference input mode.

Pedestal position (default)

SYNC position

· Mode switching

This is the test mode. Set to normal mode.

Normal mode (default)

Test mode

CXA2543R

· Sync generator function

This stops outputs other than VD and HD of the TG block.

OFF (default)

Note) Make sure that Vcc2, 3 (12V) and LCD panel power supply should be turned OFF during sync generator

ON.

· Up/down inversion function

This switches the up/down inverted display.

DOWN (normal display) (default)

UP (up/down inverted display)

· FRP256 field inversion

This further inverts the polarity of the RGB output that is inverted every 1H for 256 fields.

OFF (default)

· FRP polarity inversion function

ON (1H inversion) (default)

OFF (polarity not inverted)

· External field identification input switching

Internal field identification is not performed and an externally field input source is used.

OFF (internal identification) (default)

ON (external input)

· External VSYNC input switching

Internal VSYNC separation is not performed and an externally input VSYNC is used.

OFF (internal separation) (default)

ON (external input)

· PAL pulse elimination switching

This switches on/off the PAL pulse elimination function during PAL mode.

ON (elimination performed) (default)

OFF (elimination not performed)

CXA2543R

· PCG pulse position

This sets the PCG pulse position (A in the figure below).

(default)

DCX501 and LCX018 (4:3) mode: variable in 6f

(= 1 bit) increments

LCX018 (16:9) mode: variable in 9f

(= 1 bit) increments

· PCG pulse width

This sets the PCG pulse width (B in the figure below).

(default)

DCX501 and LCX018 (4:3) mode: variable in 8f

(= 1 bit) increments

LCX018 (16:9) mode: variable in 12f

(= 1 bit) increments

· EN pulse position

This sets the EN pulse position (C in the figure below).

(default)

DCX501 and LCX018 (4:3) mode: variable in 4f

(= 1 bit) increments

LCX018 (16:9) mode: variable in 6f

(= 1 bit) increments

· EN pulse width

This sets the EN pulse width (D in the figure below).

(default)

DCX501 and LCX018 (4:3) mode: variable in 8f

(= 1 bit) increments

LCX018 (16:9) mode: variable in 12f

(= 1 bit) increments

HSYNC

PCG

Setting Correspondence Table

Set the positions and widths for the EN and PCG pulses as follows when driving the DCX501BK and the LCX018AK.

LCX018AK

Width

PCG pulse

EN pulse

Position

DCX501BK

Width

PCG pulse

EN pulse

Position

CXA2543R

4) Serial data electronic attenuator (D/A converter) settings

· HUE

0 (default)

· COLOR

0 (default)

· BRIGHT

0 (default)

· CONTRAST

0 (default)

· R-BRT

0 (default)

· B-BRT

0 (default)

· PSIG-BRT

0 (default)

5) Test mode

Test mode results if data is sent to the following addresses.

For this reason, do not perform data transfer using these addresses.

D12

D11

D10

Note) If data transfer is performed in these addresses, the chip will enter test mode regardless of the data set.

CXA2543R

DCX501BK Color Coding Diagram

The delta arrangement is used for the color coding in the LCD panels with which this IC is compatible. Note

that the shaded region within the diagram is not displayed.

DCX501BK pixel arrangement

800

803

dummy2

Vline3

Vline2

Vline1

dummy1

HSW1

HSW266

HSW267

225 227

Display area

HSW2

Vline225

Vline224

HSW268

Precharge SW

HSW3

Photo-shielding
area

CXA2543R

LCX018AK Pixel Arrangement (4:3)

t
s

:
3

r
e

i
d

l
a

i
d

l
a

2 d

ots

5 d

ots

ffe

cti

)

2 d

ots

t
s

(
e

f
f
e

t
i
v

.
6

)

t
s

CXA2543R

LCX018AK Pixel Arrangement (16:9)

t
s

2 d

ots

5 d

ots

ffe

cti

)

2 d

ots

t
s

(
e

f
f
e

t
i
v

.
4

)

CXA2543R

(
P

)

(
B

)

(
I
n

t
e

r
n

l

p

l
s

)

I
G

(
I
n

t
e

r
n

l

p

l
s

)

/
V

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
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r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

.
7

(
7

)

.
7

(
7

)

.
5

(
7

)

.
0

(
3

)

.
5

(
1

.
5

)

.
0

(
8

.
5

)

.
5

(
2

)

I
E

.
5

(
4

)

.
0

(
1

)

.
0

(
1

)

DCX501BK Horizontal Direction Timing Chart

NTSC/PAL

Unless otherwise specified, serial settings are the default values.

RGT: H (Normal scan)

1066f

ODD LINE

Note)

The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.

FRP polarity is not specified for each line and field.

CXA2543R

(
P

)

(
B

)

(
I
n

t
e

r
n

l

p

l
s

)

I
G

(
I
n

t
e

r
n

l

p

l
s

)

/
V

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
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r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

.
7

(
7

)

.
7

(
7

)

.
5

(
7

)

.
0

(
3

)

.
5

(
2

)

.
0

(
1

)

.
5

(
4

)

.
0

(
1

)

I
E

DCX501BK Horizontal Direction Timing Chart

NTSC/PAL

Unless otherwise specified, serial settings are the default values.

RGT: H (Normal scan)

1066f

EVEN LINE

Note)

The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.

FRP polarity is not specified for each line and field.

CXA2543R

(
P

)

(
B

)

(
I
n

t
e

r
n

l

p

l
s

)

I
G

(
I
n

t
e

r
n

l

p

l
s

)

/
V

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

.
7

(
7

)

.
0

(
3

)

.
7

(
7

)

.
5

(
7

)

.
5

(
1

.
5

)

.
0

(
1

)

.
5

(
4

)

.
0

(
1

)

.
5

(
2

)

I
E

.
0

(
8

.
5

)

DCX501BK Horizontal Direction Timing Chart

NTSC/PAL

Unless otherwise specified, serial settings are the default values.

RGT: L (Reverse scan)

1066f

ODD LINE

Note)

The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.

FRP polarity is not specified for each line and field.

CXA2543R

(
P

)

(
B

)

(
I
n

t
e

r
n

l

p

l
s

)

I
G

(
I
n

t
e

r
n

l

p

l
s

)

/
V

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

.
7

(
7

)

.
7

(
7

)

.
5

(
7

)

.
0

(
3

)

.
5

(
2

)

.
5

(
4

)

.
0

(
1

)

.
0

(
1

)

I
E

DCX501BK Horizontal Direction Timing Chart

NTSC/PAL

Unless otherwise specified, serial settings are the default values.

RGT: L (Reverse scan)

1066f

EVEN LINE

Note)

The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.

FRP polarity is not specified for each line and field.

CXA2543R

(
P

)

(
B

)

(
I
n

t
e

r
n

l

p

l
s

)

I
G

(
I
n

t
e

r
n

l

p

l
s

)

/
V

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

.
7

(
7

)

.
0

(
3

)

.
7

(
7

)

.
5

(
7

)

.
5

.
0

(
1

.
5

)

.
2

(
3

)

.
0

(
1

)

.
5

(
4

)

.
0

(
1

)

.
5

(
7

)

I
E

.
5

(
7

.
5

)

.
5

(
8

)

LCX018AK Horizontal Direction Timing Chart (4:3)

NTSC/PAL

Unless otherwise specified, serial settings are the default values.

RGT: H (Normal scan), PCG width: LH, EN position: HH

Master Clock: 16.773MHz (NTSC) / 16.656MHz (PAL)

PLL Counter N: 1066f

ODD LINE

Note)

The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.

FRP polarity is not specified for each line and field.

CXA2543R

(
P

)

(
B

)

(
I
n

t
e

r
n

l

p

l
s

)

I
G

(
I
n

t
e

r
n

l

p

l
s

)

/
V

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

I
E

.
5

(
7

)

.
0

(
1

)

.
5

(
4

)

.
0

(
1

)

.
2

(
3

)

.
7

(
7

)

.
5

(
7

)

.
7

(
7

)

.
0

(
3

)

.
5

(
8

)

LCX018AK Horizontal Direction Timing Chart (4:3)

NTSC/PAL

EVEN LINE

Note)

The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.

FRP polarity is not specified for each line and field.

Unless otherwise specified, serial settings are the default values.

RGT: H (Normal scan), PCG width: LH, EN position: HH

Master Clock: 16.773MHz (NTSC) / 16.656MHz (PAL)

PLL Counter N: 1066f

CXA2543R

(
P

)

(
B

)

(
I
n

t
e

r
n

l

p

l
s

)

I
G

(
I
n

t
e

r
n

l

p

l
s

)

/
V

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

I
E

.
2

(
3

)

I
E

.
5

(
7

)

.
0

(
3

)

.
7

(
7

)

.
5

(
7

.
5

)

.
0

(
1

.
5

)

.
0

(
1

)

.
5

(
7

)

.
5

(
4

)

.
0

(
1

)

.
7

(
7

)

.
5

(
8

)

LCX018AK Horizontal Direction Timing Chart (4:3)

NTSC/PAL

ODD LINE

Note)

The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.

FRP polarity is not specified for each line and field.

Unless otherwise specified, serial settings are the default values.

RGT: L (Reverse scan), PCG width: LH, EN position: HH

Master Clock: 16.773MHz (NTSC) / 16.656MHz (PAL)

PLL Counter N: 1066f

CXA2543R

.
7

(
7

)

.
7

(
7

)

.
5

(
7

)

.
0

(
3

)

I
E

.
0

(
1

)

.
0

(
1

)

I
E

.
5

(
4

)

.
5

(
8

)

.
5

(
7

)

(
B

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

/
V

(
P

)

I
G

(
I
n

t
e

r
n

l

p

l
s

)

.
2

(
3

)

LCX018AK Horizontal Direction Timing Chart (4:3)

NTSC/PAL

EVEN LINE

Note)

The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.

FRP polarity is not specified for each line and field.

Unless otherwise specified, serial settings are the default values.

RGT: L (Reverse scan), PCG width: LH, EN position: HH

Master Clock: 16.773MHz (NTSC) / 16.656MHz (PAL)

PLL Counter N: 1066f

CXA2543R

.
7

(
1

)

.
7

(
1

)

.
5

(
1

)

.
0

(
4

)

.
0

(
1

)

.
5

(
1

)

.
2

(
5

)

.
5

(
5

)

.
5

(
1

)

(
B

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

/
V

(
P

)

I
G

(
I
n

t
e

r
n

l

p

l
s

)

.
5

.
0

(
1

.
5

)

.
5

(
1

.
5

)

I
E

.
0

(
2

)

LCX018AK Horizontal Direction Timing Chart (16:9)

NTSC/PAL

ODD LINE

Note)

The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.

FRP polarity is not specified for each line and field.

Unless otherwise specified, serial settings are the default values.

RGT: H (Normal scan), PCG width: LH, EN position: HH

Master Clock: 22.295MHz (NTSC) / 22.141MHz (PAL)

PLL Counter N: 1417f

CXA2543R

Note)

The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.

FRP polarity is not specified for each line and field.

.
7

(
1

)

.
7

(
1

)

.
5

(
1

)

.
0

(
4

)

.
2

(
5

)

.
5

(
5

)

(
B

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

/
V

(
P

)

I
G

(
I
n

t
e

r
n

l

p

l
s

)

.
5

(
1

)

.
0

(
1

)

.
5

(
1

)

I
E

.
0

(
2

)

LCX018AK Horizontal Direction Timing Chart (16:9)

NTSC/PAL

EVEN LINE

Unless otherwise specified, serial settings are the default values.

RGT: H (Normal scan), PCG width: LH, EN position: HH

Master Clock: 22.295MHz (NTSC) / 22.141MHz (PAL)

PLL Counter N: 1417f

CXA2543R

.
0

(
4

)

.
5

(
1

)

(
B

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

/
V

(
P

)

I
G

(
I
n

t
e

r
n

l

p

l
s

)

.
7

(
1

)

.
7

(
1

)

.
5

(
1

)

.
5

.
0

(
1

.
5

)

.
5

(
1

.
5

)

.
2

(
5

)

.
5

(
1

)

.
5

(
5

)

.
0

(
1

)

I
E

.
0

(
2

)

LCX018AK Horizontal Direction Timing Chart (16:9)

NTSC/PAL

ODD LINE

Note)

The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.

FRP polarity is not specified for each line and field.

Unless otherwise specified, serial settings are the default values.

RGT: L (Reverse scan), PCG width: LH, EN position: HH

Master Clock: 22.295MHz (NTSC) / 22.141MHz (PAL)

PLL Counter N: 1417f

CXA2543R

.
7

(
1

)

(
B

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

(
I
n

t
e

r
n

l

p

l
s

)

/
V

(
P

)

I
G

(
I
n

t
e

r
n

l

p

l
s

)

.
7

(
1

)

.
5

(
1

)

.
0

(
4

)

.
2

(
5

)

.
5

(
1

)

.
5

(
5

)

.
0

(
1

)

.
5

(
1

)

I
E

.
0

(
2

)

LCX018AK Horizontal Direction Timing Chart (16:9)

NTSC/PAL

EVEN LINE

Note)

The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.

FRP polarity is not specified for each line and field.

Unless otherwise specified, serial settings are the default values.

RGT: L (Reverse scan), PCG width: LH, EN position: HH

Master Clock: 22.295MHz (NTSC) / 22.141MHz (PAL)

PLL Counter N: 1417f

CXA2543R

Application Circuit (NTSC/PAL, COMP and Y/C input)

0.47µ

750

0.033µ

0.47µ

47µ

0.1µ

+12V

+3V

0.47µ

To LCD panel

15k

+4.5V

47µ

0.1µ

1µ

+4.5V

47µ

0.1µ

+3V

33k

220p

3.3µ

10k

To LCD panel

0.01µ

0.068µ

15k

0.22µ

+4.5V

47k

0.01µ

Y/C

COMP

C IN

1µ

47k

0.01µ

COMP/Y IN

To Serial controller

B-Y IN

R-Y IN

C OUT

BLK LIM

APC

VXO OUT

VXO IN

V REG

C IN

TEST3

Y IN

PIC

F0 ADJ

PWRST

XEN

VCK1

VCK2

VST

XVST

FLD IN

PCG

XPCG

HCK1

HCK2

HST

XHST

.
S

I
N

.
F

I
L

I
N

I
G

SIG.CENTER

I
N

10k

0.01µ

47k

3.3k

OUT

+12V

Sample PSIG buffer circuit

Buff

0.01µ

12V

Used crystal: KINSEKI CX-5F

Frequency deviation: within ±30ppm, frequency temperature
characteristics: within ±30ppm, load capacity: 16pF
NTSC: 3.579545Hz
PAL: 4.433619Hz

NTSC: shorted, PAL: 18pF

Variable Capcitance Diode: 1T369 (SONY)

DCX501 mode: L value: 4.7µH, C value: 22pF
LCX018 (4:3) mode: L value: 4.7µH, C value: 22pF
LCX018 (16:9) mode: L value: 2.2µH, C value: 33pF

Trap (TDK)
NTSC: NLT4532-S3R6B
PAL: NLT4532-S4R4

Resistance value variation: ±2%,
temperature coefficient: ±200ppm or less
Connect to +4.5V during Y/C input

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

CXA2543R

Application Circuit (NTSC/PAL, Y/color difference input)

0.47µ

750

0.033µ

0.47µ

47µ

0.1µ

+12V

+3V

0.47µ

To LCD panel

+4.5V

47µ

0.1µ

1µ

+4.5V

47µ

0.1µ

+3V

33k

220p

3.3µ

10k

To LCD panel

0.1µ

+4.5V

47k

0.01µ

1µ

47k

0.01µ

COMP/Y IN

To Serial controller

B-Y IN

R-Y IN

C OUT

BLK LIM

APC

VXO OUT

VXO IN

V REG

C IN

TEST3

Y IN

PIC

F0 ADJ

PWRST

XEN

VCK1

VCK2

VST

XVST

FLD IN

PCG

XPCG

HCK1

HCK2

HST

XHST

.
S

I
N

.
F

I
L

I
N

I
G

SIG.CENTER

I
N

10k

0.01µ

47k

3.3k

OUT

+12V

Sample PSIG buffer circuit

Buff

R-Y IN

B-Y IN

0.01µ

+12V

+4.5V

Variable Capcitance Diode: 1T369 (SONY)

DCX501 mode: L value: 4.7µH, C value: 22pF
LCX018 (4:3) mode: L value: 4.7µH, C value: 22pF
LCX018 (16:9) mode: L value: 2.2µH, C value: 33pF

CXA2543R

Example of Representative Characteristics

HUE adjustment characteristics

0A0 0C0 0E0 0FF

DAC value

PAL

j
u

t
m

t

a

l
e

[
d

]

COLOR adjustment characteristics

0A0 0C0 0E0 0FF

DAC value

i
n

[
d

]

BRIGHT adjustment characteristics

0A0 0C0 0E0 0FF

DAC value

Non-inverted black

-
i
n

r
t
e

t
p

t

b

l
a

l
e

l

[
V

]

I
n

r
t
e

t
p

t

b

l
a

l
e

l

[
V

]

Inverted black

CONTRAST adjustment characteristics

0A0 0C0 0E0 0FF

DAC value

t
p

t

g

i
n

[
d

]

1.5

1.0

0.5

1.0

1.5

SUB-BRIGHT adjustment characteristics

0A0 0C0 0E0 0FF

DAC value

t
p

t

l
e

l

w

i
t
h

r
e

t

t
o

t
p

t

[
V

]

DAC value

PSIG-BRIGHT adjustment characteristics

0A0 0C0 0E0 0FF

t
p

t

l
e

l

[
V

-
p

]

CXA2543R

Color difference balance adjustment

80 0A0 0C0 0E0 0FF

DAC value

B-Y output

R-Y output

Color difference COLOR adjustment characteristics

0A0 0C0 0E0 0FF

DAC value

i
n

[
d

]

i
n

[
d

]

Sharpness characteristics (COMP, NTSC)

Frequency [MHz]

2.25V

i
n

[
d

]

4.5V

Sharpness characteristics (COMP, PAL)

Frequency [MHz]

2.25V

i
n

[
d

]

4.5V

Sharpness characteristics (Y/C)

Frequency [MHz]

2.25V

i
n

[
d

]

4.5V

Pin voltage [V]

Black level limiter adjustment characteristics

1.0

1.5

2.0

2.5

3.0

3.5

4.0

i
m

i
t
e

r

l
e

l

[
V

-
p

]

CXA2543R

Notes on Operation

The CXA2543R contains digital circuits, so the set board pattern must be designed in consideration of
undesired radiation, interference to analog circuits, etc. Care should also be taken for the following items when
designing the pattern.

· Make the IC power supply and GND patterns as plain as possible. In particular, GND and V

should not be

separated and should be connected to the same GND pattern as close to the pins as possible.

· Connect the by-pass capacitors between the power supplies and GND as close to the pins as possible.

· The trap connected to Pin 1 should be located as close to the pin as possible. Also, don't pass other signal

lines close to this pin or the connected trap.

· The wiring for the crystal and capacitor connected to Pins 56 and 57 should be as short as possible in order

to prevent floating capacitance. Don't pass other signal lines close to these pins in order to prevent
interference such as color unevenness. In addition, the APC pull-in characteristics vary significantly
according to the characteristics of the used crystal and the wiring pattern, so be sure to thoroughly
investigate these items before using the set.

· The resistor connected to Pin 63 should be located as close to the pin as possible. Also, take care not to

pass other signal lines close to this pin.

The composite/Y signal and the external R-Y and B-Y signals are clamped at the inputs using the capacitors
connected to the input pins, so these signals should be input at sufficiently low impedance. The C signal is
received by the internal capacitor, so this signal should be directly input at low impedance.

The smoothing capacitor of the DC level control feedback circuit in the output block should have a leak current
with a small absolute value and variance.

A thorough study of the external buffer for PSIG output should be made before deciding on a circuit to
ascertain that it sufficiently brings out the characteristics of the LCD panel.

If this IC is used in connection with a circuit other than an LCD, it may cause that circuit to malfunction
depending on the order power is supplied to the circuits. Thoroughly study the consequences of using this IC
with other circuits before deciding on its use.

Since this IC utilizes a C-MOS structure, it may latch up due to excessive noise or power surge greater than
the maximum rating of the I/O pins, or due to interface with the power supply of another circuit, or due to the
order in which power is supplied to circuits. Be sure to take measures against the possibility of latch up.

Do not apply a voltage higher than V

or lower than V

to I/O pins.

Do not use this IC under operating conditions other than those given.

Absolute maximum rating values should not be exceeded even momentarily. Exceeding ratings may damage
the device, leading to eventual breakdown.

This IC has a MOS structure which is easily damaged by static electricity, so thorough measures should be
taken to prevent electrostatic discharge.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA2543R

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA2543R