--1--

E97657A89-TE

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Absolute Maximum Ratings (Ta=25 °C)

· Supply voltage

0.3 to +5.5

· Storage temperature

Tstg

55 to +150

°C

Operating Conditions

· Supply voltage

4.75 to 5.3

· Operating temperature

Topr

25 to +75

°C

Description

The CXA3067M is an integrated circuit designed

for CATV wide band FSK receiver. This monolithic

IC is composed of local oscillator, double balanced

mixer, limiter, FM detector, data shaper and PLL

circuit in a single chip.

Features

· Built in PLL

· 3 bits 3 states frequency selection

· Applied for 4 reference frequency

(7.15625/7.15909/14.3125/14.31818 MHz)

· Compatible with external reference clock and X'tal

oscillator

· Balanced oscillator and double balanced mixer for

low L.O. leakage

· Low power consumption

· SOP 30 pin package

Function

· Oscillator

· Mixer

· PLL

· Limiter

· FSK detector

· Data shaper

Applications

FSK receiver for CATV

Structure

Bipolar silicon monolithic IC

Wide Band FSK Receiver

30 pin SOP (Plastic)

CXA3067M

--2--

CXA3067M

Pin configuration and Block diagram

I
X

I
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I
F

I
N

I
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I
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I
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I
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V.REG

FREQ
SELECT

PHASE
DET

MAIN
DIVIDER

REF
DIVIDER

CHARGE
PUMP

SCALER

REF
OSC

DATA
SHAPER

DET

MIX

OSC

LIM

--3--

CXA3067M

Pin Description and Equivalent Circuit

Symbol

Typical

Equivalent circuit

Description

No.

voltage (V)

REFIN

XTAL

FSET1

RDSW

CPLF

3.4

4.0

2.5

(OPEN)

3.0

(OPEN)

2.0

0.3 to V

500

DVCC

DGND

20k

DVCC

DGND

25k

20k

30k

DVCC

DGND

DVCC

10k

100

DGND

External clock input

and X'tal connection for

reference oscillator.

X'tal connection for

reference oscillator.

The pin for channel selection.

The condition of pin 3 has

3 states.

Connect to 5 V source for "Hi"

selection and connect to GND for

"Low" selection and leave open.

Reference frequency selection.

Connect to GND when reference

frequency is 14.3125 MHz or

14.31818 MHz and leave open

when reference frequency is

7.15625 MHz or 7.15909 MHz.

Charge pump output.

Connect to loop filter.

OSC tuning voltage output.

--4--

CXA3067M

Symbol

Typical

Equivalent circuit

Description

No.

voltage (V)

OSC1

OSC2

DGND

MIXOUT

DVCC

LIMIN

BYP

GND

LIMOUT

3.7

4.0

2.4

3.1

RFVCC

RFGND

700

330

RFVCC

RFGND

10k

330

10k

IFVCC

IFGND

IFVCC

IFGND

Oscillator.

PLL circuit GND.

Mixer output.

Output impedance is 330

PLL circuit power supply.

Limiter input.

Input impedance is 330

GND.

Limiter output.

--5--

CXA3067M

Symbol

Typical

Equivalent circuit

Description

No.

voltage (V)

DETIN

LP1

LP2

POUT

NOUT

IFVCC

IFGND

RFGND

5.0

4.2

4.1

(Hi)

0.22

(Low)

4.1

(Hi)

0.22

(Low)

5.0

21 IFVCC

32k

22 IFGND

IFVCC

IFGND

12p

IFVCC

IFGND

IFVCC

IFGND

Detector input.

Connect to a discriminator.

The capacitor is connected

between pins 17 and 18 for

the filter.

FSK data output.

Pins 19 and 20 are each

other reversal condition.

Power supply for limiter, detector,

data shaper circuit.

GND for limiter, detector,

data shaper circuit.

GND for RFamp, Mixer,

oscillator circuit.

--6--

CXA3067M

Symbol

Typical

Equivalent circuit

Description

No.

voltage (V)

RFIN

RFEM

MIXIN

RFVCC

REFSW

FSET3

FSET2

1.9

1.1

5.0

0.7

(OPEN)

2.5

(OPEN)

2.5

(OPEN)

RFVCC

MIX

233

RFGND

20k

DVCC

DGND

DVCC

DGND

20k

DVCC

DGND

RFamp input.

Gain adjustment.

Normally, by-pass capacitor is

connected at pin 25 to GND.

RFamp output and mixer input.

Power supply for RFamp, mixer,

oscillator circuit.

Reference frequency selection.

Decoupling capacitor is

connected at pin 28 to GND

when reference frequency is

7.15909 MHz or 14.31818 MHz

and pin 28 is connected to GND

directly when reference

frequency is 7.15625 MHz or

14.3125 MHz.

The pin of channel selection.

The condition of pin 29 has

3 states.

Connect to 5 V source for "Hi"

selection and connect to GND for

"Low" selection and leave open.

The pin of channel selection.

The condition of pin 30 has

3 states.

Connect to 5 V source for "Hi"

selection and connect to GND for

"Low" selection and leave open.

--7--

CXA3067M

Electrical Characteristics

See Electrical Characteristics Test Circuit (V

=5.0 V, Ta=+25 °C)

Item

Symbol

Pin No.

Circuit

Conditions

Min.

Typ.

Max.

Unit

No.

RFVCC

Current consumption

IFVCC

Current consumption

DVCC

Current consumption

Input sensitivity 1

Input sensitivity 2

Input level

Local OSC leakage

from RF input 1

Local OSC leakage

from RF input 2

RFamp bias current

RFamp voltage gain 1

RFamp voltage gain 2

RFamp voltage gain 3

RFamp input resistance

RFamp input capacitance

Mixer input resistance

Mixer input capacitance

Mixer voltage gain

RFamp+Mixer noise figure

RFI

IFI

Vi1

Vi2

Vil

LOleak1

LOleak2

Irf

Grf1

Grf2

Grf3

(rf)

(mix)

Gmix

rfmix

26, 27

RFV

V1=5 V

IFV

V2=5 V

V4=1 V

V3=5 V

Measurement on RFIN pin

SW1 : ON

RF=53.35 M to 169.5 MHz

Measurement on RFIN pin

SW1 : ON

RF=221.95 M to 302 MHz

RFV

V1=5 V

RF=53.35 M to 169.5 MHz

RF=221.95 M to 229.8 MHz

RF=302 MHz

I=4.8 mA, RF=100 MHz

Load Resistance=510

l=4.8 mA, RF=100 MHz

Load Resistance=510

RF=100 MHz

RF=108.5 MHz

IF=10.7 MHz

RF=108.5 MHz

IF=10.7 MHz

MOD

=10 kHz, f

DEV

=±75 kHz

Jitter is 1 % for f

MOD

Termination

RF=53.35 M to 169.5 MHz
f

MOD

=10 kHz, f

DEV

=±75 kHz

Jitter is 1 % for f

MOD

Termination

RF=221.95 M to 302 MHz
f

MOD

=10 kHz, f

DEV

=±75 kHz

Jitter is 1 % for f

MOD

Termination

RF=53.35 M to 302 MHz

6.7

3.5

dBmV

+10

dBmV

4.8

670

4.7

1.7

5.7

Note)

0 dBmV=1 mV, 0 dBµV=1 µV

)

Noise figure is uncorrected for image.

0 dBmV=60 dBµV

0 dBm=47 dBmV

--8--

CXA3067M

Item

Symbol

Pin No.

Circuit

Conditions

Min.

Typ.

Max.

Unit

No.

Mixer output resistance

Limiter input resistance

Limiter voltage gain

FSK Data

output voltage "H"

FSK Data

output voltage "L"

FSK Data output rise time

FSK Data output fall time

Oscillation frequency

VT output voltage range

Charge pump current

REFCLOCK input level 1

REFCLOCK input level 2

REFOSC loop gain

FSET1/2/3 "Hi" level

input voltage

FSET1/2/3 "Low" level

input voltage

FSET1/2/3 "Hi" level

input current

FSET1/2/3 "Low" level

input current

RDSW "Low" level

input voltage

RDSW "Low" level

input current

REFSW "Low" level

input voltage

(mix)

(lim)

Glim

OUTH

OUTL

OSC

Icp

CLK 1

CLK 2

Gref

FSETVH

FSETVL

FSETIH

FSETIL

RDVL

RDIL

REFVL

19, 20

7, 8

1, 2

3, 29, 30

IF=10.7 MHz

Load Capacitance=2 pF

Load Resistance=10 k

MOD

=10 kHz, f

DEV

=±75 kHz

Load Capacitance=2 pF

Load Resistance=10 k

MOD

=10 kHz, f

DEV

=±75 kHz

Load Capacitance=2 pF

Load Resistance=10 k

MOD

=10 kHz, f

DEV

=±75 kHz

Road Capacitance=2 pF

Road Resistance=10 k

MOD

=10 kHz, f

DEV

=±75 kHz

Source current

SW2 : OFF

SW3 : OFF

Sink current

SW2 : ON

SW3 : ON

Sin wave input

Square wave input

Vin2=14 MHz

FSET "Hi"=V5=5 V

FSET "Low"=V5=0 V

RDSW "L"=V6=0 V

222

332

442

222

332

442

3.8

4.1

0.22

0.6

nsec

315

MHz

0.3

2.5

±25

±50

±75

µA

0.3

0.4

3.0

Vp-p

0.3

0.4

3.0

Vp-p

3.8

0.4

120

250

380

µA

380

250

120

µA

0.4

122

µA

0.4

--9--

CXA3067M

Electrical Characteristics Test Circuit

V1
5V

V2
5V

V4
1V

V3
5V

I
N

I
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I
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I
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I
M

I
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I
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I
F

I
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I
F

.
7

Vin

SW1

Spectrum
analyzer

Passive
probe

Oscilloscope

10.8P
10M
10 : 1

SELECTION

680p

330

10n

SELECTION

fref

10n

I
X

I
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I
M

I
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I
M

I
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I
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I
F

I
N

51k

56p

5.6µ

Measurement circuit 1

Measurement circuit 2

Measurement : Input sensitivity, local osc leakage,

FSK DATA output voltage,

rise time, fall time

Measurement : Current consumption

--10--

CXA3067M

Vin1

Vout1

=Vout1/Vin1 (RFamp voltage gain)

=Vout2/Vin2 (REFOSC loop gain)

.
7

Vin2

Vout2

I
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I
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I
F

I
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I
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I
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I
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I
M

Vout1

.
7

Vin

=Vout2/Vout1

fref

3.3n

27k 30n

51k

100p

Vout2

10n

330

10n

I
N

I
X

I
M

I
N

I
M

I
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I
N

I
F

I
N

Measurement circuit 3

Measurement circuit 4

Wire

diameter

0.5

Coil

diameter

3.8

Number of

windings

1.5 T

6.5 T

Measurement : RFamp voltage gain

: REFOSC loop gain

Measurement : Mixer voltage gain

--11--

CXA3067M

Noise Source

Noise Figure meter

10n

fref

3.3n

27k 30n

51k

100p

10n

110p

40p

2.2µ

I
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I
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I
F

I
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.
7

I
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I
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I
M

I
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I
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.
7

=Vout/Vin

330

10n

Vin

Vout

I
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I
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I
F

I
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I
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I
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I
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I
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Measurement circuit 5

Measurement circuit 6

Wire

diameter

0.5

Coil

diameter

3.8

Number of

windings

1.5 T

6.5 T

Measurement : RFamp +Mixer NF

Measurement : Limiter voltage gain

--12--

CXA3067M

V1
5V

.
7

SW2

V4
4V

fref

14MHz

2.5V

V6
0V

V7
10V

SW3

51k

10n

I
X

I
N

I
F

I
N

I
X

I
M

I
N

I
M

100P

Measurement circuit 7

Measurement : Charge pump current

Wire

diameter

0.5

Coil

diameter

3.8

Number of

windings

6.5 T

--13--

CXA3067M

Function Explanation

The CXA3067M is an integrated circuit designed for CATV wide band FSK receiver. This monolithic IC is

composed of local oscillator, double balanced mixer, limiter, FM detector, data shaper and PLL circuit in a

single chip.

The function of each other section is described below.

1. RFamp circuit

This circuit amplifies RF signal, and RF signal is input to pin 24 (RFIN).

Since pin 27 is an open collector, connect power supply through a coil which composes tune circuit or a

choke coil or a resistor.

RF signal is selected a desired frequency by this tune circuit.

The desired frequency is input to mixer circuit through coupling capacitor.

2. Mixer circuit

This is a double-balanced mixer having small leakage of local signal.

The RF signal is converted to IF signal by the signal supplied from oscillator.

The output impedance is approximately 330

Normally, connect a ceramic filter to 10 pin (MIXOUT).

3. Local oscillator circuit

The balanced oscillator circuit with pins 7 and 8 (OSC1, OSC2).

Connect an LC resonance circuit comprising a varicap diode to pins 7 and 8.

4. PLL circuit

The PLL circuit fixes the local oscillator frequency to desired frequency.

It consists of the main divider, reference divider, phase comparator, charge pump, reference oscillator.

As stated in the accompanying document, desired frequency (channel) can be selected through the

combination of the conditions of pins 1, 29 and 30 (FSET 1; 2; 3).

As stated in the accompanying document, reference frequency can be selected through the combination

the conditions of pin 3 (RDSW) and pin 28 (REFSW).

5. Limiter circuit

This circuit amplifies the mixer IF output through ceramic filter.

For quadrature FM detection, this circuit amplifies IF signal by necessary level.

The input impedance is approximately 330

6. Detector circuit

For quadrature FM detection, the phase of limiter output (pin 15) is shifted 90° by discriminator as the

output is input to pin 16.

7. Data shaper

This circuit output performs the waveform shaping of the demodulated FSK signal and outputs the resulting

signal as a rectangular wave.

--14--

CXA3067M

Description of PLL Block

1. The followings "channel No." can be selected through the combination of the conditions of pins 1, 29 and 30

(FSET 1; 2; 3).

FSET conditions have 3 states (OPEN, Hi, Low).

Channel Selection

Channel No.

Local

OSC frequency

[MHz]

42.65

83.70

98.20

100.00

108.20

117.20

117.80

119.20

133.40

139.20

168.70

180.20

211.25

219.10

312.70

Receiving

frequency

[MHz]

53.55

73.00

87.50

89.30

97.50

106.50

128.50

108.50

122.70

128.50

158.00

169.50

221.95

229.80

302.00

FSET 1

OPEN

FSET 2

OPEN

FSET 3

OPEN

Note) OPEN : No connect

L : Connect to GND

H : Connect to V

--15--

CXA3067M

2. The followings Reference frequency can be selected through the combination the conditions of pin 3

(RDSW) and pin 28 (REFSW).

When the pin 28 is connected to GND directly, the pin 28 is state of DCGND.

When the pin 28 is connected to GND through decoupling capacitor, the pin 28 is state of ACGND.

Reference Frequency selection

f (ref)

7.15625 MHz

7.15909 MHz

14.3125 MHz

14.31818 MHz

RDSW

OPEN

GND

REFSW

DCGND

ACGND

DCGND

ACGND

Note

) Connect to GND directly.

Note

) Connect to GND through decoupling capacitor

REFSW

--16--

CXA3067M

3. The comparison frequency is 25.021853 kHz at reference frequency 7.15625 MHz/14.3125 MHz, and

25.031783 kHz at reference frequency 7.15909 MHz/14.31818 MHz.

The frequency division ratio of the reference divider is 286.

The frequency division ratio of the scaler is 1 or 2;

When the reference frequency is 7.15625 MHz/7.15909 MHz, the frequency division ratio of the scaler is 1.

When the reference frequency is 14.3125 MHz/14.31818 MHz, the frequency division ratio of the scaler is 2.

Reference frequency=7.15625 MHz

The comparison frequency=7.15625/286=25.021853 kHz

Reference frequency=7.15909 MHz

The comparison frequency=7.15909/286=25.031783 kHz

fOSC [MHz]

42.65

83.7

98.2

100

108.2

117.2

117.8

119.2

133.4

139.2

168.7

180.2

211.25

219.1

312.7

Divider

1705

3345

3925

3997

4324

4684

4708

4764

5331

5563

6742

7202

8443

8756

12497

8192

4096

2048

1024

512

256

128

fOSC [MHz]

42.65

83.7

98.2

100

108.2

117.2

117.8

119.2

133.4

139.2

168.7

180.2

211.25

219.1

312.7

Divider

1704

3344

3923

3995

4323

4682

4706

4762

5329

5561

6739

7199

8439

8753

12492

8192

4096

2048

1024

512

256

128

--17--

CXA3067M

Notes on Application

Take care of the followings because the CXA3067M has limiter voltage gain of approximately 67 dB and uses

high frequency.

1) Separate the input pattern from the output pattern as far as possible and makes wiring short.

2) Ground the decoupling capacitor as close to pin 13 as possible.

Take care of the followings in order to reduce the jitter.

1) Insert the capacitor as close to pin 17 and 18 as possible.

2) Ground the by-pass capacitor as close to IFV

to supply pin 16 as possible.

Take care of the following, for the purpose of the isolation of local oscillator resonance circuit and X'tal (RFF

CLOCK).

1) Separate the patterns connected pin 1 and pin 2 from the local oscillator resonance circuit.

Take care of the following, in order to reduce the phase noise.

1) Connect the loop filter as close to pins 5 and 6 as possible.

Take care of the following, in order to prevent the parasitic oscillation.

1) Connect the local oscillator resonance circuit as close to pins 7 and 8 as possible.

And compact the local oscillator resonance circuit.

The tuning voltage at the local oscillator resonance circuit.

The output voltage at pin 6 is 0.3 V to V

When the oscillation frequency is the desired frequency, please the output voltage at pin 6 should be been 2.5 V.

Please decide the component value of loop filter by each system.

DVCC

10k

100

DGND

--18--

CXA3067M

Application

.
6

FIN

MIX

LIM

I
O

I
R

I
T

(
+

)

I
N

I
X

I
S

I
M

I
N

.
7

'
t
a

I
N

I
O

I
L

.
7

I
L

l
e

r
e

f
e

r

t
o

t
h

r

s

t
s

i
t
h

f
o

l
l
o

i
n

i
r
c

i
t
s

)

T

i
r
c

i
t

o

f

R

)

L

l

o

r
e

i
r
c

i
t

)

L

f
i
l
t
e

4.7

MIX

TIN

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility fo

any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same

fref

7.15625 MHz

7.15909 MHz

14.3125 MHz

14.31818 MHz

RDSW

OPEN

GND

REFSW

DCGND

ACGND

DCGND

ACGND

--19--

CXA3067M

The component value of the tune circuit, local oscillator resonance circuit and loop filter.

Channel

Tune circuit

Local oscillator

Loop filter

No.

of RFamp

resonance circuit

510

330p

0.5
2.5T

Wire

diameter

Number of

windings

Coil

diameter

510

180p

0.5
2.5T

510

120p

0.5
2.5T

510

120p

0.5
2.5T

510

82p

0.5
2.5T

510

150p

0.5
1.5T

510

100p

0.5
1.5T

510

120p

0.5
1.5T

51p

1T362

0.5
20.5T

82p

0.5 11.5T 3.8

100p

0.5 8.5T 3.8

100p

0.5 8.5T 3.8

100p

0.5 8.5T 3.8

100p

0.5 6.5T 3.8

100p

0.5 6.5T 3.8

100p

0.5 6.5T 3.8

3.3n

39n

24k

3.3n

30n

27k

3.3n

30n

27k

3.3n

30n

27k

3.3n

30n

27k

3.3n

30n

27k

3.3n

30n

27k

3.3n

30n

27k

--21--

CXA3067M

i
n

(
d

)

Frequency response RF amp voltage gain

Reception Frequency (MHz)

i
m

i
t
e

r

g

i
n

(
d

)

Frequency response limiter voltage gain

Intermediate Frequency (MHz)

l
e

l

(
d

)

Local oscillation leakage at RFIN pin

Local oscillation frequency (MHz)

t
p

t

L

l

(
V

)

S curve response

Intermediate Frequency (MHz)

r
r
e

t

c

t
i
o

(
m

)

Supply voltage vs. Current consumtion

Supply voltage (V)

RF BLOCK

PLL BLOCK

IF BLOCK

4.6

4.7

4.8

4.9

5.1

5.2

5.3

5.4

100

300

100

1000

4.32

4.31

4.3

4.29

4.28

4.27

4.26

10.6

10.65

10.7

10.75

10.8

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