--1--

E99904-TE

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Absolute Maximum Ratings (Ta=25 °C)

· Supply voltage

0.3 to +5.5

· Storage temperature

Tstg

55 to +150

°C

· Allowable power dissipation

730

(when mounted on a substrate)

Operating Conditions

· Supply voltage

4.75 to 5.30

· Operating temperature

Topr

25 to +75

°C

Description

The CXA3108AQ is a monolithic IC that down-

converts the L-band (1 to 2 GHz) 1st IF to 2nd IF for

satellite broadcast receivers. It integrates a local

oscillator circuit, double-balanced mixer, IF AGC

amplifier and tuning PLL onto a single chip.

This IC supports both analog and digital satellite

broadcasts, and achieves reduction in the number of

tuner components and smaller size.

Features

· On-chip tuning PLL

· Supports 2.65 GHz oscillator frequency

· Noise figure: 12.5 dB typ. (for IF full gain)

· IF AGC gain variation: 46 dB typ.

· Wide band IF AGC amplifier (60 to 500 MHz)

· Two IF outputs

· PLL supports I

C protocol

· On-chip high voltage drive transistor for charge

pump

Applications

· Analog satellite broadcast tuners (BS/CS)

· Digital satellite broadcast tuners (DSS/DVB, etc.)

Structure

Bipolar silicon monolithic IC

L-band Down Converter IC with On-Chip PLL

40 pin QFP (Plastic)

CXA3108AQ

Notes on Handling
This IC has a weak electrostatic discharge strength. Take care when handling the IC.

--2--

CXA3108AQ

Block Diagram and Pin Configuration

Receiver

Divider
11bit

Phase
Detector

Shift
Register

Lock
Det

Charge
Pump

Buffer

Divider
17 bit

Prescaler
1/2, 1/1

STSW

Buffer

OSC

MIX

IF AGC
AMP

IF V

SAW
Driver

OUTPUT SW

XTAL

DGND1

BUSSW

PS1

PS2

PS3

PS4

GND

IFOUT2

I
F

I
N

I
F

EXTIN2

EXTIN1

DGND2

GND

OSCB2

OSCE2

OSCE1

OSCB1

RFV

BIAS

REF

OSC

Output Port
Driver

--3--

CXA3108AQ

Pin Description

Symbol

Pin voltage

Equivalent circuit

Description

No.

[V]

IFOUT1

IFOUT2

IFGND2

IFSW

IFV

IFAGC

RFIN1

RFIN2

IFGND1

RFGND

2.5

(IFSW 0 V)

4.7

(IFSW 5 V)

4.7

(IFSW 0 V)

2.5

(IFSW 5 V)

0 or 5

0 to 4

1.7

IF outputs.

IF output circuit GND.

Selects whether IF output is

Pin 1 or Pin 40.

When this pin is connected to

GND, the IF signal is output

from Pin 1; when connected to

, the IF signal is output from

Pin 40.

IF output circuit power supply.

IF amplifier circuit power supply.

AGC signal input.

RF inputs.

IF amplifier circuit GND.

RF block GND.

IFV

30k

100k

IFV

40k

--4--

CXA3108AQ

Symbol

Pin voltage

Equivalent circuit

Description

No.

[V]

BIAS

RFV

OSCB1

OSCE1

OSCE2

OSCB2

GND

DGND2

EXTIN1

EXTIN2

CPO

1.8

2.2

1.5

2.2

2.5

Oscillator circuit current

adjustment.

Connect this pin to GND via a

capacitor.

RF block power supply.

Oscillator pins.

GND.

Charge pump GND.

PLL external inputs.

NPN transistor output for

varicap diode drive.

Charge pump output.

Connect a loop filter.

RFV

200

2.5k

20k

25k

200

500

20k

--5--

CXA3108AQ

Symbol

Pin voltage

Equivalent circuit

Description

No.

[V]

STSW

LOCK

ADC

SDA

5.0

(LOCK)

0.2

(UNLOCK)

Selects either the internal

oscillator circuit or external input

for input to PLL.

When this pin is open or

connected to V

, the internal

oscillator circuit is selected;

when connected to GND,

external input is selected.

Charge pump power supply.

LOCK detection.

High when locked, Low when

unlocked.

ADC input.

DATA input.

20k

2.5k

40k

--8--

CXA3108AQ

Electrical Characteristics

=5 V, Ta=25 °C)

Circuit Current

Item

Circuit current A

Circuit current D

Symbol

Measurement conditions

Analog circuit current

Sum of RFV

, IFV

1 and IFV

2 currents

PLL circuit current

Sum of DV

1 and DV

2 currents

Min.

Typ.

Max.

Unit

Item

Conversion gain

Noise figure

IFAGC gain variation

range

IF maximum output

RF pin local oscillator

leak

IF pin local oscillator

leak

Tertiary intermodulation

distortion

Local oscillator phase

noise

RF input impedance

Symbol

CG1

CG2

CG3

NF1

NF2

NF3

AGC

PoSAT

RFLK1

RFLK2

RFLK3

IFLK1

IFLK2

IFLK3

IM3

CN1

CN2

Measurement conditions

fin=950 MHz, f

=480 MHz

IFAGC=4 V (Full Gain)

fin=1450 MHz, f

=480 MHz

IFAGC=4 V (Full Gain)

fin=2150 MHz, f

=480 MHz

IFAGC=4 V (Full Gain)

fin=950 MHz, f

=480 MHz

IFAGC=4 V (Full Gain)

fin=1450 MHz, f

=480 MHz

IFAGC=4 V (Full Gain)

fin=2150 MHz, f

=480 MHz

IFAGC=4 V (Full Gain)

=480 MHz,

load saturated output

OSC

=1430 to 1830 MHz

OSC

=1830 to 2230 MHz

OSC

=2230 to 2630 MHz

OSC

=1430 to 1830 MHz

OSC

=1830 to 2230 MHz

OSC

=2230 to 2630 MHz

Pin=25 dBm

IFAGC=4 V (Full Gain)

fin=935 MHz, 940 MHz

fout=475 MHz, 480 MHz

S/I of 480 MHz and 475 MHz

OSC

=1430 MHz

10 kHz offset

OSC

=1430 MHz

100 kHz offset

f=950 MHz

Min.

Typ.

Max.

Unit

dBm

dBc/Hz

100

dBc/Hz

12.9

1.84

OSC/MIX/IF Amplifier Blocks

--9--

CXA3108AQ

PLL Block

Item

External local input level

SDA, SCL

High level input voltage

Low level input voltage

High level input current

Low level input current

SDA Low output voltage

Clock input hysteresis

CPO (charge pump)

Output current 1

Output current 2

ADC

Input current

LOCK

High output voltage

Low output voltage

REFOSC

Oscillator frequency range

Input capacitance

Drive level

PS1 to PS4

Pull-in current

Leak current

Symbol

EXT

SDA

HYS

CPO1

CPO2

ADC

LKH

LKL

XTOSC

Sink

Leak

Measurement conditions

=GND

Sink current=3 mA

Byte 4/bit 6=0 and for 3WB

Byte 4/bit 6

Input voltage=5 V

Load resistance 10 k

, for LOCK

Load resistance 10 k

, for UNLOCK

When ON

When OFF

Min.

Typ.

Max.

Unit

dBm

GND

1.5

0.1

µA

0.4

0.25

0.4

0.65

±35

±50

±75

µA

±125

±180

±270

µA

0.2

µA

0.5

MHz

200

Bus Timing

Item

C Bus

SCL clock frequency

Start waiting time

Start hold time

Low hold time

High hold time

Start setup time

Data hold time

Data setup time

Rise time

Fall time

Stop setup time

Symbol

SCL

WSTA

HSTA

LOW

HIGH

SSTA

HDAT

SDAT

SSTO

Measurement conditions

Min.

Typ.

Max.

Unit

400

kHz

1300

600

1300

600

1300

600

300

600

--10--

CXA3108AQ

Electrical Characteristics Measurement Circuit

I
F

I
N

I
A

I
F

t
2

I
F

t
1

I
N

.
1

.
2

Cin

--11--

CXA3108AQ

Description of Functions

The CXA3108AQ is a tuner IC for satellite broadcast receivers. It converts the RF signal down-converted to

1st IF (1 to 2 GHz) at the LNB to 2nd IF, so that only the desired reception frequency is selected and

detected.

This IC combines the mixer, local oscillator and IF amplifier (variable gain) circuits required for frequency

conversion to 2nd IF, and the PLL circuit which controls the local oscillator frequency onto a single chip.

The function of each block is described below.

1. Mixer Circuit

This circuit outputs the frequency difference between the signal input to RF IN and the local oscillator

signal. A double-balanced mixer with minimal local oscillator signal leak is used. RF input is equivalent to a

differential amplifier with emitter grounding.

2. Local Oscillator Circuit

A Colpitts oscillator with differential operation is used for the oscillator circuit, so it is stable relative to

supply voltage fluctuation, and undesired radiation is suppressed. This circuit also contains a capacitor

which is part of the resonance circuit, so there is minimal parasitic oscillation and design of external circuits

is easier.

3. IF Amplifier Circuit

This circuit amplifies the mixer IF output, and is comprised of an AGC amplifier stage and low impedance

output stage.

The gain can be varied by the AGC pin voltage (range 0 to 4 V) at the AGC amplifier stage. The maximum

gain is approximately 20 dB (voltage gain between RF IN and IF OUT), and the gain variation width is 30

dB or more.

The output stage has two unbalanced outputs, and can directly connect two SAW filters with different pass

bandwidths. Output pin selection is determined by the IF SW pin voltage.

The IF amplifier circuit is a wide band amplifier circuit, and can be used in the IF frequency range of 60 to

500 MHz.

4. PLL Circuit-1 (normal operation: when the STSW pin is open or connected to V

)

The PLL circuit fixes the local oscillator frequency to the desired frequency. It consists of the prescaler,

main divider, reference divider, phase comparator, charge pump and reference oscillator. The control

format supports the I

C bus protocol.

When the power (DV

1) is turned on, the power-on reset circuit activates and the frequency division data

and control data are all initialized to 0. The power-on reset threshold is 3 V at normal temperature (Ta=25

°C).

5. PLL Circuit-2 (external input PLL operation: when the STSW pin is connected to GND)

When the STSW pin is connected to GND, the PLL enters independent operation mode where the PLL only

is used with the oscillator signal input from the external signal input pin.

--12--

CXA3108AQ

Description of PLL Block

1. Programming

1-1. The main divider frequency division ratio is obtained according to the following formulas.

fosc = fref

(16M + S) or fosc = fref

(16M + S) (when PE = 1)

fosc : local oscillator frequency

fref : comparison frequency

: prescaler fixed frequency division ratio (when PE = 1)

: main divider frequency division ratio

: swallow counter frequency division ratio

The variable frequency division ranges of M and S are as follows.

4095

During PLL independent operation (STSW = GND), the prescaler halving frequency division cannot be

added.

1-2. I

C Bus

This IC conforms to the standard I

C bus format, and bidirectional bus control is possible consisting of a

write mode in which various data are received and a read mode in which various data are sent.

Write and read modes are recognized according to the setting of the final bit (R/W bit) of the address

byte. Write mode is set when the R/W bit is "0", and read mode is set when the R/W bit is "1".

1-2-1. Address Setting

The responding address can be changed by the ADSW pin voltage to allow more than one PLL in a

system.

<Table 1> Address

MA1

MA0

ADSW pin voltage

0 to 0.1 V

OPEN

0.4 V

to 0.6 V

0.9 V

to V

--13--

CXA3108AQ

MODE

Address byte

Status byte

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

MA1

MA0

1-2-2. Data format

Write mode is used to receive various data. In this mode, byte 1 contains the address data, bytes 2 and

3 contain the frequency data, and bytes 4 and 5 contain the various control data.

These data are latch transferred in the manner of byte 1, byte 2 + byte 3, byte 4, and byte 5. When the

correct address is received, the data is recognized as frequency data if the first bit of the next byte is

"0", and as control data if this bit is "1".

Also, when data transmission is stopped part-way, the previously programmed data is valid. Therefore,

once the control data has been programmed, 3-byte commands consisting of the address and

frequency data are possible.

Further, even if the I

C bus stop conditions are not met, data can be input by sending the start

conditions and the new address.

In read mode, the power-on reset operation status, phase comparator locked/unlocked status and 5-

value A/D converter input pin voltage status are transmitted to the master.

Power-on reset is set to "1" when the supply voltage (DV

1) power supply is cut off.

If DV

1 is 3 V or higher and the status is output in the read mode, this bit is reset to "0".

Write mode: slave receiver

Read mode: slave transmitter

MODE

Address byte

Divider byte 1

Divider byte 2

Control byte 1

Control byte 2

MSB

LSB

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

MA1

MA0

M10

M12

M11

--14--

CXA3108AQ

<Table 3> Reference Divider Frequency Division Ratio

Frequency division ratio

128

256

160

320

ADC pin voltage

0 to 0.15V

0.15 V

to 0.3 V

0.3 V

to 0.45 V

0.45 V

to 0.6 V

0.6 V

to V

P1 to P4

port control

M0 to M12 :

main divider frequency division ratio setting

S0 to S3

swallow counter frequency division ratio setting

varicap output OFF (when "1")

charge pump current switching

prescaler halving frequency division added (when "1")

power-on reset

lock detection signal

A0 to A2

5-value ADC data (ADC pin voltage conversion: Table 2)

R0 to R3

reference divider frequency division ratio selection (Table 3)

<Table 2> ADC Conversion Table

--16--

CXA3108AQ

Current consumption characteristics

-

C

r
r
e

t

c

t
i
o

[
m

]

Supply voltage [V]

100

4.6

4.7

4.8

4.9

5.1

5.2

5.3

5.4

Conversion gain

IF=480MHz, AGC=4V

-

C

r
s

i
o

i
n

[
d

]

RF input frequency [GHz]

0.8

1.2

1.4

1.8

2.2

1.6

NF characteristics IF=480 MHz, AGC=4V

Untuned input, DSB display

-

N

i
s

f
i
g

r
e

[
d

]

RF input frequency [GHz]

0.8

1.2

1.4

1.8

2.2

1.6

IFOUT

Example of Representative Characteristics

--17--

CXA3108AQ

I
F

t
p

t

l
e

l

[
d

]

RF input level [dBm] (935MHz, 940MHz)

RF pin local oscillator leak characteristics

i
n

l
o

l

o

i
l
l
a

t
o

r

l
e

[
d

]

OSC

- Local oscillator frequency [GHz]

1.4

1.6

1.8

2.4

2.6

2.8

2.2

IFOUT pin local oscillator leak characteristics

AGC=4V

I
F

i
n

l
o

l

o

i
l
l
a

t
o

r

l
e

[
d

]

OSC

- Local oscillator frequency [GHz]

1.4

1.6

1.8

2.4

2.6

2.8

2.2

Fundamental wave (480MHz)

Tertiary intermodulation
distortion component (470MHz)

Input/output characteristics (untuned input, AGC=4V)

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA3108AQ