1
CXA3117AN
E97220A8Z
IF Amplifier for M-ary FSK Pagers
Description
The CXA3117AN is a low current consumption FM
IF amplifier which employs the newest bipolar
process. It is suitable for M-ary FSK pagers.
Features
Low current consumption: 1.1mA
(typ. at V
CC
= 1.4V)
Low voltage operation: V
CC
= 1.1 to 4.0V
Small package 24-pin SSOP
Second mixer and oscillator
Needless of IF decoupling capacitor
Reference power supply for operational amplifier
and comparator
Bit rate filter with variable cut-off
Misoperation prevention function for continuous data
RSSI function
IF input, V
CC
standard
Quick charge by the detector output sense method
Applications
M-ary FSK pagers
Double conversion pagers
Block Diagram and Pin Configuration
Structure
Bipolar silicon monolithic IC
Absolute Maximum Ratings
Supply voltage
V
CC
7.0
V
Operating temperature
Topr
20 to +75 C
Storage temperature
Tstg 65 to +150 C
Allowable power dissipation P
D
417
mW
Operating Condition
Supply voltage
V
CC
1.1 to 4.0
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
24 pin SSOP (Plastic)
MIX IN
GND
REG OUT
REG CONT
LVA OUT
NRZ OUT
CHARGE
B.S.
AUDIO
L.C. OUT
CHG OFF
RSSI
OSC IN
OSC OUT
MIX OUT
V
CC
IF IN
TH CONT
FSK REF
QUAD
C1
C2
C3
FIL SW
OSC
IF_LIM
FILTER
MIX
QUAD_DET
LEVEL
COMP
REG
RSSI
CHARGE
GND
LVA
13
14
15
16
17
18
19
20
21
22
23
24
2
3
4
5
6
7
8
9
10
11
12
1
2
CXA3117AN
Pin Description
Pin
No.
1
1.4V
0.7V
1.3V
1.4V
--
0.2V
OSC IN
Connects the external parts of crystal
oscillator circuit.
A capacitor and crystal oscillator are
connected to these pins and V
CC
.
Mixer output.
Connect a 455kHz ceramic filter
between this pin and IF IN.
IF limiter amplifier input.
Determines the level comparator
threshold value.
Threshold value can be adjusted by
inserting the resistor between Pin 6 and
V
CC
.
Normally, short to V
CC
.
Connects the capacitor that determines
the low cut-off frequency for the entire
system.
Power supply.
OSC OUT
MIX OUT
V
CC
IF IN
TH CONT
FSK REF
2
3
4
5
6
7
Symbol
Pin
voltage
Equivalent circuit
Description
2
1
GND
V
CC
300
15k
15k
72
GND
V
CC
3
1.5k
GND
V
CC
20k
5
1.5k
1.5k
20k
GND
V
CC
6
25k
GND
V
CC
72
7
3
CXA3117AN
Pin
No.
8
1.4V
QUAD
9
10
11
0.2V
C1
C2
C3
12
--
FIL SW
13
0.1V
RSSI
14
--
CHG OFF
Connects the phase shifter of FM
detector circuit.
Connects the capacitor that determines
the LPF cut-off.
Switches the LPF cut-off.
Cut-off is decreased by setting this pin
high.
(Applied voltage range: 0.5V to +7.0V)
RSSI circuit output.
Sets off the quick charge circuit
current. The charge current is off by
setting Pin 18 low and Pin 14 high.
Symbol
Pin
voltage
Equivalent circuit
Description
8
GND
V
CC
22k
20k
20p
GND
V
CC
9
10
11
35k
50k
GND
140k
20k
72
12
GND
V
CC
7k
7k
13
70k
GND
100k
20k
72
14
4
CXA3117AN
Pin
No.
15
19
20
--
--
--
L.C. OUT
NRZ OUT
LVA OUT
Level comparator, NRZ comparator
and LVA comparator outputs. They are
open collectors.
(Applied voltage range: 0.5V to +7.0V)
18
--
CHARGE
Controls the speed of the quick charge
circuit. Set this pin high to execute the
quick charge.
(Applied voltage range: 0.5V to +7.0V)
21
--
REG
CONT
Output for internal constant-voltage
source amplifier. Connect the base of
PNP transistor.
(Current capacity: 100A)
22
1.0V
REG OUT
Constant-voltage source output.
Controlled to maintain 1.0V.
23
--
GND
Ground
17
--
B.S.
Controls the battery saving.
Setting this pin low suspends the
operation of IC.
(Applied voltage range: 0.5V to +7.0V)
Symbol
Pin
voltage
Equivalent circuit
Description
GND
72
15
19
20
GND
140k
20k
72
17
16
0.2V
AUDIO
Level comparator and NRZ comparator
inputs. The filter circuit output is
connected.
GND
V
CC
72
16
72
GND
100k
20k
18
GND
V
CC
72
21
GND
V
CC
78k
22
22k
1k
5
CXA3117AN
Pin
No.
24
1.4V
MIX IN
Mixer input.
Symbol
Pin
voltage
Equivalent circuit
Description
GND
V
CC
4.16k
2k
4.16k
24
Electrical Characteristics
(V
CC
= 1.4V, Ta = 25C, Fs = 21.7MHz, F
MOD
= 1.6kHz, F
DEV
= 4.8kHz, AM
MOD
= 30%)
Item
Current consumption
Current consumption
AM rejection ratio
NRZ output saturation voltage
NRZ output leak current
NRZ hysteresis width
VB output current
VB output saturation voltage
REG OUT voltage
LVA operating voltage
LVA output leak current
LVA output saturation voltage
Detector output voltage
Logic input voltage high level
Logic input voltage low level
Limiting sensitivity
Detector output level ratio
deviation to level comparator
window width
Level comparator output
saturation voltage
Level comparator output leak
current
RSSI output offset
Mixer input resistance
Mixer output resistance
IF limiter input resistance
I
CC
I
CCS
AMRR
V
SATNRZ
I
LNRZ
V
TWNRZ
I
OUT
V
SATVB
V
REG
V
LVA
I
LLVA
V
SATLVA
V
ODET
V
THBSV
V
TLBSV
V
IN (LIM)
V
LCWR
V
SATLC
I
LLC
V
ORSSI
R
INLIM
R
OUTMIX
R
INLIM
Measurement circuit 1, V2 = 1.0V
Measurement circuit 1, V2 = 0V
Measurement circuit 2, 30k LPF
Measurement circuit 4, Vin = 0.3V
Measurement circuit 3, Vin = 0.1V
Measurement circuit 3,
Vin = 0.1 to 0.3V
Measurement circuit 5
Measurement circuit 5
Output current 0A
Measurement circuit 6,
V1 = 1.4 to 1.0V
Measurement circuit 6, V1 = 1.0V
Measurement circuit 7
Measurement circuit 2
--
--
Measurement circuit 2,
Data filter fc = 2.4kHz
When Pin 6 is shorted to Vcc
Measurement circuit 9
Measurement circuit 8
Measurement circuit 10
--
--
--
0.7
--
25
--
--
0
100
--
0.95
1.05
--
--
50
0.9
--
--
15
--
--
--
1.6
1.2
1.2
1.1
6
--
--
--
10
--
--
1.00
1.10
--
--
63
--
--
108
0
--
--
150
2.0
1.5
1.5
1.35
10
--
0.4
5.0
20
--
0.4
1.05
1.15
5.0
0.4
80
--
0.35
--
+15
0.4
5.0
300
2.4
1.8
1.8
mA
A
dB
V
A
mV
A
V
V
V
A
V
mVrms
V
V
dBm
%
V
A
mV
k
k
k
Symbol
Conditions
Min.
Typ.
Max.
Unit
6
CXA3117AN
V2
V1
1.4V
2
3
4
5
6
7
9
10
11
12
1
13
14
15
16
17
18
20
21
22
23
24
V
CC
8
19
1000p
1.8
10p to
120p
Vin
V2
1V
1200p
1
2
0
0
p
8.2k
1
2
0
0
p
1
V1
1.4V
22p
2
3
4
5
6
7
8
9
10
11 12
1
13
14
15
16
17
18
19
20
21
22
23
24
15p
V
CC
Measurement circuit 1
Measurement circuit 2
V2
1V
V1
1.4V
2
3
4
5
6
7
9
10
11
12
1
13
14
15
16
17
18
20
21
22
23
24
V
CC
Vin
8
19
100k
V2
1V
V1
1.4V
2
3
4
5
6
7
9
10
11
12
1
13
14
15
16
17
18
20
21
22
23
24
V
CC
Vin
8
19
50A
Measurement circuit 3
Measurement circuit 4
Electrical Characteristics Measurement Circuit
7
CXA3117AN
V3
0.5V
V2
1V
V1
1.4V
2
3
4
5
6
7
9
10
11
12
1
13
14
15
16
17
18
22
23
24
V
CC
19
100A
20
8
GND
GND
21
V2
1V
V1
1.4 to 1.0V
2
3
4
5
6
7
9
10
11
12
1
13
14
15
16
17
18
21
22
23
24
V
CC
19
100k
20
8
Measurement circuit 5
Measurement circuit 6
V2
1V
V1
1.4V
2
3
4
5
6
7
9
10
11 12
1
13
14
15
16
17
18
21
22
23
24
V
CC
19
50A
20
8
Vin
0.2V
V2
1V
V1
1.4V
2
3
4
5
6
7
9
10
11 12
1
13
14
16
17
18
21
22
23
24
V
CC
19
20
8
15
100k
Measurement circuit 7
Measurement circuit 8
Vin
0.1V
V2
1V
V1
1.4V
2
3
4
5
6
7
9
10
11 12
1
13
14
16
17
18
21
22
23
24
V
CC
19
20
8
15
50A
V2
1V
V1
1.4V
2
3
4
5
6
7
9
10
11 12
1
14
15
16
17
18
20
21
22
23
24
V
CC
8
19
13
100P
Measurement circuit 9
Measurement circuit 10
8
CXA3117AN
O
S
C
I
F
_
L
I
M
F
I
L
T
E
R
M
I
X
Q
U
A
D
_
D
E
T
L
E
V
E
L
C
O
M
P
R
E
G
R
S
S
I
C
H
A
R
G
E
G
N
D
L
V
A
V
B
_
R
E
G
N
R
Z
_
C
O
M
P
C
H
A
R
G
E
B
S
A
U
D
I
O
L
.
C
.
O
U
T
C
H
G
_
O
F
F
F
I
L
_
S
W
V
C
C
G
N
D
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
AU
DIO
RS
SI
LE
VE
L
NR
Z
LV
A
RE
G
G
N
D
G
N
D
C
1
1
0
p
t
o
1
2
0
p
L
1
1
.
8
H
C
3
1
0
0
0
p
G
N
D
C
6
1
0
G
N
D
P
N
P
R
4
2
2
0
C
9
0
.
0
1
G
N
D
R
5
1
0
0
k
R
6
1
0
0
k
G
N
D
G
N
D
G
N
D
S
4
S
3
R
8
1
0
0
k
S
2
G
N
D
C
1
4
1
0
0
p
G
N
D
S
1
C
1
3
1
4
2
0
p
(
1
2
0
0
p
+
2
2
0
p
)
R
7
6
.
8
k
G
N
D
C
1
2
6
8
0
p
C
1
1
1
1
0
0
p
(
1
0
0
p
+
1
0
0
0
p
)
G
N
D
D
I
S
C
G
N
D
C
1
0
1
C
E
R
A
F
I
L
C
8
0
.
0
1
C
7
1
0
G
N
D
C
5
1
5
p
C
4
2
2
p
X
T
A
L
R
F
S
M
A
Application circuit
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility fo
r
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same
.
9
CXA3117AN
Application Note
1) Power Supply
The CXA3117AN, with the built-in regulator, is designed to permit stable operation at the wide range of
supply voltage from 1.1 to 4.0V. Decouple the wiring to V
CC
(Pin 4) as close to the pin as possible.
2) Oscillator Input
Oscillator input method
a) Using Pins 1 and 2, input self-excited oscillation signal through the composition of a Colpitts type crystal
oscillator circuit. Connect the capacitors attached to the crystal and Pin 2 to V
CC
.
b) Directly input a local oscillation signal to Pin 1.
2
3
1
V
CC
Ceramic
filter
2
3
1
From
local signal
Ceramic
filter
Fig. 1
3) Mixer
The mixer is of double-balance type. Pin 24 is the input pin. Input though a suitable matching circuit. The
input impedance is 2.0k
.
Pin 3 serves as the output pin for the mixer, and a load resistance of 1.5k
is incorporated.
4) IF Filter
The filter to be connected between this mixer output and the IF limiter amplifier input should have the
following specifications. Connect the ground pin of the IF filter to V
CC
.
I/O impedance : 1.5k
10%
Bandwidth
: Changes according to applications.
5) IF Limiter Amplifier
The gain of this IF limiter amplifier is approximately 100dB. Take notice of the following points in making
connection to the IF limiter amplifier input pin (Pin 5).
a) Wiring to the IF limiter amplifier input (Pin 5) should be as short as possible.
b) As the IF limiter amplifier output appears at QUAD (Pin 8), wiring to the ceramic discriminator connected
to QUAD should be as short as possible to reduce the interference with the mixer output and IF limiter
amplifier input.
V
CC
Wire as short and apart as possible
As short as possible
3
4
5
6
7
8
9
Fig. 2
10
CXA3117AN
6) Quick Charge
In order to hasten the rising time from when power is turned on, the CXA3117AN features a quick charge
circuit. Therefore, the quick charge circuit eliminates the need to insert a capacitor between the detector
output and the LPF as is the case with conventional ICs, but a capacitor should be connected to Pin 7 to
determine the average signal level during steady-state reception. The capacitance value connected to Pin
7 should be chosen such that the voltage does not vary much due to discharge during battery saving.
Connect a signal for controlling the quick charge circuit to Pin 18. Setting this pin high enables the quick
charge mode, and setting this pin low enables the steady-state reception mode. Quick charge is used when
the power supply is turned on. The battery saving must be set high at the time.
Connect Pin 18 to GND when quick charge is not being used.
Power supply to the IC
(Pin 4)
Quick charge
(Pin 18)
Battery saving control
(Pin 17)
A
5ms
T2
T1
T3
T4
A
A
1ms
1ms
Fig. 3
Example when the Pin 7 REF capacitance value is 1F
T1 in Fig. 3: 2-level data setting time after quick charge
When the input frequency offset is within 4.8kHz: 0ms
T2 in Fig. 3: 4-level data setting time after quick charge
When the input frequency offset is within 1.6kHz or less: 0ms
When the input frequency offset is within 3kHz or less: 500ms or less
T3 in Fig. 3: 4-level data is obtained
T4 in Fig. 3: 2-level data is obtained
11
CXA3117AN
7) Detector
The detector is of quadrature type. To perform phase shift, connect a ceramic discriminator to Pin 8.
The phase shifting capacitor for the quadrature detector is incorporated. The FM (FSK) signal demodulated
with the detector is output to AUDIO (Pin 16) through the internal primary LPF.
The AUDIO output is the anti-phase output to the NRZ OUT.
The CDBM455C50 (MURATA MFG. CO., LTD.) ceramic discriminator is recommended for the CXA3117AN.
For the 2-level system, the CDBM455C28 can also be used.
6.8k
7
8
9
V
CC
Ceramic
discriminator
CDBM455C50
Fig. 4
The detector output level is changed according to the resistance value connected to Pin 8.
8) Filter Buffer, Level Comparator and NRZ Comparator
The LPF circuit is built in this IC.
The LPF output is connected internally to the NRZ comparator, level comparator and quick charge circuit.
0.2V
15
16
19
7
L. C.
LPF
DET
Using the LPF, remove noise from the demodulated signal and input the signal to the above three circuits.
Fig. 5
12
CXA3117AN
8)-1. LPF Constant
The data filter cut-off (fc) is expressed with the following equation.
fc
1
=
fc
2
=
, Q =
C
11
to C
13
: External capacitance (Pin 9 to Pin 11)
R: IC internal resistance
R is approximately 55k
20% when Pin 12 is low. The table below shows the example of constants to
data rate.
2
C
11
R
1
Pin 12 filter switch
H
L
H
L
H
L
H
L
--
430
950
1900
1000
2000
1000
2000
--
512bps (2 levels)
1200bps (2 levels)
2400bps (2 levels)
1600bps (2 levels)
3200bps (2 levels)
3200bps (4 levels)
6400bps (4 levels)
Capacitance (pF)
6800
1500
Pin 9
1100
Pin 10
680
Pin 11 1420
Pin 9
1100
Pin 10
680
Pin 11 1420
fc (Hz)
Data rate
8)-2. Comparator Output
The level comparator and the NRZ comparator shape the waveform of this input signal and output it as a
square wave. The comparator output stage is for open collector.
Thus, if the CPU is of CMOS type and the supply voltage is different, a direct interface as illustrated in the
figure below can be implemented.
CMOS IC
19
4
CMOS power supply
V
CC
1.4V
V
CC
(15)
Comparator output
Fig. 6
C
13
C
12
2
1
C
12
C
13
R
2
1
13
CXA3117AN
9) REG CONT
Controls the base bias of the external transistors.
10) LVA OUT
This pin goes high (open) when the supply voltage becomes low. Since the output is an open collector, it
can be used to directly drive CMOS device. The setting voltage of the LVA is 1.10V (typ.), and it possesses
a hysteresis with respect to the supply voltage. The hysteresis width is 10mV (typ.).
11) B.S.
Operation of the CXA3117AN can be halted by setting this pin low. This pin can be connected directly to
CMOS device. The current consumption during battery saving is 10A or less (at 1.4V).
B.S.
17
Fig. 7
8)-3. Level Comparator Output
The level comparator characteristics are as shown in the figure below. Therefore, a high signal is output at
the bit border even if the input signal is a 4.8kHz signal. This high output interval varies according to the
frequency response of the bit rate filter, and widens as the cut-off frequency becomes lower. The decoder
avoids this high interval when processing data.
Input signal
Level comparator output
f
0
+1.6
+4.8
1.6
4.8
L
H
Input frequency deviation [kHz]
O
u
t
p
u
t
14
CXA3117AN
12) M-ary (M = 2- or 4-level) FSK Demodulation System
12)-1. Output Waveform
Polarity discrimination output and MSB comparator output are used to demodulate the 4-level waveform
shown below.
[4-level FSK demodulating waveform]
01
00
10
11
01
10
00
+4.8kHz
+1.6kHz
1.6kHz
4.8kHz
[NRZ OUT] Polarity discrimination output
(When the input frequency is higher than the local frequency)
0
0
1
1
0
1
0
POS
NEG
[L.C. OUT] MSB comparator output
1
0
0
1
1
0
0
1.6kHz
4.8kHz
The 4-level FSK demodulating data is divided into an NRZ OUT and L.C. OUT shown above. Here, the
NRZ OUT corresponds to a conventional NRZ comparator output. The L.C. OUT is made comparing the
demodulated waveform amplitude to the IC internal reference voltage levels. When the threshold value of
L.C. OUT is not appropriate to the detector output, the resistance value on Pin 8 should be varied for the
detector output level adjustment or the resistor should be inserted between Pin 6 and V
CC
for the level
comparator threshold value adjustment.
For the 2-level FSK demodulation, it corresponds to a conventional NRZ comparator output.
6
R
V
CC
(The polarity can be inverted by setting the local
frequency higer than the input frequency.)
15
CXA3117AN
12)-2. 4-level Signal and Threshold Value
For Sony pager ICs, the demodulated signal is optimally matched to the NRZ comparator threshold value
by the curve correction operation described in 13) as shown in the figure below. (operation point correction
using a feedback loop filter)
Offset correction circuit
Detector output
Level comparator 1
NRZ comparator
Level comparator 2
Operation point correction (The comparator threshold value is fixed.)
The level comparator threshold value can be adjusted by varying the detector output level, which is
achieved by varying the discriminator dumping resistance. (AC gain adjustment)
Level comparator threshold value 1
NRZ threshold value = Demodulated signal average voltage
Level comparator threshold value 2
AC gain adjustment
16
CXA3117AN
12)-3. Offset Amount and Threshold Value
Immediately after power-on when the REF capacitor is not charged with the correction voltage, if the input
frequency has an offset, some time is required to correct this offset. In addition, the times required to obtain
2-level and 4-level data differ according to the offset amount.
a) 2-level signals
In the case of 2-level signals, correct data is obtained when the offset amount is smaller than the detector
output amplitude. This is 75mV or less when the detector output level is 150mVp-p which corresponds to
within 4.8kHz when converted to a frequency by the S curve. Thus, 2-level data is obtained without an
operation point correction time lag when the frequency offset is within 4.8kHz.
b) 4-level signals
In the case of 4-level signals, correct data is obtained when the offset amount is less than 1/3 of the
detector output amplitude (during 4.8kHz DEV). This is 25mV or less when the detector output level is
150mVp-p which corresponds to 1.6kHz or less when converted to a frequency by the S curve, . Thus, 4-
level data is obtained without an operation point correction time lag when the frequency offset is within
1.6kHz.
As shown above, 4-level signals have an allowable offset range 1/3 that of 2-level signals. When the offset
exceeds this allowable range, time is required to determine the operation point and obtain correct data
through feedback. Also, even if the offset is within the allowable range, the output pulse duty changes until
the offset is 0.
NRZ threshold
value offset
NRZ threshold
value offset
Level comparator threshold value 2
Level comparator threshold value 1
17
CXA3117AN
13) Principle of Quick Charge Operation
BUF in Fig. 8 is the detector buffer amplifier and COMP is the level comparator or the NRZ comparator.
The CXA3117AN has a feedback loop from the comparator input to the input circuit of the detector output
buffer. This equalizes the average value of the comparator input voltage to the reference voltage, with the
quick charge circuit of CHG being set in the feedback loop. Switching the current of the quick charge circuit
enables reduction of the rise time.
In this block, CHG is a comparator which compares input voltages and outputs a current based on this
comparison. The current on CHG is switched between high and low at Pin 18. When the power is turned
on, switch the current to high to increase the charge current at C in Fig. 8 and shorten the time constant.
During steady-state reception mode, switch the current to low, lengthening the charge time constant and
allowing for stable data retrieval. Also, controlling Pin 14 can make the current off. This is effective when the
same data are received continuously.
7
COMP
16
19
LPF
C
Reference voltage
CHG
BUF
AUDIO
FSK REF
Fig. 8
13)-1. Slow Charge Mode , Quick Charge Mode
During slow charge mode and Quick Charge Mode, if the RF system frequency is deviated, etc., and the
demodulated output has an offset voltage, feedback is applied to correct this offset voltage. Here, feedback is
applied so that the average value of the audio output voltage matches the internal regulator voltage. This
feedback shifts the S curve up and down in a parallel manner.
S curve
Offset
Reference voltage
f
0
I
n
p
u
t
s
i
g
n
a
l
When the RF system frequency is deviated,
there is no correction so an offset occurs.
S curve
Reference voltage
During slow charge mode, the S curve shifts
to correct the offset.
f
0
I
n
p
u
t
s
i
g
n
a
l
16) Misoperation Prevention Function for Continuous Data
The offset to the comparator threshold value of the detector output is canceled with the feedback loop
indicated in the paragraph 13). This operation assumes that "0" and "1" are in equal numbers in the data.
The offset is occurred when the "0" or "1" data are received continuously. In this case, setting Pin 14 high to
make the charge current off prevents the offset occurrence.
Without using this function, the stability for the same data continuously received depends on the
capacitance value on Pin 7 shown in the paragraph 13). When this capacitance value is increased, the data
is demodulated more stably; however, it takes more time for the IC to rise. If this function is not used, be
sure to connect Pin 14 to GND.
Reception signal
CHG OFF
(Pin 14)
H
L
Sync part
Data
Sync part
Data
Fig. 9
18
CXA3117AN
14) S Curve Characteristics
Even if the IF IN input signal frequency is deviated, the feedback is applied to the AUDIO operating point so
as to match it to the comparator reference voltage by the quick charge operation shown in Fig. 8. Therefore,
this feedback must be halted in order to evaluate the S curve characteristics.
To execute the evaluation, measure the average voltage on Pin 16 first and input this voltage to Pin 7 from
the external power supply.
15) Control Pins
The function controls are as shown below.
Pin No.
Symbal
Function
Input high
Input low
12
FIL SW
Data filter cut-off
control
fc: Low
fc: High
14
CHG OFF
Pin 7 charge current
control
Slow charge off
Slow charge operation
17
B.S.
Battery saving mode
control
IC operation
Sleep
18
CHARGE
Pin 7 charge speed
control
Quick charge
Slow charge
Note) Pin 14 control should be performed with Pin 18 low.
When each function is not controlled externally, set it to the state with an asterisk (
).
19
CXA3117AN
17) REF Capacitance Value and Charge Time, Hold Time
The REF capacitance is the feedback loop time constant of the S curve. This determines the detector
output low frequency cut-off, IC rise characteristics and operating voltage hold characteristics during battery
saving.
When the REF capacitance is reduced:
1. The detector output low frequency cut-off becomes higher.
2. The IC rise characteristics become faster.
3. The operating voltage hold characteristics during battery saving become shorter.
Of these, 1 has little effect on FSK, so a capacitance value that matches the used system should be
selected in consideration of 2 and 3.
17)-1. Example of IC Rise Characteristics Immediately After Power-on
17)-2. Example of Operating Voltage Hold Characteristics
When the REF capacitance is 1F, the S curve hold voltage variation is a value that has no effect on the
rise of the 4-level data after 5 minutes of battery saving as shown below.
Offset voltage after 5 minutes of battery saving: 10mV or less
1.0
0.5
0
3
f
0
+3
When the REF capacitance is 1F
[kHz]
[s]
Offset frequency and T2 (after power-on until 4-level data is obtained)
20
CXA3117AN
18) Sensitivity Adjustment Method
The constants shown in the Application Circuit diagram are for the standard external parts. However,
adjustment may be necessary depending on the conditions of use, characteristics of external parts, and the
RF system circuit and decoder connected to the IF IC, etc. Adjust the sensitivity according to the following
procedures.
a) MIX IN matching
When using a matching circuit between the RF system circuit and MIX IN of the CXA3117N, adjust the
trimmer to obtain the optimal sensitivity while monitoring the AUDIO output.
b) Local input level
The mixer circuit gain is dependent on the local signal input level to OSC IN. The input level to OSC IN
should be set as high as possible within the range of 6 to +2dBm as shown in the graph of "Local input
level vs. Mixer gain characteristics". However, care should be taken as raising the input level above +2dBm
will cause the sensitivity to drop.
When creating the local signal using the internal oscillator circuit, the oscillation level varies according to
the external capacitances attached to Pins 1 and 2 and the characteristics of the used crystal. Therefore,
be sure to adjust the external capacitance values attached to Pins 1 and 2 according to the crystal
characteristics.
C
1
and C
2
have the following range in the figure above.
C
1
C
2
C
1
= C
2
to C
1
= 5C
2
As for the ratio of C
1
to C
2
, the oscillation stabilizes as C
1
approaches equality with C
2
.
The oscillation level decreases as the C
1
and C
2
values become larger, and increases as the C
1
and C
2
values become smaller.
Use a FET probe to confirm the local input level.
c) LPF constant
The data filter cut-off may need to be changed depending on the characteristics of the connected decoder.
Adjust the capacitance values of Pins 9 to 12 while checking the incoming sensitivity including the decoder.
If the capacitance values are too large, the detector output waveform will deviate at high data rates, causing
the sensitivity to drop. Conversely, if the capacitance values are too small, the LPF will be easily affected by
noise, causing the sensitivity to drop.
Adjust capacitance values of Pins 9 to 12 so that the capacitance value described in "16) LPF Constant"
becomes smaller.
2
1
OSC
V
CC
C
1
C
2
21
CXA3117AN
d) Detector output level
The NRZ comparator and level comparator threshold values are fixed for the CXA3117AN. In the case of 4-
level signals, the relationship between the level comparator threshold value and the detector output level
affects the sensitivity. The detector output level can be adjusted by the resistance attached to Pin 8.
Increasing the resistance value also increases the output level, and vice versa.
The Pin 8 resistance value differs according to the ceramic discriminator attached to Pin 8. When the
discriminator is changed to a different type, the resistance value must be adjusted.
Adjust the resistance value while monitoring the level comparator output waveform or the sensitivity
including the decoder.
e) Quick charge circuit
The CXA3117AN has a feedback circuit that corrects the detector output operation point in order to correct
the IF frequency deviation. When the IF frequency deviation amount is large, correction takes time and may
lower the sensitivity. Adjust the oscillator frequency of the local oscillator so that the center frequency of the
signal input to Pin 5 (IF IN) is as close to 455kHz as possible.
19) CXA3117AN Standard Board Description
Outline
This board contains the external parts shown in the Application Circuit in order to evaluate CXA3117AN
operation.
Features
The following CXA3117AN basic operations can be checked.
1) Varying the data filter cut-off
2) Battery saving and other mode switching
3) NRZ output and level comparator output pins
Method of use
1) Input the CXA3117AN supply voltage Vcc = 1.4V.
The CXA3117AN operates with a single power supply.
2) The CXA3117AN uses a 21.245kHz crystal. Input the RF signal from the RF pin and use the
CXA3117AN in the condition where IF = 455kHz.
3) Set the mode switches.
Mode switch setting
Mode switches S1, S2, S3 and S4 are provided in four locations in the board. Each basic operation can
be confirmed by switching these mode switches while referring to the board layout. See the table in 15)
Control Pins for the mode switching.
Device specifications
See these Specifications for the IC specifications. The ICs for this evaluation board are ES specification.
Circuit diagram
The circuit diagram is the same as the Application Circuit diagram in these Specifications.
22
CXA3117AN
19)-1. Standard Board Layout
1
12
24
13
V
CC
GND
DISC
XTAL
C
E
R
A
F
I
L
S
1
S
2
S
3
S
4
P
N
P
R
F
3117
EVALUATION BOARD
19)-2. Mode Switch Description
S
4
Slow charge
Low
High
Quick charge
CHARGE
S
3
Sleep
L
H
IC operation
B. S.
S
2
Slow charge operation
L
H
Slow charge off
CHG-OFF
fc: High
L
H
fc: Low
FIL SW
S
1
23
CXA3117AN
19)-3. List of Standard Board Parts
VALUE
PART#
REMARKS
(MANUFACTURE)
NOTE
Inductor
1.8H
L1
EL0405
(TDK Products)
E12 series
2.5mm pitch
(Lead Pitch)
Active Component
PNP
2SA1015
(TOSHIBA CORPORATION)
Crystal
21.245MHz
XTAL
KSS 2B
(KINSEKI, LTD.)
Resistor
220
8.7k
100k
R4
R7
R5
R6
R8
(RIVER)
E12 series
1/8W
Capacitor
10 to 120p
15p
22p
100p
1000p
1200p
0.01
1
10
C1
C5
C4
C14
C3
C11
C12
C13
C8
C9
C10
C6
C7
TZ03P450FR169
(MURATA PRODUCTS)
TRIMMER CAPACITOR
DD100 series
temperature characteristics
type B
(MURATA PRODUCTS)
CERAMIC CAPACITOR
E12 series
(high dielectric constant type)
25V 1
(SHIN-EI TUSHIN KOGYO CO., LTD.)
25V 10
(SHIN-EI TUSHIN KOGYO CO., LTD.)
ELECTROLYTIC CAPACITOR
E6 series
24
CXA3117AN
Ceramic Filter
CERAFIL
CFWS455D
(MURATA PRODUCTS)
455kHz
1.5k
Ceramic Discriminator
DISC
CDBM455C50
(MURATA PRODUCTS)
455kHz
Switch
S1, S2,
S3, S4
ATE1D-2M3-10
(FUJISOKU CORPORATION)
ON ON (1 poles)
Connector
RF
HRM300-25
(HIROSE ELECTRIC CO., LTD.)
SMA CONNECTOR
Pin
2
6
Mac 8 test pin ST-1-3
(Mac eight)
L = 10mm 0.8
Mac 8 test pin LC-2-G
(Mac eight)
25
CXA3117AN
Mixer I/O characteristics and 3rd intercept point
Mixer input level [dBm]
O
u
t
p
u
t
l
e
v
e
l
[
d
B
m
]
60
80
70
60
50
40
30
20
50
40
30
20
10
0
f
O
f
1
+ f
2
Current consumption characteristics
Supply voltage [V]
1.0
2.0
3.0
4.0
0.9
1.0
1.1
1.2
1.3
1.4
C
u
r
r
e
n
t
c
o
n
s
u
m
p
t
i
o
n
[
m
A
]
Mixer input audio response and RSSI characteristics
Mixer input level [dBm]
120
60
50
40
30
20
10
0
110
100
90
80
70
60
50
40
30
20
A
u
d
i
o
r
e
s
p
o
n
s
e
[
d
B
]
R
S
S
I
[
m
V
]
0
200
400
600
800
1000
S/N
S + N + D
RF 21.7MHz
LOCAL 21.245MHz 6dBm
Audio 1.6kHz CW
Dev. 4.8kHz
0dB = 63.1mVrms
V
CC
= 1.4V
T = 25C
RSSI
f
O
= 21.7MHz
f
LO
= 21.245MHz 6dBm
f
1
= 21.725MHz
f
2
= 21.750MHz
The I/O level is for the values read at
I/O pin with the spectrum analyzer
Example of Representative Characteristics
26
CXA3117AN
Variable cut-off characteristics of audio filter
R
e
s
p
o
n
s
e
[
d
B
]
Input frequency [Hz]
100
60
200
500
1k
2k
5k
10k
50
40
30
20
10
0
Pin 12 voltage
L
H
Local input level vs. Mixer gain characteristics
Local input level [dBm]
20
5
15
10
5
0
5
0
5
10
M
i
x
e
r
g
a
i
n
[
d
B
]
f
RF
21.7MHz 60dBm
f
LO
21.245MHz
1
50
0.01
Level comparator characteristics
Comparator input voltage [mV]
C
o
m
p
a
r
a
t
o
r
o
u
t
p
u
t
v
o
l
t
a
g
e
[
m
V
]
150
0.2
0
0.6
0.4
1.0
0.8
1.4
1.2
200
250
300
1.6
1.8
2.0
27
CXA3117AN
LVA characteristics
Supply voltage [V]
1.05
0
L
V
A
c
o
m
p
a
r
a
t
o
r
o
u
t
p
u
t
v
o
l
t
a
g
e
[
V
]
0.2
0.4
0.6
0.8
1.0
1.2
1.20
1.15
1.10
NRZ comparator characteristics
Comparator input voltage [mV]
160
0
C
o
m
p
a
r
a
t
o
r
o
u
t
p
u
t
v
o
l
t
a
g
e
[
V
]
180
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
200
220
240
260
Pin 6 current [A]
0
100
L
e
v
e
l
c
o
m
p
a
r
a
t
o
r
t
h
r
e
s
h
o
l
d
v
a
l
u
e
[
m
V
]
0.5
1.0
1.5
2.0
2.5
3.0
150
200
250
300
210
Level comparator threshold value control characteristics
(Output low high switching level)
Representative example
using typical sample
Typical value when Pin 6 is shorted to Vcc
28
CXA3117AN
RF input level [dBm]
RSSI output voltage temperature characteristics
R
S
S
I
o
u
t
p
u
t
v
o
l
t
a
g
e
c
h
a
r
a
c
t
e
r
i
s
t
i
c
s
[
m
V
]
120
100
110
100
90
80
70
60
50
40
30
20
200
300
400
500
600
700
800
20C
0C
25C
50C
75C
:
:
:
:
:
Quick charge circuit output current characteristics
Pin 11 input Pin 16 voltage [mV]
80
120
160
200
240
280
320
360
0.5
0.3
0
0.3
0.5
s
l
o
w
c
u
r
r
e
n
t
[
A
]
50
30
0
30
50
f
a
s
t
c
u
r
r
e
n
t
[
A
]
Fast mode
Slow mode on
Slow mode off
Pin 7 215mV fixed
29
CXA3117AN
Detector output level and level comparator threshold
value vs. Temperature characteristics
D
e
t
e
c
t
o
r
o
u
t
p
u
t
l
e
v
e
l
a
n
d
l
e
v
e
l
c
o
m
p
a
r
a
t
o
r
t
h
r
e
s
h
o
l
d
v
a
l
u
e
[
m
V
]
100
50
0
50
100
4.8kHz Dev. detector output level
Level comparator threshold value for positive side
1.6kHz Dev. detector output level
Level comparator threshold value for negative side
Temperature [C]
20
0
25
50
75
: H L
: L H
30
CXA3117AN
Package Outline
Unit: mm
SONY CODE
EIAJ CODE
JEDEC CODE
SSOP-24P-L01
SSOP024-P-0056
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER/PALLADIUM
42/COPPER ALLOY
PACKAGE STRUCTURE
PLATING
0.1g
24PIN SSOP(PLASTIC)
0.1 0.1
0 to 10
0
.
5
0
.
2
DETAIL A
5
.
6
0
.
1
24
7.8 0.1
13
0.65
12
1
7
.
6
0
.
2
0.1
1.25 0.1
+ 0.2
A
0.13 M
NOTE: Dimension "
" does not include mold protrusion.
b=0.22 0.05
+ 0.1
0
.
1
5
0
.
0
2
+
0
.
0
5
(0.22)
(
0
.
1
5
)
0
.
1
5
0
.
0
1
DETAIL B : SOLDER
DETAIL B : PALLADIUM
+
0
.
0
3
b=0.22 0.03
B
b
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
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