CXA3246Q

8-bit 120MSPS Flash A/D Converter

Description

The CXA3246Q is an 8-bit high-speed flash A/D

converter capable of digitizing analog signals at the
maximum rate of 120MSPS. ECL, PECL or TTL can
be selected as the digital input level in accordance
with the application. The TTL digital output level
allows 1: 2 demultiplexed output.

Features
· Differential linearity error: ±0.5LSB or less
· Integral linearity error: ±0.5LSB or less
· High-speed operation with a maximum conversion

rate of 120MSPS

· Low input capacitance: 10pF
· Wide analog input bandwidth: 250MHz
· Low power consumption: 500mW
· 1: 2 demultiplexed output
· 1/2 frequency-divided clock output

(with reset function)

· Compatible with ECL, PECL and TTL digital input

levels

· TTL output "H" levels: 2.8V (Typ.)
· +3.3V line CMOS IC direct connecting available
· Single +5V power supply operation available
· Surface mounting package (48-pin QFP)

Pin Configuration (Top View)

Structure

Bipolar silicon monolithic IC

Applications
· Magnetic recording (PRML)
· Communications (QPSK, QAM)
· LCDs
· Digital oscilloscopes

E97902A8X-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CLK/E

N.C.

CLK/T

N.C.

DGND2

PAD0

PAD1

PAD2

PAD3

CLKN/E

PAD4

PAD7

PAD6

DGND1

DGND2

PBD0

PBD1

PBD2

PBD3

PAD5

RESETN/E

SELECT

RESETN/T

INV

CLKOUT

DGND2

PBD7

PBD6

PBD5

PBD4

RESET/E

AGND

DGND3

25 26 27 28 29 30

31 32 33

48 pin QFP (Plastic)

LEAD TREATMENT: PALLADIUM PLATING

CXA3246Q

Absolute Maximum Ratings (Ta = 25°C)

Unit

· Supply voltage

, DV

1, DV

0.5 to +7.0

DGND3

0.5 to +7.0

7.0 to +0.5

DGND3 DV

0.5 to +7.0

· Analog input voltage

2.7 to AV

· Reference input voltage

2.7 to AV

2.5

· Digital input voltage

ECL/PECL input pin

3 0.5 to DGND3 + 0.5

TTL input pin

DGND1 0.5 to DV

1 + 0.5

VID

N/E|)

2.7

· Storage temperature

Tstg

65 to +150

°C

· Allowable power dissipation P

1.6

(when mounted on a two-layer glass fabric base epoxy board with dimentions of 50mm

50mm, 1.6mm thick)

Recommended Operating Conditions

With a single power supply

With dual power supply

Unit

Min.

Typ.

Max.

Min.

Typ.

Max.

· Supply voltage

1, DV

2, AV

+4.75

+5.0

+5.25

+4.75

+5.0

+5.25

DGND1, DGND2, AGND

0.05

+0.05

0.05

+0.05

DGND3

+4.75

+5.0

+5.25

0.05

+0.05

0.05

+0.05

5.5

5.0

4.75

· Analog input voltage

· Reference input voltage V

+2.9

+4.1

+2.9

+4.1

+1.4

+2.6

+1.4

+2.6

1.5

2.1

1.5

2.1

· Digital input voltage

ECL/PECL input pin : V

3 + 1.5

DGND3 DV

3 + 1.5

DGND3

: V

3 + 1.1

0.4 DV

3 + 1.1

0.4

TTL input pin

: V

2.0

: V

0.8

VID

N/E|)

0.4

0.8

0.4

0.8

· Maximum conversion rate Fc (Straight mode)

100

MSPS

(DMUX mode)

120

MSPS

· Ambient temperature

+75

°C

VID: Input Voltage Differential

ECL and PECL switching level

VID

(min.)

(DGND3 1.2V)

(max.)

DGND3

CXA3246Q

Pin Description

[Symbol]

[Pin No.]

[Description]

Digital power supply

Bottom reference voltage

Analog ground

Reference voltage mid point

Analog power supply

Analog signal input

Reference voltage mid point

Analog power supply

Reference voltage mid point

Analog ground

Reference voltage (typ.)

Digital power supply

ECL/PECL clock input

TTL clock input

No connected pin

Digital power supply

Digital ground

PA side data output

Digital ground

Digital power supply

Digital ground

PB side data output

Digital ground

Digital power supply

Clock output

Data output polarity inversion

Output mode selection

TTL reset input

ECL/PECL reset input

16 to 18

21 to 28

33 to 40

AGND

DGND3

CLK/E

CLKN/E

CLK/T

N.C.

DGND2

PAD0 to PAD7

DGND1

DGND2

PBD0 to PBD7

DGND2

CLKOUT

INV

SELECT

RESETN/T

RESET/E

RESETN/E

1.4 to 2.6V

+5V

to V

+5V

2.9 to 4.1V

+5V

PECL

TTL

+5V

TTL

+5V

TTL

+5V

TTL

PECL

5.0V

1.4 to 2.6V

+5V

to V

+5V

2.9 to 4.1V

ECL

TTL

+5V

TTL

+5V

TTL

+5V

TTL

ECL

Typical voltage
level with a single
power supply

Typical voltage
level with dual
power supply

CXA3246Q

Block Diagram

6bit

126

127

128

129

191

192

193

254

255

6bit

8bit

Select

SELECT

DGND1

DGND2

AGND

INV

DGND3

VRM3

VRM2

VRM1

CLK/T

CLK/E

CLKN/E

RESETN/T

RESETN/E

RESET/E

CLKOUT

PAD0

PAD1

PAD2

PAD3

PAD4

PAD5

PAD6

PAD7

PBD0

PBD1

PBD2

PBD3

PBD4

PBD5

PBD6

PBD7

i
t

L

(LSB)

(MSB)

(LSB)

(MSB)

N.C.

CXA3246Q

Pin Description and I/O Pin Equivalent Circuit

Analog ground.
Separated from the digital ground.

Analog power supply.
Separated from the digital power
supply.

Digital ground.

Digital power supply.

Digital power supply.
Ground for ECL input.
+5V for PECL and TTL inputs.

Digital power supply.
5V for ECL input.
Ground for PECL and TTL inputs.

No connected pin.
Not connected with the internal
circuits.

N.C.

16, 17
18

3, 10

5, 8

20, 29
32, 41

19, 30
31, 42

AGND

DGND1
DGND2

DGND3

GND

+5V
(typ.)

GND

+5V
(typ.)

+5V (typ.)
(With a
single
power
supply)

GND
(With dual
power
supply)

GND
(With a
single
power
supply)

5V (typ.)
(With dual
power
supply)

No.

Symbol

I/O

Standard

voltage level

Equivalent circuit

Description

CXA3246Q

No.

CLK/T

Clock input.

RESETN/T

TTL

Vcc

GND

Reset signal input.
When left open, this pin goes to high
level. When set to low level, the
built-in CLK frequency divider circuit
can be reset.

INV

Data output polarity inversion input.
When left open, this input goes to
high level.
(See Table 1. I/O Correspondence
Table.)

SELECT

Data output mode selection.
(See Table 2. Operation Mode
Table.)

Symbol

Standard

voltage level

Equivalent circuit

Description

15 46

DGND1

1.5V

I/O

Clock input.

CLK/E complementary input.
When left open, this pin goes to the
threshold voltage.
Only CLK/E can be used for
operation, but complementary inputs
are recommended to attain fast and
stable operation.

Reset signal input.
When set to low level, the built-in
CLK frequency divider circuit can be
reset.

RESETN/E complementary input.
When left open, this pin goes to the
threshold voltage. Only RESETN/E
can be used for operation.

ECL/
PECL

CLK/E

CLKN/E

RESETN/E

RESET/E

DGND3

CXA3246Q

4.0V

(typ.)

Top reference voltage.
By-pass to AGND with a 1µF tantal
capacitor and a 0.1µF chip capacitor.

)

Reference voltage mid point.
By-pass to AGND with a 0.1µF chip
capacitor.

2.0V

(typ.)

Bottom reference voltage.
By-pass to AGND with a 1µF tantal
capacitor and a 0.1µF chip capacitor.

Comparator 1

Comparator 63

Comparator 64

Comparator 128

Comparator 191

Comparator 127

Comparator 192

Comparator 255

)

No.

Symbol

I/O

Standard

voltage level

Equivalent circuit

Description

Clock output.
(See Table 2. Operation Mode Table.)
TTL output; the high level is
clamped to approximately 2.8V.

PAD0

PAD7

Port A side data output.
TTL output; the high level is
clamped to approximately 2.8V.

PBD0

PBD7

CLKOUT

Port B side data output.
TTL output; the high level is
clamped to approximately 2.8V.

TTL

Analog input.

Comparator

Vref

AGND

DGND2

DGND1

VEE

CXA3246Q

Resolution

DC characteristics

Integral linearity error
Differential linearity error

Analog input

Analog input capacitance
Analog input resistance
Analog input current

Reference input

Reference resistance
Reference current
Offset voltage V

side

Digital input (ECL, PECL)

Digital input voltage: High

: Low

Threshold voltage
Digital input current : High

: Low

Digital input capacitance

Digital input (TTL)

Digital input voltage: High

: Low

Threshold voltage
Digital input current : High

: Low

Digital input capacitance

Digital output (TTL)

Digital output voltage : High

: Low

Switching characteristics

Maximum conversion rate
Aperture jitter
Sampling delay
Clock high pulse width
Clock low pulse width
Reset signal setup time
Reset signal hold time
Clock output delay
Data output delay

Output rise time
Output fall time

Electrical Characteristics

(AV

, DV

1, 2, DGND3 = +5V, AGND, DGND1, 2, DV

3 = 0V, V

= 4V, V

= 2V, Ta = 25°C)

Item

Symbol

Min.

Typ.

Max.

Unit

Conditions

Rref

Iref

EOT
EOB

Fc
Taj
Tds
Tpw1
Tpw0
T_rs
T_rh
Td_clk
Tdo1
Tdo2
Tr
Tf

7
0

400

2.7

6
0

3 + 1.5

3 + 1.1

50
50

2.0

10
20

2.4

120

1.2
3.0
4.5
1.0

0.5

3.0

3.5

10
20

100

600

3.3

1.5

DGND3 1.2

1.5

1.4

4.5

+ 0.5

5.0

1
1

±0.5
±0.5

285

740

5.0

DGND3

0.4

20
20

0.8

5
0
5

0.5

1.6

7.0

7.5

bits

LSB
LSB

µA

mA
mV
mV

V
V
V

µA
µA

V
V
V

µA
µA

V
V

MSPS

ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

= 2Vp-p, Fc = 5MSPS

= +3.0V + 0.07Vrms

= DGND3 0.8V

= DGND3 1.6V

= 3.5V

= 0.2V

= 2mA

= 1mA

DMUX mode

CLK
CLK
RESETN CLK
RESETN CLK

= 5pF)

DMUX mode

= 5pF)

0.8 to 2.0V

= 5pF)

0.8 to 2.0V

= 5pF)

These characteristics are for PECL input unless otherwise specified.

CXA3246Q

T =

TPS: Times Per Sample

Pd = (I

+ I

) · V

)

Rref

Dynamic characteristics

Input bandwidth
S/N ratio

Error rate

Power supply

Supply current
AVcc Pin supply current
DVcc1 pin supply current
DVcc2 pin supply current
DGND3 pin supply current
Power consumption

+ I

250

70
45
20

0.5

400

500

140

87
36
15

1.5

700

MHz

TPS

mA
mA
mA
mA
mA

= 2Vp-p, 3dB

Fc = 120MSPS,
fin = 1kHz Fs
DMUX mode
Fc = 120MSPS,
fin = 29.999MHz Fs
DMUX mode
Fc = 120MSPS,
fin = 1kHz Fs
DMUX mode
Error > 16LSB
Fc = 120MSPS,
fin = 29.999MHz Fs
DMUX mode
Error > 16LSB
Fc = 100MSPS,
fin = 24.999MHz Fs
Straight mode
Error > 16LSB

{
{

{
{
{

Item

Symbol

Min.

Typ.

Max.

Unit

Conditions

Rref: Resistance value between V

and V

Iref =

Rref

CXA3246Q

Electrical Characteristics Measurement Circuit

Current Consumption Measurement Circuit

DGND3

DGND2
DGND1
AGND

CLK/E

5MHz PECL

1.95V

Icc

Integral Linearity Error Measurement Circuit

Differential Linearity Error Measurement Circuit

CXA3246Q

A < B A > B

Comparator

Buffer

Controller

DVM

"1"

"0"

000···00

111···10

S1: ON when A < B
S2: ON when A > B

Sampling Delay Measurement Circuit

Aperture Jitter Measurement Circuit

CXA3246Q

OSC1

: Variable

OSC2

Logic

Analizer

100MHz

Amp

ECL
Buffer

CLK

1024

samples

Aperture Jitter Measurement Method

CLK

129
128
127

126
125

Sampling timing fluctuation
(= aperture jitter)

(LSB)

Error Rate Measurement Circuit

Comparator

A > B

Pulse

Counter

CXA3246Q

Signal

Source

Latch

1/8

Signal

Source

1kHz

2Vp-p Sine Wave

CLK

16LSB

Where

(LSB) is the deviation of the output codes when

the largest slew rate point is sampled at the clock which

has exactly the same frequency as the analog input

signal, the aperture jitter Taj is:

Taj =

/ =

/ ( )

256

CXA3246Q

Description of Operation Modes

The CXA3246Q has two types of operation modes which are selected with Pin 45 (SELECT).

1. DMUX mode (See Application Circuit 1-(1), (2) and (3).)

Set the SELECT pin to Vcc for this mode. In this mode, the clock frequency is divided by 2 in the IC, and the

data is output after being demultiplexed by this 1/2 frequency-divided clock. The 1/2 frequency-divided clock,

which has adequate setup time and hold time for the output data, is output from the clock output pin.

When using the multiple CXA3246Q in DMUX mode, the start timing of the 1/2 frequency-divided clocks

becomes out of phase, producing operation such as that shown in the example on the next page. As a

countermeasure, the CXA3246Q has a function that resets the 1/2 frequency-divided clocks.

When resetting this 1/2 frequency-divided clock, the low level of the reset signal should be input to the

RESETN pin (Pin 46 or 48). The reset signal requires the setup time (T_rs

1.0ns) and hold time (T_rh

0.5ns) to the clock rising edge because it is synchronized with and taken in the clock.

The reset period can be extended by making the low level period of the reset signal longer because the clock

output pin is fixed to low (reset) during the low level period at the clock rising edge. If the reset start timing is

regarded as not important, the timing where the reset signal is set from high to low is not so consequence.

However, when the reset is released the timing where the reset signal is set from low to high must become

significant because the timing is used to commence the 1/2 frequency-divided clock. In this case, the setup

time (T_rs) is also necessary.

See the timing chart for detail. (This chart shows the example of reset for 2T.)

The A/D converter can operate at Fc (min.) = 120MSPS in this mode.

Table 2. Operation Mode Table

SELECT
pin

GND

DMUX mode

Straight mode

120MSPS

100MSPS

Demultiplexed output

60Mbps

Straight output

100Mbps

The input clock is 1/2 frequency divided
and output.

60MHz

The input clock is inverted and output.

100MHz

Operation
mode

Maximum
conversion rate

Data output

Clock output

CXA3246Q

8bit

CLKOUT

DATA

8bit

CLKOUT

DATA

CLK

CXA3246Q

CLK

RESETN

CLK

RESETN

8bit

CLKOUT

DATA

8bit

CLKOUT

DATA

CLK

CXA3246Q

CLK

RESETN

CLK

RESETN

CLK

Reset signal

(Reset period)

2. Straight mode (See Application Circuits 1-(4), (5) and (6).)

Set the SELECT pin to GND for this mode. In this mode, data output can be obtained in accordance with the

clock frequency applied to the A/D converter for applications which use the clock applied to the A/D converter

as the system clock.

The A/D converter can operate at Fc (min.) = 100MSPS in this mode.

Digital input level and supply voltage settings

The logic input level for the CXA3246Q supports ECL, PECL and TTL levels.

The power supplies (DV

3, DGND3) for the logic input block must be set to match the logic input (CLK and

reset signals) level.

Digital input level

ECL

PECL

TTL

0V
0V

+5V
+5V

±5V
+5V
+5V

(1) (4)
(2) (5)
(3) (6)

DGND3

Supply voltage Application circuits

Table 3. Logic Input Level and Power Supply Settings

When the reset signal is not used

When the reset signal is used

CXA3246Q

Application Circuit 1

(1) DMUX ECL input

+5V(D)

(
D

)

(
A

)

+5V(D)

8 bit Digital Data

Latch

8 bit Digital Data

Latch

PBD0 to PBD7
8 bit Digital Data

PAD0 to PAD7
8 bit Digital Data

ECL RESET signal

ECL-CLK

13 14 15 16 17 18 19 20 21 22 23 24

40 39 38 37

(
D

)

(
A

)

(2) DMUX PECL input

+5V(D)

8 bit Digital Data

Latch

8 bit Digital Data

Latch

PBD0 to PBD7
8 bit Digital Data

PAD0 to PAD7
8 bit Digital Data

PECL-CLK

13 14 15 16 17 18 19 20 21 22 23 24

40 39 38 37

(
D

)

(
D

)

(
A

)

(
A

)

PECL RESET signal

(3) DMUX TTL input

+5V(D)

(
A

)

+5V(D)

8 bit Digital Data

Latch

8 bit Digital Data

Latch

PBD0 to PBD7
8 bit Digital Data

PAD0 to PAD7
8 bit Digital Data

TTL RESET signal

TTL-CLK

13 14 15 16 17 18 19 20 21 22 23 24

40 39 38 37

(
D

)

(
A

)

(
D

)

CXA3246Q

(4) Straight ECL input

+5V(D)

8-bit Digital Data

Latch

PBD0 to PBD7
8-bit Digital Data

ECL-CLK

13 14 15 16 17 18 19 20 21 22 23 24

40 39 38 37

(
D

)

ECL

TTL

(
A

)

(
A

)

(
D

)

(5) Straight PECL input

+5V(D)

8-bit Digital Data

Latch

PBD0 to PBD7
8-bit Digital Data

PECL-CLK

13 14 15 16 17 18 19 20 21 22 23 24

40 39 38 37

(
D

)

PECL

TTL

(
A

)

(
A

)

(
D

)

(6) Straight TTL input

+5V(D)

8-bit Digital Data

Latch

PBD0 to PBD7
8-bit Digital Data

TTL-CLK

13 14 15 16 17 18 19 20 21 22 23 24

40 39 38 37

(
D

)

(
A

)

(
A

)

(
D

)

CXA3246Q

Application Circuit 2

DMUX Mode TTL I/O (When a single power supply is used)

CLK/E

N.C.

CLK/T

N.C.

DGND2

PAD0

PAD1

PAD2

PAD3

CLKN/E

RESETN/E

SELECT

RESETN/T

INV

CLKOUT

DGND2

PBD7

PBD6

PBD5

PBD4

RESET/E

I
N

Analog
input

+5V (A)

TTL CLK

(
L

)

P

(
M

)

P

(
L

)

P

(
M

)

P

1µF

10µF

1µF

+5V

(D)

short

Short the analog system and digital system at one point immediately
under the A/D converter. See the Notes on Operation.
is the chip capacitor of 0.1µF. Also, C

is important to suppress the noise generated

during the TTL output circuit is operating. Place C

at the fixed position

between the pins with the shortest distance.

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

CXA3246Q

Notes on Operation

· The CXA3246Q has the PECL and TTL input pins for the clock and reset input pins. When the clock is input

in PECL level, inputting the reset signal in PECL level is recommended. Also, when the clock is input in TTL

level, inputting the reset signal in TTL is recommended.

· The impedance of the input signal should be properly matched to ensure the CXA3246Q's stable operation at

the high speed.

· The power supply and grounding have a profound influence on converter performance. The power supply

and grounding method are particularly important during high-speed operation. General points for caution are

as follows.

-- The ground pattern should be as large as possible. It is recommended to make the power supply and

ground patterns wider at an inner layer using a multi-layer board.

-- To prevent interference between AGND and DGND and between AVcc and DVcc, make sure the

respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVcc

and DVcc lines at one point each via a ferrite-bead filter, etc. Shorting the AGND and DGND patterns in

one place immediately under the A/D converter improves A/D converter performance.

-- Be sure to turn the analog and digital power supplies on simultaneously. If not simultaneously, the IC does

not operate correctly.

-- Ground the power supply pins (AVcc, DVcc1, DVcc2, DV

3) as close to each pin as possible with a

0.1µF or larger ceramic chip capacitor.

(Connect the AVcc pin to the AGND pattern and the DVcc1, DVcc2 and DV

3 pins to the DGND pattern.)

-- It is recommended to place the ceramic chip capacitor of 0.1µF or more, in particular, between DVcc2

and DGND2 with the shortest distance. This has the effect to suppress the noise generated when the

CXA3246Q TTL output circuit operates.

-- The digital output wiring should be as short as possible. If the digital output wiring is long, the wiring

capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output

waveform since the original output slew rate is quite fast.

· The analog input pin V

has an input capacitance of approximately 10pF. To drive the A/D converter with the

proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance

or parasitic inductance by using a large capacity drive circuit, keeping wiring as short as possible, and using

chip parts for resistors and capacitors, etc.

· The V

and V

pins must have adequate by-pass to protect them from high-frequency noise. By-pass them

to AGND with approximately 1µF tantal capacitor and 0.1µF chip capacitor as short as possible.

· If the CLKN/E pin is not used, by-pass this pin to DGND with an approximately 0.1µF capacitor. At this time,

approximately DGND3 1.2V voltage is generated. However, this is not recommended for use as the threshold

voltage V

because it is too weak.

· When the digital input level is ECL or PECL level,

/E pins should be used and

/T pins left open. When

the digital input level is TTL,

/T pins should be used and

/E pins left open.

· The CXA3246Q TTL output high level is clamped to approximately 2.8V in the IC. This makes it possible to

directly interface with the 3.5V system CMOS IC.

· The CXA3026Q has the output pins P1

and P2

. However, in the CXA3246Q, these symbols are

changed as PA

and PB

. At this time, the P1 side of the CXA3026Q is changed to the PB side for the

CXA3246Q; the P2 side of the CXA3026Q to the PA side for the CXA3246Q.

· The pipeline delay of the CXA3246Q is smaller by one clock, compared to that of CXA3026Q.

CXA3246Q

Current consumption vs.

Ambient temperature characteristics

Ta Ambient temperature [°C]

r
r
e

t

c

t
i
o

[
m

]

100

105

110

Current consumption vs.

Conversion rate characteristics

Fc Conversion rate [MSPS]

r
r
e

t

c

t
i
o

[
m

]

100

105

110

120

DMUX mode
C

= 5pF

fin = 1kHz

CLK

Analog input current vs.

Analog input voltage characteristics

Analog input voltage [V]

l
o

i
n

t

c

r
r
e

t

[
µ

]

100

Reference current vs.

Ambient temperature characteristics

Ta Ambient temperature [°C]

f
e

r
e

r
r
e

t

[
m

]

= 4V

= 2V

Example of Representative Characteristics

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA3246Q

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA3246Q