E01115-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXA3562R

100 pin LQFP (Plastic)

Description

The CXA3562R is a driver IC developed for use

with Sony polycrystalline silicon TFT LCD panels. It

supports digital 2-parallel and single input, and the

input data is analog demultiplexed into 12 phases and

output. The CXA3562R can directly drive an LCD

panel, and the VCOM setting circuit and precharge

pulse waveform generator are also on-chip.

Features

· Supports 10-bit 2-parallel and single input

· Supports signals up to UXGA

(1/2 clock when using UXGA signals)

· Low output deviation by on-chip output offset cancel circuit

· Supports both line inversion and dot and line inversion

· On-chip timing generator with ECL

· VCOM voltage generation circuit

· Precharge pulse waveform generation circuit

Applications

LCD projectors and other video equipment

Absolute Maximum Ratings (V

= 0V)

· Supply voltage

5.5

· Operating temperature

Topr

20 to +70

°C

· Storage temperature

Tstg

65 to +150

°C

· Allowable power dissipation P

2300

Recommended Operating Conditions

· Supply voltage

15.0 to 15.5

4.75 to 5.25

· Operating temperature

Topr

20 to +70

°C

LCD Driver

CXA3562R

Block Diagram and Pin Configuration

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

100

D_A9

TEST

SL_INV

SL_SCN

SL_D

DIRC

F/H_CNT

VREF_O

VREF_I

GND

PRG

SID_L

PRG_L

SID_OUT

SID_OUTX

VCOM_OFST

VCOM_OUT

SH_OUT1

SH_OUT2

SH_OUT3

SH_OUT4

SH_OUT5

SH_OUT6

GND

D_A8

D_A7

D_A6

D_A5

D_A4

D_A3

D_A2

D_A1

D_A0

GND

D_B9

D_B8

D_B7

D_B6

D_B5

D_B4

D_B3

D_B2

D_B1

D_B0

GND

PGND

GND

SH_OUT7

SH_OUT8

SH_OUT9

SH_OUT10

SH_OUT11

TEST

POSCTR0

MCLK

MCLKX

FRP

SHST

POSCTR1

POSCTR2

POSCTR3

SHTEST

GND

DCFBOFF

CAL_IL

CAL_IH

CAL_OH

CAL_OL

SIG_OFST

SIG.C

SH_OUT12

Line Inv.

VCOM Gen.

SID Gen.

Offset Cancel

Line Inv.

Offset Cancel

Line Inv.

Offset Cancel

Line Inv.

Offset Cancel

Line Inv.

Offset Cancel

Line Inv.

Offset Cancel

Line Inv.

S/H

D/A

Vref Gen.

Offset Cancel

Line Inv.

Offset Cancel

Line Inv.

Offset Cancel

Line Inv.

Offset Cancel

Line Inv.

Offset Cancel

Line Inv.

FRP_OD

FRP_EV

CAL_PLS

Offset Cancel

Offset Cancel Level Gen.

S/H

D/A

CXA3562R

Pin Description

No.

Symbol

I/O

Standard
voltage level

Equivalent circuit

Description

140k

60k

100µ

140k

GND

192

50k

PECL
differential
(amplitude
0.4V or more
between
V

to 2V)

or TTL input

High:

2.0V

Low:

0.8V

High:

2.0V

Low:

0.8V

High:

2.0V

Low:

0.8V

GND

192

50k

GND

192

50k

GND

30k

20µ

GND

30k

10µ

1 to 5.0V

0 to 5.0V

SIG_OFST

SIG.C

POSCTR0
POSCTR1
POSCTR2
POSCTR3

6
7
8
9

SHST

FRP

MCLK
MCLKX

2
3

Dot clock input.
PECL differential input or TTL
input. For TTL input, input to
MCLK and connect MCLKX to
GND through a capacitor.

LCD panel AC drive inversion
timing input.
High: inverted
Low: non-inverted
See the Timing Chart.

Internal sample-and-hold timing
circuit reset pulse input.
This pin is also used as the
offset cancel level insertion
timing input.
A reset is applied to the internal
timing generator at the falling
edge.

Output phase adjustment.
The output phase is adjusted in
MCLK period units when
SL_DAT (Pin 72) is high, and in
1/2 MCLK period units when
SL_DAT is low.

Signal center voltage (inversion
folded voltage) adjustment input.
The SH_OUT output center
voltage can be adjusted in the
range from 7.0 to 8.0V.

Output signal offset adjustment
from signal center voltage.
The SH_OUT output 100%
white level (at 3FF input) voltage
can be adjusted in the range
from 0 to 1V from the center
voltage.

CXA3562R

3.0 to 6.0V
9.0 to 12.0V

9.0 to 12.0V
3.0 to 6.0V

GND

1.5 to 13.5V

5.0 to 8.0V

0 to 5.0V

VCOM_OFST

VCOM_OUT

SH_OUT12

SH_OUT1

25, 27,
29, 31,
33, 35,
41, 43,
45, 47,
49, 51

DCFBOFF

CAL_IH
CAL_IL

21
22

CAL_OL
CAL_OH

18
19

GND

145

40µ

20µ

GND

30k

20k

GND

145

24k

GND

300

GND

145

100k

80µ

500

GND

100

No.

Symbol

I/O

Standard
voltage level

Equivalent circuit

Description

Level output for canceling the
offset between channels.
Connect directly to CAL_IL and
CAL_IH, respectively.

Level input for canceling the
offset between channels.
Connect directly to CAL_OL and
CAL_OH, respectively. When
using two CXA3562R, connect
the CAL_IL and CAL_IH of both
chips to the CAL_OL and
CAL_OH of only one CXA3562R.

Offset cancel function off.
Normally connect to GND to
use with the offset cancel
function on.
High (offset cancel function off)
when open.

Demultiplexed output of AC
inverse driven video signals.
Can be connected directly to
the LCD panel.

LCD panel common voltage
output.
Can be set in the range from
the SH_OUT center potential
Vsig.c to Vsig.c 2V by
VCOM_OFST.

LCD panel common voltage
adjustment.
VCOM_OUT can be set in the
range from the SH_OUT center
potential Vsig.c to Vsig.c 2V
by inputting 0 to 5V.

CXA3562R

1.5 to 13.5V

1.0 to 5.0V

High:

2.0V

Low:

0.8V

3.2V

High:

2.0V

Low:

0.8V

Open: Low

F/H_CNT

VREF_O

VREF_I

PRG

PRG_LV
SID_LV

58
59

SID_OUTX
SID_OUT

56
57

GND

145

100k

0.2p

GND

50k

29µ

50k

GND

10k

100k

GND

280µ

70µ

10µ

33.3k

GND

20µ

20k

12.4k

GND

192

50k

200k

No.

Symbol

I/O

Standard
voltage level

Equivalent circuit

Description

Precharge waveform output.
SID_OUTX outputs the inverse
of SID_OUT based on the
output center voltage. These
pins cannot directly drive the
LCD panel, so input to the LCD
panel with an external a buffer.

Precharge level setting.
Adjusts the SID_OUT and
SID_OUTX output potential.
PRG_LV is reflected when the
PRG input pin (Pin 60) is high,
and SID_LV is reflected when
PRG is low.

Timing pulse input for switching
the Pins 56 and 57 output levels.
(See PRG_LV (Pin 58) and
SID_LV (Pin 59).)

Internal D/A converter reference
voltage input.
Normally connect directly to
VREF_O.

Reference voltage output.
Normally connect directly to
VREF_I, and connect to GND
through a 0.5 to 1.0µF capacitor.

SH_OUT output timing selection.
High: SH_OUT1 to SH_OUT6
and SH_OUT7 to SH_OUT12
are output at different timing.
Low: SH_OUT1 to SH_OUT12
are output at the same timing.

CXA3562R

Power GND.

Power V

15V power supply.

5V power supply.

1.7 to 3.2V

2.5V

High:

2.0V

Low:

0.8V

DIRC

SHTEST

TEST

1, 75

GND

70k

30µ

180k

GND

192

1µ

20µ

GND

192

250k

20k

250k

20k

10µ

GND

192

50k

GND

15.5V

GND

PGND

GND

26, 50

11 to 15,
20, 36,
37, 39,
40,
61 to 65,
86 to 90

23, 28,
30, 32,
34, 42,
44, 46,
48, 52

No.

Symbol

I/O

Standard
voltage level

Equivalent circuit

Description

Power saving.
Power saving mode when set to
low level.
Low (power saving mode) when
open.
Normally connect to V

GND.

DAC output monitor test.
Normally connect to V

Test.
Leave open.

Scan direction setting.
High: output as a time series in
ascending order of output pin
symbol (in order from SH_OUT1
to SH_OUT12)
Low: output in descending order

CXA3562R

High:

2.0V

Low:

0.8V

Open: Low

High:

2.0V

Low:

0.8V

Open: High

High:

2.0V

Low:

0.8V

Open: Low

High:

2.0V

Low:

0.8V

High:

2.0V

Low:

0.8V

D_B9
to
D_B0

100

D_A9
to
D_A0

SL_INV

SL_SCN

SL_DAT

GND

192

50k

200k

GND

192

50k

200k

GND

192

50k

200k

GND

192

50k

76 to

GND

192

50k

100

91 to

No.

Symbol

I/O

Standard
voltage level

Equivalent circuit

Description

Digital input mode switch setting.
High: single input from the A port
Low: parallel input from both the
A and B ports

A and B port input switching
interlocked/non-interlocked
setting relative to scan direction
setting during parallel input.
High: A and B port switching
interlocked to DIRC
Low: fixed regardless of DIRC

SH_OUT odd-numbered and
even-numbered output polarity
inverted/non-inverted setting.
High: odd-numbered and even-
numbered outputs inverted
Low: non-inverted

A port digital data input.

B port digital data input.

CXA3562R

Electrical Characteristics Measurement Circuit

100

D_A9

TEST

SL_INV

SL_SCN

SL_D

DIRC

F/H_CNT

VREF_O

VREF_I

GND

PRG

SID_L

PRG_L

SID_OUT

SID_OUTX

VCOM_OFST

VCOM_OUT

SH_OUT1

SH_OUT2

SH_OUT3

SH_OUT4

SH_OUT5

SH_OUT6

GND

D_A8

D_A7

D_A6

D_A5

D_A4

D_A3

D_A2

D_A1

D_A0

GND

D_B9

D_B8

D_B7

D_B6

D_B5

D_B4

D_B3

D_B2

D_B1

D_B0

GND

PGND

GND

SH_OUT7

SH_OUT8

SH_OUT9

SH_OUT10

SH_OUT11

TEST

POSCTR0

MCLK

MCLKX

FRP

SHST

POSCTR1

POSCTR2

POSCTR3

SHTEST

GND

DCFBOFF

CAL_IL

CAL_IH

CAL_OH

CAL_OL

SIG_OFST

SIG.C

SH_OUT12

360p

1µ

47p

360p

15.5V

CXA3562R

Electrical Characteristics

No.

Item

Symbol

Measurement
points

Measurement conditions

Min.

Typ. Max. Unit

Digital input
resolution

Digital input
setup time

Digital input
hold time

MCLK input
frequency
range 1

MCLK input
frequency
range 2

VREF_O output
voltage range

SH_OUT
amplitude 1

SH_OUT
amplitude 2

SH_OUT
minimum
amplitude

SH_OUT
slew rate

SH_OUT
minimum
output voltage

SH_OUT
maximum
output voltage

Output deviation
between
channels 1

Output deviation
between
channels 2

Output deviation
between ICs 1

MCLK1

MCLK2

VREF_O

SHOUT1p-p

SHOUT2p-p

OUTMINp-p

OUT

MIN

MAX

OUT1

OUT2

IC1

OUT1

OUT2

OUT1

OUT12

OUT1

OUT12

OUT1

OUT12

OUT1

OUT12

OUT1

OUT12

OUT1

OUT12

SHST, D_A[9:0] and D_B[9:0] minimum
setup time relative to MCLK input. (PELL)

SHST, D_A[9:0] and D_B[9:0] minimum
hold time relative to MCLK input. (PECL)

SL_DAT: 5V; maximum frequency at
which the internal timing generator
and D/A converter operate normally.

SL_DAT: 0V; maximum frequency at
which the internal timing generator
and D/A converter operate normally.

Measure the VREF_O (Pin 69)
voltage.

Measure the SH_OUT1 voltage
difference at D_A[9:0]: 000h and 3FFh.

Measure the SH_OUT2 voltage
difference at D_B[9:0]: 000h and 3FFh.

Lower the VREF_I voltage and adjust
the amplitude; minimum amplitude at
which SH_OUT1 can be output at
D_B[9:0]: 000h and 3FFh.

Load capacitance = 360pF; measure
slew rate at 10 to 90% of output
waveform rise and fall when D_A[9:0]
is varied from 000h to 3FFh and from
3FFh to 000h.

Minimum voltage at which sample-
and-hold outputs V

OUT1

to V

OUT12

can

be output.

Maximum voltage at which sample-
and-hold outputs V

OUT1

to V

OUT12

can

be output.

Value obtained by subtracting minimum
V

OUT1

to V

OUT12

value from maximum

OUT1

to V

OUT12

value at D_A[9:0]: 200h

and D_B[9:0]: 200h.

Value obtained by subtracting minimum
V

OUT1

to V

OUT12

value from maximum

OUT1

to V

OUT12

value at D_A[9:0]: 000h

or 3FFh and D_B[9:0]: 000h or 3FFh.

Value obtained by subtracting minimum
V

OUT1

to V

OUT12

value from maximum

OUT1

to V

OUT12

value at D_A[9:0]: 200h

and D_B[9:0]: 200h. (when using two
CXA3562R)

3.20

4.50

300

bit

MHz

V/µs

mVp-p

3.10

4.44

160

1.5

100

3.32

4.83

13.6

CXA3562R

Output deviation
between ICs 2

SID output
gain 1

SID output
gain 2

SID output
slew rate

Signal center
adjustable range

SH_OUT offset
adjustable range

VCOM
adjustable range

current

consumption

current

consumption

Current
consumption in
power saving
mode

Differential
linearity error

Integral linearity
error

IC2

SID1

SID2

SID

SIG

SIGOFST

COM

DLE

ILE

OUT1

OUT12

SID_LV

SID

SIDX

PRG_LV

SID

SIDX

SID

SIDX

OUT1

COM

VDD

VCC1

VCC2

VDD

VCC1

VCC2

Value obtained by subtracting minimum
V

OUT1

to V

OUT12

value from maximum

OUT1

to V

OUT12

value at D_A[9:0]: 000h

or 3FFh and D_B[9:0]: 000h or 3FFh.
(when using two CXA3562R)

PRG: 0V; measure V

SID_LV

and V

SID

FRP: 0V, and V

SID_LV

and V

SIDX

FRP: 5V.
Calculate as A

SID1

= V

SID(X)

SID_LV

PRG: 5V; measure V

PRG_LV

and V

SID

FRP: 0V, and V

PRG_LV

and V

SIDX

FRP: 5V.
Calculate as A

SID2

= V

SID(X)

PRG_LV

Load capacitance = 47pF, PRG: 0V;
input a repeating high/low pulse to FRP
(Pin 4), and apply DC input voltage so
that V

SID

and V

SIDX

are 2.5V/11.5V.

Measure slew rate at 10 to 90% of
output waveform rise and fall.

OUT1

center voltage when SIG.C

(Pin 16) is varied from 1 to 5V.

D_A[9:0]: 3FFh, FRP: 0V, D_B[9:0]:
3FFh; value obtained by subtracting
V

OUT1

from V

OUT1

center voltage when

SIG_OFST (Pin 17) is varied from 1 to
5V.

VCOM_OUT voltage when VCOM_OFST
(Pin 54) is varied from 0 to 5V.

= I

VDD

= I

VCC1

+ I

VCC2

(no digital data input)

GND (Pin 66),
I

= I

VDD

+ I

VCC1

+ I

VCC2

VREF

_I = 3.2V

VREF

_I = 3.2V

2.0

mVp-p

times

V/µs

LSB

No.

Item

Symbol

Measurement
points

Measurement conditions

Min.

Typ.

Max. Unit

1.9

2.5

0.7

1.2

2.1

112

0.7

1.2

CXA3562R

Description of Operation

The flow of internal operations is described below.

The digital signals input to D_A9 to D_A0 and D_B9 to D_B0 are internally D/A converted into approximately

1.5V (at VREF_I: 3.2V) analog signals. After that, the signal that has been demultiplexed into 12 phases is

amplified by a factor of three times, inverted at the signal center potential according to FRP, and output.

The output level relative to the digital input changes according to the following settings.

A: SIG_OFST voltage

B: VREF_I voltage

C: SIG.C voltage

1. Digital input block

The CXA3562R can be set to single input from only the A port or parallel input from both the A and B ports,

and port switching by right/left inversion is also possible in parallel input mode. This makes it possible to

support various systems.

In single input mode, the signal is internally demultiplexed to 2-parallel format and input to the D/A converter.

2. D/A converter block

The internal D/A converter has two systems for odd-numbered and even-numbered outputs. The voltage input

from VREF_I becomes the 100% white level potential of the analog converted signal, and this amplitude is a

maximum 1.5Vp-p with respect to input data of 000h to 3FFh.

3. Sample-and-hold (S/H) block

The odd-numbered and even-numbered D/A converter outputs are input to the odd-numbered and even-

numbered sample-and-hold blocks, respectively. The signals are converted from time series signals into 6-phase

cyclic parallel signals by the sample-and-hold group which is appropriately controlled by the internal timing

generator. For forward scan, the signals are output in the ascending order of SH_OUT1, SH_OUT2, SH_OUT3

... SH_OUT12. For reverse scan, this order is inverted and the signals are output in descending order. Connect

the signals to the LCD panel according to the order used. The timing of each sample-and-hold pulse is shown

on the following pages. These pulses are not output and are used only inside the IC.

GND

Signal Center

1023

512

Digital IN

SH_OUT

CXA3562R

Single input mode

DAC

S/H

D_A[9:0]

MCLK/2

D_A2

D_A1

D_B2

DAC_O

MCLK

10bit

D_A[9:0]

D_A1

D_A2

DAC_O

MCLK

D_B2

SH1_1_2

SH1_3_4

SH1_5_6

SH1_7_8

SH1_9_10

SH1_11_12

SH2_1_6

SH2_7_12

SH3A_1_12

SH3B_7_12

SH3B_1_6

SH1_1_2

SH1_3_4

SH1_5_6

SH1_7_8

SH1_9_10

SH1_11_12

SH2_1_6

SH2_7_12

SH3A_1_12

SH3B_7_12

SH3B_1_6

DIRC: H

DIRC: L

F/H_CNT: L

F/H_CNT: H

F/H_CNT: L

F/H_CNT: H

CH1 to CH12 simultaneous output timing

CH1 to CH6 simultaneous output timing

CH7 to CH12 simultaneous output timing

CH1 to CH12 simultaneous output timing

CH1 to CH6 simultaneous output timing

CH7 to CH12 simultaneous output timing

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

CXA3562R

2-parallel input mode

DAC

S/H

D_A[9:0]

MCLK

D_A2

D_B2

DAC_O

D_B[9:0]

10bit

D_A[9:0]

MCLK

D_A2

DAC_O

D_B[9:0]

D_B2

SH1_1_2

SH1_3_4

SH1_5_6

SH1_7_8

SH1_9_10

SH1_11_12

SH2_1_6

SH2_7_12

SH3A_1_12

SH3B_7_12

SH3B_1_6

SH1_1_2

SH1_3_4

SH1_5_6

SH1_7_8

SH1_9_10

SH1_11_12

SH2_1_6

SH2_7_12

SH3A_1_12

SH3B_7_12

SH3B_1_6

DIRC: H

DIRC: L

F/H_CNT: L

F/H_CNT : H

F/H_CNT: L

F/H_CNT: H

CH1 to CH12 simultaneous output timing

CH1 to CH6 simultaneous output timing

CH7 to CH12 simultaneous output timing

CH1 to CH12 simultaneous output timing

CH1 to CH6 simultaneous output timing

CH7 to CH12 simultaneous output timing

CXA3562R

4. Timing generator (TG) block

The internal timing generator operates by one pair of differential clock inputs (MCLK, MCLKX) and a horizontal sync

signal input (SHST), and generates the timing pulses needed by the demultiplexer block, dot inversion control pulse

and output deviation cancel circuit. The various operating modes can be designated by the pin settings.

The SHST and FRP inputs should satisfy the relationship shown in the figure below with the MCLK and

MCLKX input period as 1clk.

The CXA3562R can select various operating modes according to the timing generator block settings. These

settings are described below.

· SL_DAT (Pin 72)

Digital input selection. Single input from only the A port is selected when set to high level, and parallel input

from both the A and B ports is selected when set to low level. When inputting a 2-parallel processed digital

video signal in parallel input mode, input the earlier time series data to the A port and the later time series data

to the B port. Input a master clock having the same period as the input data rate to MCLK in both modes.

This pin is low level (2-parallel input mode) when left open.

· DIRC (Pin 71), SL_SCN (Pin 73)

Scan direction settings. Output is ascending order when DIRC is set to high level, and inverted to descending

order (SH_OUT1 to SH_OUT12) when set to low level. At this time if SL_SCN is set to high, the A and B port

data can be switched by switching DIRC between high and low. When SL_SCN is set to low, the A port data is

output from the odd-numbered SH_OUT and the B port data is output from the even-numbered SH_OUT

regardless of the DIRC setting.

Set SL_SCN to high when SL_DAT is high.

SL_SCN: L

SL_SCN: H

SH_OUT1: A6, SH_OUT2: B6,
SH_OUT3: A5, SH_OUT4: B5,
SH_OUT5: A4, SH_OUT6: B4,
SH_OUT7: A3, SH_OUT8: B3,
SH_OUT9: A2, SH_OUT10: B2,
SH_OUT11: A1, SH_OUT12: B1

SH_OUT1: B6, SH_OUT2: A6,
SH_OUT3: B5, SH_OUT4: A5,
SH_OUT5: B4, SH_OUT6: A4,
SH_OUT7: B3, SH_OUT8: A3,
SH_OUT9: B2, SH_OUT10: A2,
SH_OUT11: B1, SH_OUT12: A1

SH_OUT1: A1, SH_OUT2: B1,
SH_OUT3: A2, SH_OUT4: B2,
SH_OUT5: A3, SH_OUT6: B3,
SH_OUT7: A4, SH_OUT8: B4,
SH_OUT9: A5, SH_OUT10: B5,
SH_OUT11: A6, SH_OUT12: B6

DIRC: H

DIRC: L

30clk or more

1µs or more

SHST

FRP

D_A[9:0]

D_B[9:0]

CXA3562R

· SL_INV (Pin 74)

Dot inversion and line inversion selection. When set to low level, all SH_OUT channels are output at the same

polarity as shown by the solid line in the figure below. When set to high level, the odd-numbered and even-

numbered SH_OUT outputs are output at inverse polarities. At this time the odd-numbered outputs are

inverted when the FRP pulse is high, and non-inverted when the FRP pulse is low. Conversely, the even-

numbered outputs are inverted when the FRP pulse is low, and non-inverted when the FRP pulse is high.

· Output phase setting

The phase of each SH_OUT output can be adjusted in MCLK period units when SL_DAT is high or in 1/2 MCLK

period units when SL_DAT is low by POSCTR[3:0] (Pins 6 to 9). The phase can be set in 16 ways by 4-bit digital

input. The output phase shifts backward by the above unit each time this setting is increased by one bit.

· F/H_CNT (Pin 70)

SH_OUT output timing phase setting. When set to low level, all SH_OUT outputs are output at the same

timing. When set to high level, SH_OUT1 to SH_OUT6 and SH_OUT7 to SH_OUT12 are output at phases

offset by 1/2 clock period from each other.

SH_OUT

GND

FRP

GND

SH_OUT1 to 6

SH_OUT7 to 12

GND

SH_OUT1 to 6

SH_OUT7 to 12

F/H_CNT: L

F/H_CNT: H

CXA3562R

5. Calibration level generator block

The CXA3562R generates the offset cancel circuit reference with a calibration level generator in order to

minimize the deviation between channels at the center level.

The 200h output level is generated at both the AC output high and low sides, and these levels are DC output

from CAL_OH and CAL_OL, respectively. At the same time, 200h data is forcibly inserted into the video signal

while the video blanking period SHST pulse is low level, and feedback is applied so that the output levels of all

SH_OUT channels conform to CAL_IH and CAL_IL during this period.

6. SID signal generator block

This circuit generates the precharge signal waveform used by the LCD panel.

The voltage input from PRG_LV (Pin 58) and SID_LV (Pin 59) is switched by the PRG pulse (Pin 60). The

PRG_LV voltage is selected when PRG is high, and the SID_LV voltage is selected when PRG is low. This

signal is then further amplified by a factor of two times and folded by the FRP pulse. The folded center voltage

is the SH_OUT center voltage (voltage set by the SIG.C pin). SID_OUT (Pin 57) is inverted when FRP is high,

and non-inverted when FRP is low. Conversely, SID_OUTX (Pin 56) is inverted when FRP is low, and non-

inverted when FRP is high.

SID_OUT and SID_OUTX cannot directly drive the precharge signal input of the LCD panel, so they should be

connected via a buffer having sufficient current supply capability.

7. VCOM potential generator block

This block sets the DC common potential for the LCD panel.

VCOM_OFST (Pin 54) sets the deviation relative to the SH_OUT center potential, which is set by SIG.C.

SHST

FRP

SH_OUT

200h

000h

CAL_PLS
(internal pulse)

200ns

Video signal replacement period

Signal center

Offset cancel operation

Delayed by sample-and-hold

CXA3562R

Example of Representative Characteristics (V

= 15.5V, V

= 5.0V, Ta = 25°C)

VREF_I voltage vs. SH_OUT voltage white-black amplitude

3.2

3.1

3.0

2.9

2.8

2.7

4.6

4.5

4.3

4.2

4.4

4.1

4.0

3.9

3.8

4.8

4.7

SH_OUT white-b

lac

k amplitude v

oltage [V]

VREF_I voltage [V]

Input data vs. SH_OUT voltage

3FFh

300h

200h

100h

000h

SH_OUT v

oltage [V]

Input data (10 bits)

SIG.C voltage vs. SH_OUT center voltage

4.0

3.5

3.0

2.5

8.0

8.5

7.0

6.0

5.0

5.5

7.5

SH_OUT center v

oltage [V]

SIG.C voltage [V]

SIG_OFST voltage vs. SH_OUT voltage

5.0

2.0

2.5

3.0

3.5

4.0

4.5

1.5

1.0

0.5

SH_OUT v

oltage [V]

SIG_OFST voltage [V]

VCOM_OFST voltage vs. VCOM_OUT voltage

3.1

3.0

2.9

2.8

5.95

5.85

5.80

5.70

6.00

VCOM_OUT v

oltage [V]

VCOM_OFST voltage [V]

3.3

4.5

6.5

9.0

3.2

5.90

5.75

<Measurement conditions>
SIG.C = 3.75V
SIG_OFST = 3.6V

<Measurement conditions>
SIG_OFST = 3.6V

<Measurement conditions>
SIG.C = 3.75V

<Measurement conditions>
SIG.C = 3.75V
SIG_OFST = 3.6V

<Measurement conditions>
SIG.C = 3.75V
DATA = 200h

FRP = High

FRP = Low

FRP = High

FRP = Low

CXA3562R

Application Circuit 1 (to XGA Panel)

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

100

47µF

20k

1µF

0.1µF

10k

R1OUT9

RGT

PRG

DSD
CXD3511Q

R1OUT8

R1OUT7

R1OUT6

R1OUT5

R1OUT4

R1OUT3

R1OUT2

R1OUT1

R1OUT0

FRP

SHST

CLKH

CXA3266Q

CLKL

D_A9

TEST

SL_INV

SL_SCN

SL_D

DIRC

F/H_CNT

VREF_O

VREF_I

GND

PRG

SID_L

PRG_L

SID_OUT

SID_OUTX

VCOM_OFST

VCOM_OUT

SH_OUT1

SH_OUT2

SH_OUT3

SH_OUT4

SH_OUT5

SH_OUT6

GND

D_A8

D_A7

D_A6

D_A5

D_A4

D_A3

D_A2

D_A1

D_A0

GND

CXA3562R

GND

D_B9

D_B8

D_B7

D_B6

D_B5

D_B4

D_B3

D_B2

D_B1

D_B0

20k

0.1µF

20k

GND

PGND

GND

SH_OUT7

SH_OUT8

SH_OUT9

SH_OUT10

SH_OUT11

47µF

0.1µF

10k

TEST

POSCTR0

MCLK

MCLKX

FRP

SHST

POSCTR1

POSCTR2

POSCTR3

SHTEST

OPEN

GND

DCFBOFF

CAL_IL

CAL_IH

CAL_OH

CAL_OL

SIG_OFST

SIG.C

SH_OUT12

20k

0.1µF

1µF

20k

0.1µF

15.5V

121

122

111

112

113

116

117

118

119

120

157

159

130

Vsig12

Vsig11

Vsig10

Vsig9

Vsig8

Vsig7

Vsig6

LCD Panel
LCX023

Vsig5

Vsig4

Vsig3

Vsig2

Vsig1

Buffer

Psig

136

161

COM

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

CXA3562R

Application Circuit 2 (to SXGA Panel)

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

100

47µF

20k

1µF

0.1µF

10k

R1OUT9

RGT

PRG

DSD
CXD3511Q

R1OUT8

R1OUT7

R1OUT6

R1OUT5

R1OUT4

R1OUT3

R1OUT2

R1OUT1

R1OUT0

FRP

SHST

CLK/2H

CXA3266Q

CLK/2L

D_A9

TEST

SL_INV

SL_SCN

SL_D

DIRC

F/H_CNT

VREF_O

VREF_I

GND

PRG

SID_L

PRG_L

SID_OUT

SID_OUTX

VCOM_OFST

VCOM_OUT

SH_OUT1

SH_OUT2

SH_OUT3

SH_OUT4

SH_OUT5

SH_OUT6

GND

D_A8

D_A7

D_A6

D_A5

D_A4

D_A3

D_A2

D_A1

D_A0

R2OUT9

R2OUT8

R2OUT7

R2OUT6

R2OUT5

R2OUT4

R2OUT3

R2OUT2

R2OUT1

R2OUT0

GND

CXA3562R

GND

D_B9

D_B8

D_B7

D_B6

D_B5

D_B4

D_B3

D_B2

D_B1

D_B0

20k

0.1µF

20k

GND

PGND

GND

SH_OUT7

SH_OUT8

SH_OUT9

SH_OUT10

SH_OUT11

47µF

0.1µF

10k

TEST

POSCTR0

MCLK

MCLKX

FRP

SHST

POSCTR1

POSCTR2

POSCTR3

SHTEST

OPEN

GND

DCFBOFF

CAL_IL

CAL_IH

CAL_OH

CAL_OL

SIG_OFST

SIG.C

SH_OUT12

20k

0.1µF

1µF

20k

0.1µF

15.5V

121

122

111

112

113

116

117

118

119

120

157

159

130

Vsig12

Vsig11

Vsig10

Vsig9

Vsig8

Vsig7

Vsig6

LCD Panel
LCX028

Vsig5

Vsig4

Vsig3

Vsig2

Vsig1

Buffer

Psig

136

161

COM

COML

COMR

103

104

105

106

107

108

109

110

CXA3562R

Application Circuit 3 (to WXGA Panel)

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

100

47µF

20k

1µF

0.1µF

10k

R1OUT9

RGT

DSD
CXD3511Q

R1OUT8

R1OUT7

R1OUT6

R1OUT5

R1OUT4

R1OUT3

R1OUT2

R1OUT1

R1OUT0

FRP

SHST

CLK/2H

CXA3266Q

CLK/2L

D_A9

TEST

SL_INV

SL_SCN

SL_D

DIRC

F/H_CNT

VREF_O

VREF_I

GND

PRG

SID_L

PRG_L

SID_OUT

SID_OUTX

VCOM_OFST

VCOM_OUT

SH_OUT1

SH_OUT2

SH_OUT3

SH_OUT4

SH_OUT5

SH_OUT6

GND

D_A8

D_A7

D_A6

D_A5

D_A4

D_A3

D_A2

D_A1

D_A0

R2OUT9

R2OUT8

R2OUT7

R2OUT6

R2OUT5

R2OUT4

R2OUT3

R2OUT2

R2OUT1

R2OUT0

GND

CXA3562R

GND

D_B9

D_B8

D_B7

D_B6

D_B5

D_B4

D_B3

D_B2

D_B1

D_B0

20k

0.1µF

GND

PGND

GND

SH_OUT7

SH_OUT8

SH_OUT9

SH_OUT10

SH_OUT11

47µF

0.1µF

10k

TEST

POSCTR0

MCLK

MCLKX

FRP

SHST

POSCTR1

POSCTR2

POSCTR3

SHTEST

OPEN

GND

DCFBOFF

CAL_IL

CAL_IH

CAL_OH

CAL_OL

SIG_OFST

SIG.C

SH_OUT12

20k

0.1µF

1µF

20k

0.1µF

15.5V

121

122

111

112

113

116

117

118

119

120

157

159

130

Vsig-b6

Vsig-b5

Vsig-b4

Vsig-b3

Vsig-b2

Vsig-b1

Vsig-a6

LCD Panel
LCX037

Vsig-a5

Vsig-a4

Vsig-a3

Vsig-a2

Vsig-a1

Buffer

Another
CXA3562R

SID_OUTX

SID_OUT

Psig1

Psig2

Psig3

Psig4

136

COM

COML

COMR

103

104

105

106

107

108

109

110

CXA3562R

Application Circuit 4 (to UXGA Panel)

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

100

47µF

0.47µF

0.1µF

10k

R1OUT9

RGT

DSD
CXD3511Q

R1OUT8

R1OUT7

R1OUT6

R1OUT5

R1OUT4

R1OUT3

R1OUT2

R1OUT1

R1OUT0

FRP

SHST

R2OUT9

R2OUT8

R2OUT7

R2OUT6

R2OUT5

R2OUT4

R2OUT3

R2OUT2

R2OUT1

R2OUT0

XFRP

CLK/2H

CXA3266Q

CLK/2L

D_A9

TEST

SL_INV

SL_SCN

SL_D

DIRC

F/H_CNT

VREF_O

VREF_I

GND

SID_OUT

SID_OUTX

VCOM_OFST

VCOM_OUT

SH_OUT1

SH_OUT2

SH_OUT3

SH_OUT4

SH_OUT5

SH_OUT6

GND

D_A8

D_A7

D_A6

D_A5

D_A4

D_A3

D_A2

D_A1

D_A0

GND

CXA3562R

GND

D_B9

D_B8

D_B7

D_B6

D_B5

D_B4

D_B3

D_B2

D_B1

D_B0

GND

PGND

GND

SH_OUT7

SH_OUT8

SH_OUT9

SH_OUT10

SH_OUT11

47µF

0.1µF

10k

TEST

POSCTR0

MCLK

MCLKX

FRP

SHST

POSCTR1

POSCTR2

POSCTR3

SHTEST

OPEN

GND

DCFBOFF

CAL_IL

CAL_IH

CAL_OH

CAL_OL

SIG_OFST

SIG.C

SH_OUT12

OPEN

20k

0.1µF

0.47µF

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

100

47µF

20k

0.47µF

0.1µF

10k

D_A9

TEST

SL_INV

SL_SCN

SL_D

DIRC

F/H_CNT

VREF_O

VREF_I

GND

PRG

SID_L

PRG_L

SID_OUT

SID_OUTX

VCOM_OFST

VCOM_OUT

SH_OUT1

SH_OUT2

SH_OUT3

SH_OUT4

SH_OUT5

SH_OUT6

GND

D_A8

D_A7

D_A6

D_A5

D_A4

D_A3

D_A2

D_A1

D_A0

GND

D_B9

D_B8

D_B7

D_B6

D_B5

D_B4

D_B3

D_B2

D_B1

D_B0

20k

0.1µF

GND

PGND

GND

SH_OUT7

SH_OUT8

SH_OUT9

SH_OUT10

SH_OUT11

47µF

0.1µF

10k

TEST

POSCTR0

MCLK

MCLKX

FRP

SHST

POSCTR1

POSCTR2

POSCTR3

SHTEST

GND

DCFBOFF

CAL_IL

CAL_IH

CAL_OH

CAL_OL

SIG_OFST

SIG.C

SH_OUT12

20k

0.1µF

15.5V

0.1µF

0.47µF

Buffer

121

122

111

112

113

116

117

118

119

120

103

104

105

106

107

108

109

110

157

159

130

158

Sig24

Sig22

Sig20

Sig18

Sig16

Sig14

Sig12

Sig10

Sig8

Sig6

Sig4

VSig2

COM2

Vsig23

Vsig21

Vsig19

Vsig17

Vsig15

Vsig13

Vsig11

LCD Panel
LCX036

Vsig9

Vsig7

Vsig5

Vsig3

Vsig1

COM1

Psig3

Psig4

Buffer

Psig1

Psig2

136

20k

0.1µF

SID_L

PRG_L

20k

PRG

161

0.1µF

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA3562R

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXA3562R