Description

CXD1172AM/AP is a 6-bit CMOS A/D converter for

video use. The adoption of a 2-step parallel system

achieves low consumption at a maximum conversion

speed of 20MSPS minimum, 35MSPS typical.

Features

· Resolution: 6-bit

1/2LSB

· Max. sampling frequency: 20MSPS

· Low power consumption: 40mW (at 20MSPS typ.)

(Reference current excluded)

· Built-in sampling and hold circuit.

· 3-state TTL compatible output.

· Power supply: 5V single

· Low input capacitance: 4pF

· Reference impedance: 250

(typ.)

Applications

TV, VCR digital systems and a wide range of fields

where high speed A/D conversion is required.

Structure

Silicon gate CMOS monolithic IC

Absolute Maximum Ratings (Ta = 25°C)

· Supply voltage

· Reference voltage

, V

+ 0.5 to V

0.5 V

· Input voltage

+ 0.5 to V

0.5 V

(Analog)

· Input voltage

CLK

+ 0.5 to V

0.5 V

(Digital)

· Output voltage

, V

+ 0.5 to V

0.5 V

(Digital)

· Storage temperature

Tstg

55 to +150

°C

Recommended Operating Conditions

· Supply voltage

, AV

4.75 to 5.25

, DV

4.75 to 5.25

· Reference input voltage

0 to 4.1

0.9 to 5.0

0.9 to AV

· Analog input voltage

to V

· Clock pulse width

PW1

, T

PW0

23ns (min.) to 1.1µs (max.)

· Operating temperature

Topr

20 to +75

°C

E89320C78-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXD1172AM/AP

6-bit 20MSPS Video A/D Converter (CMOS)

CXD1172AM

16 pin SOP (Plastic)

CXD1172AP

16 pin DIP (Plastic)

CXD1172AM/AP

Block Diagram and Pin Configuration

Pln Description and Equivalent Circuits

Reference voltage

Lower

Sampling comparators

(3BIT)

Lower

Sampling comparators

(3BIT)

Upper

Sampling comparators

(3BIT)

Lower encoder

(3BIT)

Lower encoder

(3BIT)

Upper encoder

(3BIT)

Lower data

latchs

Upper data

latchs

Clook generator

VRB

VRT

CLK

No. Symbol

Equivalent

Circuit

Description

(LSB) to D

(MSB) output

1 to 6

to D

Analog input

Analog GND

Clock input

9, 15

10, 14

Digital GND

Digital +5V

Analog +5V

CLK

Reference voltage (Top)

Reference voltage (Bottom)

VRT

VRB

CXD1172AM/AP

Electrical Characteristics

= 5V, V

= 1.0V, V

= 2.0V, Ta = 25°C)

Conversion speed

Supply current

Reference pin current

Analog input band width
(1dB)

Analog input capacitance

Reference resistance
(V

to V

)

Offset voltage

Digital input voltage

Digital input current

Digital output current

Output data delay

Integral non-linearity error

Differential non-linearity
error

Differential gain error

Differential phase error

Aperture jitter

Sampling delay

0.5

175

4.0

1.1

3.7

= 4.75 to 5.25V

Ta = 20 to +75°C
V

= 1.0 to 2.0V

= 1kHz ramp

Fc = 20MSPS
NTSC ramp wave input

Envelope

= 1.5V + 0.07Vrms

Potential difference to VRT

Potential difference to VRB

= 4.75 to 5.25V

Ta = 20 to +75°C

= max.

= min.

With TTL 1 gate and 10pF load
Ta = 20 to +75°C
V

= 4.75 to 5.25V

End point

NTSC 40 IRE mod ramp
Fc = 14.3MSPS

250

0.3

1.0

5.7

325

1.0

0.5

MSPS

MHz

µA

LSB

deg

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

The offset voltage EOB is a potential difference between VRB and a point of position where the voltage

drops equivalent to 1/2 LSB of the voltage when the output data changes from "00000000" to "00000001".

EOT is a potential difference between VRT and a potential of point where the voltage rises equivalent to

1/2 LSB of the voltage when the output data changes from "11111111" to "11111110".

= V

= 0V

= V

+ 0.5V

= 0.4V

REF

Taj

Tsd

CXD1172AM/AP

Integral non-linearity error

Differential non-linearity

}

Test Circuit

Offset voltage

CXD1172A

A < B

A > B

COMPARATOR

BUFFER

DVM

CONTROLLER

CLK (20MHz)

: ON

A < B

: ON

B > A

B1
B0

"0"

"1"

000

...

111

...

Maximum operational speed

Differential gain error

}

Test Circuit

Differential phase error

S. G.

NTSC

SIGNAL

SOURCE

S. G.
(CW)

TTL

ECL

CXD
1172A

10bit

D/A

TTL

ECL

COUNTER

ERROR RATE

VECTOR
SCOPE

H. P. F

620

5.2V

CX20202A-1

5.2V

CLK

620

AMP

100

1.0V

2.0V

40 IRE
MODULATION

BURST

SYNC

IAE

2.0V

1.0V

1kHz

D. G
D. P

Digital output current test circuit

CLK

GND

2.0V

1.0V

CLK

GND

2.0V

1.0V

Electrical Characteristics Test Circuit

CXD1172AM/AP

Operation (See Block Diagram and Timing Chart)

1. CXD1172AM/AP is a 2-step parallel system A/D converter featuring a 3-bit upper comparators group and 2

Iower comparators groups of 3-bit each. The reference voltage that is equal to the voltage between VRT-

VRB/8 is constantly applied to the upper 3-bit comparator block. Voltage that corresponded to the upper

data is fed through the reference supply to the lower data.

2. This IC uses an offset cancel type comparator and operates synchronously with an external clock. It features

the following operating modes which are respectively indicated on the timing chart with S, H, C symbols.

That is input sampling (auto zero) mode, input hold mode and comparison mode.

3. The operation of respective parts is as indicated in the chart. For instance input voltage Vi (1) is sampled with

the falling edge of the first clock by means of the upper comparator block and the Iower comparator A block.

The upper comparators block finalizes comparison data MD (1) with the rising edge of the first clock.

Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to the

upper results. The lower comparator block finalizes comparison data LD (1) with the rising edge of the

second clock. MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the 3rd clock.

Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output.

Operation Notes

1. V

, Vss

To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and

analog V

pins, use a ceramic capacitor of about 0.1µF set as close as possible to the pin to bypass to the

respective GND's.

2. Analog input

Compared with the flash type A/D converter, the input capacitance of the analog input is rather small.

However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability.

When driving with an amplifier of low output impedance, parasite oscillation may occur. That may be

prevented by inserting a resistance of about 100

in series between the amplifier output and A/D input.

3. Clock input

The clock line wiring should be as short as possible also, to avoid any interference with other signals,

separate it from other circuits.

4. Reference input

Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and

VRB pins to GND, by means of a capacitor about 0.1µF, stable characteristics are obtained.

5. Timing

Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks and

with the following rising edge. The delay from the clock rising edge to the data output is about 18ns.

6. About latch up

It is necessary that AV

and DV

pins be the common source of power supply.

This is to avoid latch up due to the voltage difference between AV

and DV

pins when power is ON.

See "For latch up prevention" of CXD1172P/CXA1106P PCB description. (Page 6, 7)

CXD1172AM/AP

Latch Up Prevention

The CXD1172A is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in

the voltage rising time of AV

(Pins 10 and 14) and DV

(Pins 9 and 15), when power supply is ON.

1. Correct usage

a. When analog and digital supplies are from different sources

+5V

C14

DIGITAL IC

CXD1172A

b. When analog and digital supplies are from a common source

(i)

+5V

C14

DIGITAL IC

CXD1172A

(ii)

+5V

C14

DIGITAL IC

CXD1172A

CXD1172AM/AP

Package Outline

Unit: mm

CXD1172AM

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

SONY CODE

EIAJ CODE

JEDEC CODE

SOP-16P-L01

SOP016-P-0300-A

COPPER ALLOY

SOLDER PLATING

EPOXY RESIN

16PIN SOP (PLASTIC) 300mil

9.9 0.1

+ 0.4

1.27

0.45 ± 0.1

5.3 0.1

+ 0.3

7.9 ±

0.4

6.9

1.85 0.15

+ 0.4

0.5 ±

0.2

0.2 0.05

+ 0.1

0.1 0.05

+ 0.2

0.2g

0.15

± 0.12

CXD1172AP

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN

SOLDER PLATING

COPPER ALLOY

19.2 0.1

+ 0.4

2.54

0.5 ± 0.1

1.2 ± 0.15

3.0 MIN

0.5 MIN

3.7 0.1

+ 0.4

6.4 0.1

+ 0.3

7.62

0.25 0.05

+ 0.1

0° to 15°

16PIN DIP (PLASTIC)

1.0 g

SONY CODE

EIAJ CODE

JEDEC CODE

DIP-16P-01

DIP016-P-0300

Similar to MO-001-AE

1.All mat surface type.

Two kinds of package surface:

2.All mirror surface type.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXD1172AP

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXD1172AP