--1--
E91845B67-TE
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any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CCD Camera Synchronization and Timing Signal Generator
CXD1254AR/AQ
Absolute Maximum Ratings (Ta=25 C, V
SS
=0 V)
Supply voltage
V
SS
0.5 to +7.0
V
Input voltage
V
SS
0.5 to V
DD
+0.5
V
Output voltage
V
SS
0.5 to V
DD
+0.5
V
Operating temperature
20 to +75
C
Storage temperature
55 to +150
C
Recommended Operating Conditions
Supply voltage
4.75 to 5.25
V
Operating temperature
20 to +75
C
Description
The CXD1254AR and CXD1254AQ Ics generates
the necessary synchronization and timing signals for
camera systems employing CCD image sensors
(ICX044, ICX045, ICX046, etc.).
Features
Supports color (NTSC) and black & white
(EIA/CCIR) systems
On-chip electronic shutter
On-chip horizontal (H) driver
Timing generator for mirror images
Applications
CCD camera systems
Structure
Silicon gate CMOS IC
CXD1254AR
CXD1254AQ
64 pin LQFP (Plastic)
64 pin QFP (Plastic)
--2--
CXD1254AR/AQ
Block Diagram (Pin No.s given for CXD1254AR)
TEST
GENERATOR
RESET
GENERATOR
1/7 or 1/6
COUNTER
H-DECODER
1/525 or 1/625
COUNTER
V-DECODER
V-CONTROL
OUTPUT CONTROL
H-INIT
V-RELATIVE
COUNTER
V-ROM
(VD1)
LATCH
H-RELATIVE COUNTER
LATCH
ADDRESS
COUNTER
H-ROM
(HD1)
H-ROM
(HD2)
H-ROM
(HD3)
H-ROM
(RD1)
H-ROM
(RD2)
48
49
54
58
52
1/65 COUNTER
3
1
2
H-RELATIVE COUNTER
V-INIT
LATCH
LATCH
LATCH
LATCH
ADDRESS
COUNTER
62
63
64
6
4
5
RESET
CK
GENERATION
1/3
1/2
11
10
9
PHASE CONT.
SERIAL-
PARALLEL
CONVERTER
GATE
SHUTTER
ROM
COUNTER/GATE
SELECT
GATE
GATE
GATE
16
13
12
14
15
27
29
26
31
21
23
33
34
35
36
18
20
37
38
19
25
39
45
46
28
30
TEST2
TEST3
EXT
TEST1
FLD
HD
VD
C KIN
OSCI
OSCO
CL
PS
ED0
ED1
ED2
ENB
D1
D2
D3
BF
CBLK
SYNC
41
43
42
44
XDL1
XDL2
H1
H2
H3
H4
XSHD
XSHP
XSP1
XSP2
RG
XSUB
PBLK
BFG
ID
CLP1
CLP2
CLP3
CLP4
XV1
XV2
XV3
XV4
XSG1
XSG2
--3--
CXD1254AR/AQ
Pin Configuration (1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
59
58
60
61
62
63
64
17
18
20
21
22
23
24
25
26
27
28
29
30
31
32
19
CXD1254AR
FLD
HTSG
V
DD
EXT
V
SS
TEST2
NC
V
DD
NC
TEST3
V
SS
NC
NC
BF
CBLK
SYNC
V
SS
XV4
XSG2
XV3
XSG1
XV1
XV2
XSUB
V
DD
RG
AV
SS
H4
H3
H2
H1
AV
DD
TEST1
V
DD
ID
PBLK
CLP4
CLP3
CLP2
CLP1
V
SS
BFG
XDL2
XDL1
XSP2
XSP1
XSHD
XSHP
HD
VD
CL
D1
D2
D3
TRIG
V
SS
OSCI
OSCO
CKIN
ENB
ED0
ED1
ED2
PS
Mode
D1
D2
D3
ENB
ED0
ED1
ED2
PS
EXT
TEST2
Pin No.
4
5
6
12
13
14
15
16
52
54
PRESET
Low
Low
Low
High
High
High
High
High
Low
Low
Low
High
NTSC/EIA
CCIR
Normal Image
Mirror Image
Color
B/W
Normal
Shutter
Shutter Speed
Serial input
Parallel input
Internal
External
Normally Low
--4--
CXD1254AR/AQ
Pin Configuration (2)
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
59
58
60
61
62
63
64
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CXD1254AQ
HTSG
V
DD
EXT
V
SS
TEST2
NC
V
DD
NC
TEST3
V
SS
NC
NC
BF
XSG2
XV3
XSG1
XV1
XV2
XSUB
V
DD
RG
AV
SS
H4
H3
H2
H1
CBLK
SYNC
HD
VD
CL
D1
D2
D3
TRIG
V
SS
OSCI
OSCO
CKIN
ENB
ED0
ED1
ED2
PS
AV
DD
FLD
TEST1
V
DD
ID
PBLK
CLP4
CLP3
CLP2
CLP1
V
SS
BFG
XDL2
XDL1
XSP2
XSP1
XSHD
XSHP
V
SS
XV4
Mode
D1
D2
D3
ENB
ED0
ED1
ED2
PS
EXT
TEST2
Pin No.
6
7
8
14
15
16
17
18
54
56
PRESET
Low
Low
Low
High
High
High
High
High
Low
Low
Low
High
NTSC/EIA
CCIR
Normal Image
Mirror Image
Color
B/W
Normal
Shutter
Shutter Speed
Serial input
Parallel input
Internal
External
Normally Low
--5--
CXD1254AR/AQ
Pin Description
Pin No.
LQFP QFP
1
3
2
4
3
5
4
6
5
7
6
8
7
9
8
10
9
11
10
12
11
13
12
14
13
15
14
16
15
17
16
18
17
19
18
20
19
21
20
22
21
23
22
24
23
25
24
26
25
27
26
28
27
29
28
30
29
31
30
32
31
33
32
34
33
35
34
36
35
37
36
38
37
39
38
40
39
41
40
42
Pin
HD
VD
CL
D1
D2
D3
TRIG
V
SS
OSCI
OSCO
CKIN
ENB
ED0
ED1
ED2
PS
AV
DD
H1
H2
H3
H4
AV
SS
RG
V
DD
XSUB
XV2
XV1
XSG1
XV3
XSG2
XV4
V
SS
XSHP
XSHD
XSP1
XSP2
XDL1
XDL2
BFG
V
SS
I/O
O
O
O
I
I
I
I
--
I
O
I
I
I
I
I
I
--
O
O
O
O
--
O
--
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
--
Function
Horizontal drive pulse output
Vertical drive pulse output
Clock output
NTSC/EIA: 14.318 MHz CCIR: 14.1875 MHz
Mode selection
"Low": NTSC/EIA "High": CCIR
(Pull-down resistor)
Mode selection
"Low": Normal "High": Mirror
(Pull-down resistor)
Mode selection
"Low": Color "High": B/W
(Pull-down resistor)
Shutter speed setting pulse input
(Pull-up resistor)
GND for signal generator
Oscillator input
NTSC/EIA: 28.636 MHz CCIR: 28.375 MHz
Oscillator output
Input for determining oscillator duty cycle
Shutter selection "Low": Normal "High": Shutter
(Pull-up resistor)
Shutter speed control
(Pull-up resistor)
Shutter speed control
(Pull-up resistor)
Shutter speed control
(Pull-up resistor)
Shutter speed setting data format selection
"Low": Serial
"High": Parallel
(Pull-up resistor)
Independent power supply for horizontal driver
Clock output for horizontal register driver
Clock output for horizontal register driver (Leave open except for ICX046.)
Clock output for horizontal register driver (Use as H2 except for ICX046.)
Clock output for horizontal register driver (Leave open except for ICX046.)
Independent GND for horizontal driver
Reset gate pulse output
Power supply for timing generator
Sensor charge sweep output pulse output
Clock output for vertical register driver
Clock output for vertical register driver
Sensor charge readout pulse output
Clock output for vertical register driver
Sensor charge readout pulse output
Clock output for vertical register driver
GND for timing generator
Pre-charge level/sample-and-hold pulse output
1
Data sample-and-hold pulse output
1
Color separation sample-and-hold pulse output
1
Color separation sample-and-hold pulse output
1
Pulse output for delay line
1
Pulse output for delay line
1
Burst flag gate pulse output
GND for timing generator
--6--
CXD1254AR/AQ
Pin No.
LQFP QFP
41
43
42
44
43
45
44
46
45
47
46
48
47
49
48
50
49
51
50
52
51
53
52
54
53
55
54
56
55
57
56
58
57
59
58
60
59
61
60
62
61
63
62
64
63
1
64
2
Pin
CLP1
CLP2
CLP3
CLP4
PBLK
ID
V
DD
TEST1
FLD
HTSG
V
DD
EXT
V
SS
TEST2
NC
V
DD
NC
TEST3
V
SS
NC
NC
BF
CBLK
SYNC
I/O
O
O
O
O
O
O
--
I
I/O
I
--
I
--
I
--
--
--
I
--
--
--
O
O
O
Function
Pulse output for clamp
Pulse output for clamp
Pulse output for clamp
Pulse output for clamp
Blanking/cleaning pulse output
Line discrimination pulse output
Power supply for timing generator
Test input/H reset pulse input
2
Field pulse output/V reset pulse input
2
XSG1, 2 controller/Test input
2
Power supply for signal generator
Synchronization mode selection.
"Low": Internal
"High": External
(Pull-down resistor)
GND for signal generator
Test input (Normally open)
(Pull-down resistor)
Used open
Power supply for signal generator
Used open
Test input (Normally fixed at "Low")
GND for signal generator
Used open
Used open
Burst flag pulse output
Composite blanking pulse output
Composite synchronization pulse output
(Note)
1...Output determined by mode setting.
2...Function determined by mode setting.
Outputs for Pins Determined by Mode Setting
1
Pin
XSHP
XSHD
XSP1
XSP2
XDL1
XDL2
Pin No.
(LQFP)
33
34
35
36
37
38
XSHP (
) output
XSHD (
) output
XSP1 (
) output
XSP2 (
) output
XDL1 output
XDL2 output
O
O
O
O
O
O
O
O
O
O
O
O
SHP (
) output
SHD (
) output
(Out put stopped)
(Out put stopped)
(Out put stopped)
(Out put stopped)
D3 (Pin 6)
Low (Color)
High (B/W)
--7--
CXD1254AR/AQ
Functions for Pins Determined by Mode Settings
2
Pin
TEST1
FLD
HTSG
Pin No.
(LQFP)
48
49
50
Test input (Normally low)
FLD output
XSG1, 2 control input
("Low" : OFF "High" : ON)
I
O
I
I
I
I
H reset pulse input
V reset pulse input
Test input (Normally low)
EXT (Pin 11)
Low (Internal)
High (External)
Electrical Characteristics
1) DC Characteristics
(V
DD
=5 V 0.25 V, Topr= 20 to +75 C)
Item
Supply voltage
Input voltage
Output voltage 1
Output voltage 2
CL, RG, XSHP, XSHD, XSP1,
XSP2, XDL1, XDL2
Output voltage 3
H1, H2, H3, H4
Output voltage 4
OSC0
Feedback resistance
Pull-up resistor
Pull-down resistor
Symbol
V
DD
V
IH1
V
IL1
V
OH1
V
OL1
V
OH2
V
OL2
V
OH3
V
OL3
V
OH4
V
OL4
R
FB
R
PU
R
PD
Conditions
I
OH
=2 mA
I
OL
=4 mA
I
OH
=4 mA
I
OL
=8 mA
I
OH
=8 mA
I
OL
=8 mA
I
OH
=1 mA
I
OL
=1 mA
V
IN
=V
SS
or V
DD
V
IL
=0 V
V
IH
=V
DD
Min.
4.75
0.7 V
DD
V
DD
0.5
V
DD
0.5
V
DD
0.5
V
DD
/2
500 k
40 k
40 k
Typ.
5.0
2 M
100 k
100 k
Max.
5.25
0.3 V
DD
0.4
0.4
0.4
V
DD
/2
5 M
250 k
250 k
Unit
V
V
V
V
V
V
V
V
V
V
V
Item
Input pin capacitance
Output pin capacitance
Input/Output pin capacitance
Symbol
C
IN
C
OUT
C
I/O
Min.
Typ.
Max.
9
11
11
Unit
pF
pF
pF
2) Input/Output Capacitance
(V
DD
=V
I
=0 V, f
M
=1 MHz)
--8--
CXD1254AR/AQ
Electronic Shutter Description
Pins for Shutter
PS, TRIG, ENB
Inputs for overall mode setting
XSUB
Output
ED0, ED1, ED2
Inputs for shutter speed setting
(Note)
Regardless of shutter speed setting controlled by PS, ED0 to ED2, and TRIG, if ENB is "Low", the shutter
will be OFF.
The speed set by PS and ED0 to ED2 is subject to control by TRIG.
Mode Description
1. TRIG (Pull-up resistor)
For normal shutter operation, TRIG should be either left Open or set at High.
For continuous variable shutter operation, input a clock pulse to TRIG.
By taking out XSUB pulses between downward pulses of XSG1 and TRIG, and thus stopping XSUB pulses
from the downward pulse of TRIG to the following downward pulse of XSG1, the shutter speed is determined.
In order to increase the range of control when the TRIG pin is used to control the shutter speed, Pins ED0 to
ED2 (described in next section) must be pre-set to 1/10000 sec. (Described in later section.)
2. ED0, ED1, and ED2 (Shutter speed control)
PS (Selects between parallel/serial input)
ENB (Shutter mode selection)
2-1. PS
Selects either parallel or serial input data format to be used for determining shutter speed.
Parallel input
Combination of the 3 bits, ED0, ED1, ED2, yields 8 possible shutter speed settings.
Serial input
Shutter speed is determined by inputting ED0 (strobe), and ED1 (clock), and ED2
(data) to respective pins.
Shutter speded
VD
HD
XSGI
TRIG
XSUB
--9--
CXD1254AR/AQ
2-1-1. [Parallel input] (PS = H) -- For high speed shutter only
Table of Shutter Settings
2-1-2. [Serial input] (PS = L)
The combination of serial data SMD1 and SMD2 can be used to select one of four modes.
Shutter Mode
Flickerless
Mode for eliminating flicker caused by oscillation frequency of fluorescent lights.
High-speed shutter
Shutter speed faster than 1/60 sec. (NTSC/EIA) or 1/50 sec. (CCIR).
Low-speed shutter
Shutter speed slower than 1/60 sec. (NTSC/EIA) or 1/50 sec. (CCIR).
No shutter
Shutter operation inactive.
ED2 data is latched in the register on the rising edge of ED1 and the register contents are transferred during
the low period of ED0.
D1
X
L
H
L
H
X
X
X
X
X
X
ENB
L
H
H
H
H
H
H
H
H
H
H
ED0
X
H
H
L
L
H
L
H
L
H
L
ED1
X
H
H
H
H
L
L
H
H
L
L
ED2
X
H
H
H
H
H
H
L
L
L
L
Shutter speed
Shutter OFF
1/60 (s)
1/50 (s)
1/100 (s)
1/120 (s)
1/250 (s)
1/500 (s)
1/1000 (s)
1/2000 (s)
1/4000 (s)
1/10000 (s)
Mode
SMD1
SMD2
Flickerless
Low
Low
High-speed shutter
Low
High
Low-speed shutter
High
Low
No shutter
High
High
ED1 (CLK)
ED2 (OATA)
EDO (STB)
D0
D1
D2
D3
D4
D5
D6
D7
D8
SMD1 SMD2
Dummy
--10--
CXD1254AR/AQ
AC Characteristics
t
s2
t
h2
t
s1
t
s0
t
W0
ED2
ED1
ED0
Symbol
t
s2
t
h2
t
s2
t
w0
t
s0
ED2 set-up time referenced from the ED1 rising edge
ED2 hold-time referenced from the ED1 rising edge
ED1 rise set-up time referenced from the ED0 rising edge
ED0 pulse width
ED0 rise set-up time referenced from the ED1 rising edge
Min.
20 ns
20 ns
20 ns
20 ns
20 ns
Max.
--
--
--
50 s
--
2-1-3. [Shutter speed calculation formula]
High-speed Shutter
For NTSC/EIA
T= [262
10
(1FF
16
L
16
)]
63.56 + 34.78 s
L
16
: Load value
For CCIR
T= [312
10
(1FF
16
L16)]
64 + 35.6 s
NTSC/EIA
Load value
Shutter speed
Calculated value
0FA
16
1/10000
1/10169
0FC
16
1/4000
1/4435
100
16
1/2000
1/2085
108
16
1/1000
1/1012
118
16
1/500
1/499
137
16
1/250
1/252
176
16
1/125
1/125
196
16
1/100
1/100
CCIR
Load value
Shutter speed
Calculated value
0C8
16
1/10000
1/10040
0CA
16
1/4000
1/4349
0CE
16
1/2000
1/2068
0D6
16
1/1000
1/1004
0E6
16
1/500
1/495
105
16
1/250
1/250
143
16
1/125
1/125
149
16
1/100
1/120
Low-speed Shutter
N = 2
(1FF
16
L
16
) FLD
"1FF" cannot be used as a load value.
Load value
1FE
16
1FD
16
:
101
16
100
16
Shutter speed (FLD)
2
4
:
508
510
--11--
CXD1254AR/AQ
External Synchronization Mode Description
H Reset
The reset process is started from the first falling edge of the inputted reset pulse. The next reset occurs
only when there is a divergence of at least a clock cycles (0.98 s) from the edge.
The minimum reset pulse width is 0.98 s.
The HD output reset position leads the H reset input by 2.45 to 2.94 s.
V Reset
The VD output reset position leads the falling edge of the V reset input by 3.5 to 4.0 H for NTSC/EIA and by
3.0 to 3.5 H for PAL.
The minimum reset pulse width is 32 s.
1H
0.98s and over
2.45 to 2.94s
HD pulse reset at the falling edge of 0.98s and over
H reset input
HD output
1V
32s and over
V reset input
VD output
9H
3.5 to 4.0H (NTSC/EIA)
3.0 to 3.5H (CCIR)
--12--
CXD1254AR/AQ
Timing Chart (1) <NTSC/EIA vertical direction>
ODD Field
For EIA (black & white), the TG system output follows the VD switching point by 1H. (for both ODD and EVEN.)
BLK
FLD
VD
HD
SYNC
BF
XSG1
XSG2
XV1
XV2
XV3
XV4
PBLK
CLP1
CLP2
CLP3
CLP4
ID
BFG
--13--
CXD1254AR/AQ
EVEN Field
BLK
FLD
VD
HD
SYNC
BF
XSG1
XSG2
XV1
XV2
XV3
XV4
PBLK
CLP1
CLP2
CLP3
CLP4
ID
BFG
--14--
CXD1254AR/AQ
Timing Chart (2) <CCIR vertical direction>
ODD Field
FL
D
BL
K
VD
SYN
C
B
F
(
41)
B
F
(
23)
XSG
1
XSG
2
XV1
XV2
XV3
XV4
PBL
K
CLP
1
CLP
2
CLP
3
CLP
4
ID
BF
G
HD
--15--
CXD1254AR/AQ
EVEN Field
FL
D
BL
K
VD
SYN
C
B
F
(
34)
B
F
(
12)
XSG
1
XSG
2
XV1
XV2
XV3
XV4
PBL
K
CLP
1
CLP
2
CLP
3
CLP
4
ID
BF
G
HD
--16--
CXD1254AR/AQ
NTSC/EIA Normal Mode H Direction Timing Chart
Timing Chart (3) <NTSC/EIA horizontal direction, normal mode>
HD
H
SYN
C
BF
BL
K
EQ
VSYN
C
CL
CLK
H1
H2
H3
H4
RG
XSH
P
XSH
D
SH
P
SH
D
XSP1
XSP2
XD
L
1
XD
L
2
XV1
XV2
XV3
XV4
PBL
K
CLP
1
CLP
2
CLP
3
CLP
4
ID
BF
C
XSU
B
B/
W
Color
--17--
CXD1254AR/AQ
NTSC/EIA Mirror Mode H Direction Timing Chart
Timing Chart (4) <NTSC/EIA horizontal direction, mirror mode>
HD
BL
K
H
SYN
C
EQ
VSYN
C
BF
CL
CLK
H1
H2
H3
H4
RG
XSH
P
XSH
D
SH
P
SH
D
XSP1
XSP2
XD
L
1
XD
L
2
XV1
XV2
XV3
XV4
PBL
K
CLP
1
CLP
2
CLP
3
CLP
4
ID
BF
C
XSU
B
B/
W
Color
--18--
CXD1254AR/AQ
CCIR Normal Mode H Direction Timing Chart
Timing Chart (5) <CCIR horizontal direction, normal mode>
HD
BL
K
H
SYN
C
EQ
VSYN
C
BF
CL
CLK
H1
H2
H3
H4
RG
XSH
P
XSH
D
SH
P
SH
D
XSP1
XSP2
XD
L
1
XD
L
2
XV1
XV2
XV3
XV4
PBL
K
CLP
1
CLP
2
CLP
3
CLP
4
ID
BF
C
XSU
B
--19--
CXD1254AR/AQ
CCIR Mirror Mode H Direction Timing Chart
Timing Chart (6) <CCIR horizontal direction, mirror mode>
HD
BL
K
H
SYN
C
EQ
VSYN
C
BF
CL
CLK
H1
H2
H3
H4
RG
XSH
P
XSH
D
SH
P
SH
D
XSP1
XSP2
XD
L
1
XD
L
2
XV1
XV2
XV3
XV4
PBL
K
CLP
1
CLP
2
CLP
3
CLP
4
ID
BF
C
XSU
B
--20--
CXD1254AR/AQ
Application Circuit
(LQFP Package)
CXD1254AR
49
50
51
52
53
54
55
56
57
59
58
60
61
62
63
64
17
18
20
21
22
23
24
25
26
27
28
29
30
31
32
19
Driver
CCD imase sensor
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Signal Processing
Shutter control
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OSC NTSC/EIA : 28.6363MHz
CCIR : 28.375MHz
Please use a clock crystal which
operates on a fundamental wave.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CXD1254AR/AQ
--21--
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY / PHENOL RESIN
PLATING
42/COPPER ALLOY
PACKAGE STRUCTURE
12.0 0.2
10.0 0.1
(0.22)
0.18 0.03
+ 0.08
0.5 0.08
1
16
17
32
33
48
49
64
0.5
0.2
(11.0)
0.127 0.02
+ 0.05
A
1.5 0.1
+ 0.2
0.1 0.1
0.5
0.2
0 to 10
64PIN LQFP (PLASTIC)
LQFP-64P-L01
QFP064-P-1010
0.3g
DETAIL A
0.1
SOLDER/PALLADIUM
NOTE: "
" Dimensions do not include mold protrusion.
SONY CODE
EIAJ CODE
JEDEC CODE
23.9 0.4
20.0 0.1
1.0
0.4 0.1
+ 0.15
14.
0
0.
1
1
19
20
32
33
51
52
64
0.15 0.05
+ 0.1
2.75 0.15
16.
3
0.1 0.05
+ 0.2
0.
8
0.
2
M
0.12
0.15
+ 0.4
17.9
0.4
+
0.
4
+ 0.35
64PIN QFP(PLASTIC)
QFP64PL01
QFP064P1420
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY RESIN
SOLDER/PALLADIUM
COPPER /42 ALLOY
PACKAGE STRUCTURE
PLATING
1.5g
Package Outline Unit : mm
CXD1254AR
CXD1254AQ
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