1
CXD1268M
E96635-PS
CCD Vertical Clock Driver
Description
The CXD1268M is a clock driver for CCD vertical
register drive.
Features
On-chip 4-channel driver.
(Binary driver
2, and trinary driver
2)
Low output ON resistance provides optimal drive
for large load capacity CCD.
Applications
CCD cameras
Structure
CMOS
Absolute Maximum Ratings (GND = 0V, Ta = 25C)
Supply voltage
V
H
V
L
to V
L
+ 25
V
Supply voltage
V
M
V
L
to V
L
+ 17
1
V
Supply voltage
V
DD
GND to GND + 7
V
Supply voltage
V
L
GND 10 to GND
V
Input voltage
V
I
0.5 to V
DD
+ 0.5
V
Input/output clamp
diode current
I
IC
, I
OC
10 to +10
mA
Maximum DC load current
I
ODC
3 to +3
mA
Maximum load capacity
C
L
to 30,000
pF/pin
Allowable power dissipation
P
D
to 200
mW
Storage temperature
Tstg
60 to +150
C
1
Use V
M
at less than V
DD
.
Recommended Operating Conditions
Supply voltage
V
H
V
M
+ 6.5 to V
M
+ 15.5
V
Supply voltage
V
L
V
M
10.0 to V
M
7.0
V
Supply voltage
V
M
0.0 to 4.0
V
Supply voltage
V
DD
4.75 to 5.25
V
High level input voltage
V
IH
2
3.5 to V
DD
V
Low level input voltage
V
IL
2
0.0 to 1.0
V
Operating temperature
Topr
10 to +60
C
2
V
DD
= 5V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
20 pin SOP (Plastic)
2
CXD1268M
Block Diagram
Level
Converter
SG
Input
Gate
XSG1
9
Level
Converter
Trinary
Driver
Trinary
Driver
Level
Converter
SG
Input
Gate
Level
Converter
12
13
15
16
18
19
V
4
V
3
V
H
GND
XV3
XSG2
2
3
5
6
8
1
V
L
V
2
V
M1
V
1
V
DD
XV1
XV2
Level
Converter
Binary
Driver
Level
Converter
Binary
Driver
20
V
M2
11
XV4
10
Pin Configuration (Top View)
11
12
13
14
15
16
17
18
19
20
2
3
4
5
6
7
8
9
10
1
V
L
V
2
V
M1
NC
V
1
V
DD
NC
XV1
XSG1
XV2
V
M2
V
4
V
3
NC
V
H
GND
NC
XV3
XSG2
XV4
3
CXD1268M
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
--
O
--
O
--
I
I
I
I
I
I
--
--
O
O
--
Low level power supply
High-voltage output (2 levels: V
M2
, V
L
)
Middle level power supply for trinary
High-voltage output (3 levels: V
H
, V
M1
, V
L
)
Input section power supply
Output control (V
1)
Output control (V
1)
Output control (V
2)
Output control (V
4)
Output control (V
3)
Output control (V
3)
GND
High level power supply for trinary
High-voltage output (3 levels: V
H
, V
M1
, V
L
)
High-voltage output (2 levels: V
M2
, V
L
)
Middle level power supply for binary
V
L
V
2
V
M1
NC
V
1
V
DD
NC
XV1
XSG1
XV2
XV4
XSG2
XV3
NC
GND
V
H
NC
V
3
V
4
V
M2
Symbol
I/O
Description
Truth Table
Input
XV1, XV3
H
H
L
L
X
X
L
H
L
H
X
X
X
X
X
X
L
H
V
L
V
L
V
H
V
M1
X
X
X
X
X
X
V
M2
V
L
XSG1, XSG2
XV2, XV4
V
1, V
3
V
2, V
4
Output
X: Don't care
4
CXD1268M
Electrical Characteristics
1. DC Characteristics
(Unless otherwise specified, V
H
= 14.5V, V
M
= 1V, V
DD
= 5V, GND = 0V, V
L
= 6V,
V
IL
= GND, V
IH
= V
DD
, Ta = 10 to +60C)
Item
"H" level output voltage
"M" level output voltage
"L" level output voltage
Input current
"H" level output ON resistance
"M" level output ON resistance
"L" level output ON resistance
Static current consumption
V
H
V
M
V
L
I
I
Ron (H)
Ron (M)
Ron (L)
I
DD
+ I
H
+ I
M
I
H
= 1mA
I
M
= 1mA
I
L
= 1mA
I
H
= 50mA
I
M
= 50mA
I
L
= 50mA
V
H
0.1
V
M
0.1
V
L
18
18
18
10
4
V
H
V
M
V
L
+ 0.1
1.0
30
30
30
100
V
V
V
A
A
Symbol
Conditions
Min.
Typ.
Max.
Unit
Item
Propagation delay time
L
M, M
L
Propagation delay time
M
H, H
M
Rise time L
M
Fall time M
L
Rise time M
H
Fall time H
M
Operating current
consumption
t
PLH
,
t
PHL
t
PLH
,
t
PHL
t
TLH
,
t
THL
t
TLH
,
t
THL
Idyn
(I
DD
+ I
H
+ I
M
+ I
L
)
I
DD
I
H
+ I
M
I
L
Waveform diagram (1),
no load
Waveform diagram (2),
no load
Refer to waveform
diagram (1), output
load circuit diagram
Refer to waveform
diagram (2), output
load circuit diagram
Refer to input pulse
timing diagram, output
load circuit diagram
5.0
100
200
200
200
6.0
0.02
3.8
3.8
200
400
300
300
10.0
0.2
5.0
ns
ns
ns
ns
mA
mA
mA
mA
Symbol
Conditions
Min.
Typ.
Max.
Unit
2. AC Characteristics
5
CXD1268M
Waveform Diagram (1)
Waveform Diagram (2)
tr
tf
90%
50%
10%
t
PLH
t
PHL
t
TLH
t
THL
V
DD
GND
tr = tf = 20ns
V
M
V
L
input
XV1 to XV4
output
V
1 to V
4
90%
50%
10%
tr
tf
t
PLH
t
PHL
10%
90%
V
DD
GND
tr = tf = 20ns
V
H
V
M
input
XSG1, XSG2
output
V
1, V
3
50%
90%
50%
10%
t
TLH
t
THL
V
4
V
3
V
2
V
1
3000pF
3000pF
1600pF
2000pF
2000pF
1600pF
1000pF
1000pF
Output Load Circuit Diagram
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