CXD2301Q

E92Y50B4X-PK

8-bit 30MSPS Video A/D Converter with Built-in Amplifier/Clamp

Description

The CXD2301Q is an 8-bit CMOS A/D converter

for video applications with built-in amplifier/sync-

clamp circuits. A maximum conversion rate of

30MSPS is attained at a low power consumption by

adopting a 2-step parallel system.

Features

· Resolution: 8 bits ±1/2LSB (DL)

· Maximum sampling frequency: 30MSPS

· Low power consumption: 120mW (at 30MSPS

typ.)

(Including reference current)

· Standby function:

0.5mW power consumption in standby

· Amplifier functions: Built-in 3x amplifier (15MHz band),

2-input selector function

provided

· Synchronous clamp function

· Clamp ON/OFF function

· Reference voltage self-bias circuit

· TTL compatible output

· 3V digital interface capability

· Single 5V or dual 4.75/3.3V power supplies

· Low input capacitance: 8pF

· Reference impedance: 330

(typ.)

Applications

Wide range of application fields where high-speed

A/D conversion is required such as in the digital

systems of TVs, VCRs, etc.

Structure

Silicon gate CMOS IC

Absolute Maximum Ratings (Ta = 25°C)

· Supply voltage

· Reference voltage

, V

+0.5 to V

0.5

· Input voltage (analog) V

+0.5 to V

0.5

· Input voltage (digital)

, V

+0.5 to V

0.5

· Output voltage (digital) V

, V

+0.5 to V

0.5

· Storage temperature

Tstg

55 to +150 °C

Recommended Operating Conditions

· Supply voltage

IDV

I 0 to 100

Single power supply

, DV

5.0 ± 0.25

Dual power supply

4.75 ± 0.25

3.3 ± 0.3

· Reference input voltage

0 to

to 2.2

· Analog input

ADIN

More than 1.2Vp-p

· Clock pulse width

PWI

16 (min)

PWO

16 (min)

· Operating ambient temperature

Topr

20 to +75 °C

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

32 pin QFP (Plastic)

For the availability of this product, please contact the sales office.

CXD2301Q

Block Diagram

Lower
data
latch

Upper
data
latch

TEST

(DV

)

SEL

D0(LSB)

D7(MSB)

CLK

REF

CLE CLP CCP

ADV

OPO

IN2

IN1

Clock generator

Upper encoder
(4 bit)

Upper
sampling comparator
(4 bit)

Lower encoder
(4 bit)

Lower
sampling comparator
(4 bit)

Lower encoder
(4 bit)

Lower
sampling comparator
(4 bit)

ADIN

Reference supply

ADV

A/D Converter

Block

CXD2301Q

Pin Description

Reference voltage (bottom)
Connect to AV

for normal use.

When another external voltage is input,
connect an external 0.1µF capacitor and
retain a 1.5V differential compared to the
top reference voltage.

Reference voltage (top)
By setting V

to AV

, outputs

approximately 1.5V.
Connect only a 0.1µF external by-pass
capacitor for normal use.
When another external voltage is input, it
must be 2.2V or lower.

Rref

Pin No.

Symbol

2, 3, 7,

28, 31

SEL

TEST

CLE

CLK

CLP

9 to 16

to D

Equivalent circuit

Description

Analog GND.

Switches the input of the 3x amplifier.
When SEL is at Low level, V

IN1

is selected.

When SEL is at High level, V

IN2

is selected.

Standby function ON/OFF selector.
In standby state when High.

Fix to V

for normal use.

When CLE = Low: Clamp functiion is
enabled.
When CLE = High: Clamp function is
disabled, and only the normal A/D
converter function is enabled.

Clock input

Inputs the clamp pulse to Pin 20 (CLP).
Clamps the High interval signal voltage.

Digital GND.

(MSB) to D

(LSB) output

Outputs Low level in standby.
In operation, the phase of D

to D

output is inverted against the phase of
ADIN.

5V or 3.3V

CXD2301Q

Short Pins 21 and 22, and connect 0.1µF
external capacitor.

200

R11

R12

ADV

Clamp reference voltage input.
Clamps so that the reference voltage
and the clamp interval ADIN input signal
are equal.
The reference voltage is more than 0.5V.

REF

Amplifier input pin.
Biased internally
at 1.9V (when AV

= 5V) or

at 1.8V (when AV

= 4.75V).

When in standby as well.
When SEL is at Low level, V

IN1

selected for input;
When SEL is at High level, V

IN2

selected for input.

25
27

IN1

IN2

5V or 4.75V

Pin No.

Symbol

Equivalent circuit

Description

CXD2301Q

A/D converter block analog input.

ADIN

Amplifier output.
The phase of this output is inverted
against the phase of V

IN1, 2

In standby mode, it becomes
high-impedance output condition.

OPO

Integrates the clamp control voltage.
The relationship between the CCP
voltage variation and the ADIN voltage
is positive phase.

TEST

SEL

L
L

H
H
H

H
H

X
X
X

TEST mode

CCP

· The following table shows the status of the digital output pins when the TEST pin is used with the CE and

SEL pins.

Pin No.

Symbol

Equivalent circuit

Description

CXD2301Q

Digital Output

The following table shows the correlation between the ADIN input voltage and the digital output code.

Take notice that the phase of ADIN input signal voltage is inverted against the phase of the digital output.

ADIN

Input signal voltage

Step

Digital output code

MSB LSB

:
:
:
:

127
128

255

0 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

: Indicates point at which input signal is sampled

Clock 2V

ADIN input

Data output

N+1

N+2

N+3

N+4

N+1

Fig. 1. Timing Chart

CXD2301Q

Electrical Characteristics

(1) When using a single power supply (Fc = 30MSPS, AV

= DV

= +5V, V

= 0V, V

= 1.5V, Ta = 25°C)

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

Supply current

Standby supply current

Max. conversion rate

Min. conversion rate

ADIN input band (at 1dB)

ADIN input capacitance

Reference resistance (V

to V

)

Self bias

Offset voltage

Digital input voltage

Digital input current

Digital output current

Output data delay

Integral nonlinearity error

Differential nonlinearity error

Differential gain error

Differential phase error

Aperture jitter

Sampling delay

Clamp offset voltage

Clamp pulse delay

Amplifier gain

IN1

and V

IN2

bias voltage

IN1

and V

IN2

input resistance

IN1

and V

IN2

input capacitance

STB

Fc max

Fc min

ADIN

REF

taj

tsd

Eoc

tcpd

BI1, 2

I1, 2

Fc = 35MSPS
NTSC ramp wave input

CE = DV

= 0 to 1.5V

= 1kHz ramp

= 0.75V + 0.07Vrms

= AV

= V

= 0V

= V

0.5V

= 0.4V

With TTL 1gate and 10pF load

Fc = 30MSPS
V

= 0 to 1.5V

Fc = 30MSPS
V

= 0 to 1.5V

NTSC 40IRE mod
ramp, Fc = 14.3MSPS

REF

= 0.5V

REF

= 1.5V

DC to 15MHz

When open

230

1.38

+25

3.5

1.1

3.7

8.5

130

330

1.52

+45

2.5

6.5

+0.5

±0.3

0.5

+20

9.5

1.9

200

0.5

440

1.66

+65

0.5

+1.3

±0.5

+40

10.5

µA

MSPS

MHz

µA

LSB

deg

= max.

= min.

ADIN

= DC,

PWS = 3µsec

CXD2301Q

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

Analog supply current

Digital supply current

Standby supply current

Max. conversion rate

Min. conversion rate

ADIN input band (at 1dB)

ADIN input capacitance

Reference resistance (V

to V

)

Self bias

Offset voltage

Digital input voltage

Digital input current

Digital output current

Output data delay

Integral nonlinearity error

Differential nonlinearity error

Differential gain error

Differential phase error

Aperture jitter

Sampling delay

Clamp offset voltage

Clamp pulse delay

3x amplifier gain

IN1

and V

IN2

bias voltage

IN1

and V

IN2

input resistance

IN1

and V

IN2

input capacitance

STB

Fc max

Fc min

ADIN

REF

taj

tsd

Eoc

tcpd

BI1, 2

I1, 2

Fc = 30MSPS
NTSC ramp wave input

CE = DV

= 0 to 1.5V

= 1kHz ramp

= 0.75V + 0.07Vrms

= AV

= DV

= 0V

= V

0.5V

= 0.4V

With TTL 1gate and 10pF load

Fc = 30MSPS
V

= 0 to 1.5V

Fc = 30MSPS
V

= 0 to 1.5V

NTSC 40IRE mod
ramp, Fc = 14.3MSPS

REF

= 0.5V

REF

= 1.5V

DC to 15MHz

When open

230

1.44

+25

2.5

1.1

3.7

8.5

130

330

1.52

+45

2.5

6.5

+0.5

±0.3

0.5

+20

9.5

1.8

200

0.5

440

1.6

+65

0.5

+1.3

±0.5

+40

10.5

µA

MSPS

MHz

µA

LSB

deg

= max.

= min.

= DC,

PWS = 3µsec

(2) When using a dual power supply (Fc = 30MSPS, AV

= 4.75V, DV

= 3.3V, V

= 0V, V

= 1.5V, Ta = 25°C)

CXD2301Q

Application Circuit

(1) When using the internal amplifier

a) Clamp usage example (using self bias)

GND (digital)

GND (analog)

0.01µ

0.1µ

10p

0.1µ

VIDEO IN

REF

20k

+4.75V

0.1µ

CLAMP PULSE IN

CLOCK IN

+3.3V

0.1µ

ACO4

LATCH *

Although the ADC sampling clock latches the clamp pulse, it is not needed for basic clamp

operation. However, depending on the relationship between the sampling frequency and the

clamp pulse frequency, a small beat might be generated as V sag. The latch circuit is valid at

this time.

CXD2301Q

b) Digital clamp usage example (using self bias)

GND (digital)

GND (analog)

0.1µ

VIDEO

IN2

+4.75V

0.1µ

CLOCK IN

+3.3V

0.1µ

ACO4

Subtracter,

Comparator,

etc.

Clamp Level
Setting data

DAC,

PWM,

etc.

High impedance for all
information outside the
clamp interval

0.1µ

VIDEO

IN1

The relationship between the CCP voltage (Pin 32) variation and the ADIN voltage variation is

positive phase.

ADIN/

CCP

= 3.0 (fs = 30MSPS)

CXD2301Q

(2) When not using the internal amplifier

a) Clamp usage example

GND (digital)

GND (analog)

10p

0.1µ

VIDEO IN #

+4.75V (analog)

0.1µ

CLAMP PULSE IN

CLOCK IN

+3.3V (digital)

0.1µ

ACO4

LATCH *

0.01µ

10µ

0.1µ

+4.75V

20k

Although the ADC sampling clock latches the clamp pulse, it is not needed for basic clamp

operation. However, depending on the relationship between the sampling frequency and the

clamp pulse frequency, a small beat might be generated as V sag. The latch circuit is valid at

this time.

# Take care that the phase of ADIN input is inverted against the phase of the digital output,

because the use of the built-in inverting amplifier is standard. (Refer to "Digital Output" on page

6.)

CXD2301Q

b) Digital clamp usage example

Subtracter,

Comparator,

etc.

Clamp Level
Setting data

DAC,

PWM,

etc.

High impedance for all
information outside the
clamp interval

GND (digital)

GND (analog)

10p

0.1µ

VIDEO IN #

+4.75V (analog)

0.01µ

10µ

0.1µ

CLOCK IN

{

3.3V (digital)

0.1µ

ACO4

0.1µ

The relationship between the CCP voltage (Pin 32) variation and the ADIN voltage variation is

positive phase.

ADIN

CCP

= 3.0 (fs = 20MSPS)

c) When not using the clamp

GND (digital)

GND (analog)

10p

VIDEO IN #

+4.75V (analog)

0.1µ

CLOCK IN

+3.3V (digital)

0.1µ

ACO4

0.1µ

+3.3V (digital)

0.1µ

# Take care that the phase of ADIN input is inverted against the phase of the digital output,

because the use of the built-in inverting amplifier is standard. (Refer to "Digital Output" on page

6.)

CXD2301Q

Example of Representative Characteristics

Input frequency of V

IN2

vs.

Crosstalk V

IN2

IN1

=4.75V

=150mVrms

IN1

=GND

Crosstalk [dB]

Input frequency [MHz]

Sampling frequency vs. Current consumption

=NTSC ramp wave

=150mVrms

fsSampling frequency [MHz]

0.1

0.5

Current consumption [mA]

Input frequency vs. Current consumption

=5V,

Input waveform is ramp wave
V

=150mVrms

Current consumption [mA]

Input frequency [MHz]

0.1

0.5

CXD2301Q

ANALOG CIRCUIT

MOUNT PORTION

ANALOG INPUT
INTERFACE

ANALOG CIRCUIT

MOUNT PORTION

V REF

KET

CLOCK
BUFFER

OSC

DIGITAL CIRCUIT MOUNT
PORTION

V IN

V OUT

CLOCK

SEL SYNC

CLE

BLK

Unnecessary at
self bias use

+5V

GND

KET

8bit ADC and DAC Evaluation Board

Evaluation boards are available for the high speed, low power consumption CMOS converters, CXD2301Q

(8-bit 30MHz A/D) and CXD1171M (8-bit 40MHz D/A).

The evaluation board is composed of a main board common to either type, to which is added sub board

D2301Q or sub board D1171M. The junction is made through a socket.

To the main board are mounted an input interface, clock buffer and latch. To each of the sub boards is

mounted CXD2301Q and CXD1171M respectively. Those IC's are mounted according to recommended print

patterns designed to provide maximum performance to the A/D and D/A converters.

Block Diagram

Characteristics

· Resolution

8bit

· Maximum conversion rate

30MHz

· Digital input level

CMOS level

· Supply voltage

±5.0V (Single +5V power supply possible at self bias use)

Supply Voltage

Item

Min.

Typ.

Max.

Unit

+5V
5V

165

Clock Input

CMOS compatible

Pulse width

CW1

16ns (min)

CW0

16ns (min)

CXD2301Q

Analog Output (CXD1171M)

(RL > 10k

)

Item

Min.

Typ.

Max.

Unit

Analog output

1.8

2.0

2.1

Item

Symbol

Min.

Typ.

Unit

Clock High time

Clock Low time

Clock Delay

Data delay AD

Data delay (latch)

Settling time

Hold time

Data delay DA

PW1

PW0

Tdc

PD (AD)

PD (DA)

Max.

Output Format (CXD2301Q)

The table shows the output format of AD Converter

Analog input

voltage

Step

Digital output code

MSB LSB

:
:
:
:

127
128

255

0 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

Timing Chart

(DA)

PD(AD)

Tdc

PW1

PW0

Analog input

External clock

AD clock

AD output

Latch output
DA input

DA clock

DA output

CXD2301Q

CMOS ADC/DAC Peripheral Circuit Board

(Main Board)

20k

(
16R

)

200

)

R5 510

R6 510

R4 510

C3 0.

20k

R3 75

10µ

R2 75

470µ

R1 100k

I
D

O IN

47µ

EAR

01µ

SEL

SYN

RNA

EXT

/
I
N

R9 75

20k

47µ

NC I

75µ

)

GND

+5V

SYN

SEL

74S04

74HC0

(INV

ER)

74S

174

(
L

CH)

74S

174

(
L

CH)

CXD2301Q

CMOS ADC/DAC Peripheral Circuit Board (Sub Board)

0.1µ

CLK

CLP

VIN

1µ

1000p

0.1µ

0.01µ

CXD2301Q

CLE

REF

CXD1171M

BLK

CLK

REF

CXD2301Q

List of Parts

resitance

transistor

100k

2SC2785

510

IC1

74S174

R = 200

IC2

74S174

18R

3.3k

IC3

74S04

R10

oscillator

VR1

OSC

VR2

VR3

20k

others

VR4

20k

connector

BNC071

VR5

20k

AT1D2M3

capacitance

470µF/6.3V (chemical)

10µF/16V (chemical)

0.01µF

0.1µF

C10

0.1µF

C11

47µF/10V (chemical)

C12

47µF/10V (chemical)

C13

47µF/10V (chemical)

C14

0.1µF

Adjustment

1. Vref adjustment (VR1, VR2)

Adjustment of A/D converter reference voltage. V

is adjusted through VR1 and V

through VR2. When

self bias is used, there is no need for adjustment. Reference voltage is set through self bias at delivery.

2. Setting of clamp reference voltage (VR3)

Clamp reference voltage is set.

3. DAC output full scale adjustment (VR4)

Full scale voltage of D/A converter output is adjusted at the PCB shipment, the full scale voltage is adjusted

to approx. 2V.

4. Sync (clamp) pulse interface (VR5)

This adjustment enables interface with the signal generator and others at the PCB shipment, adjustment is

performed to obtain a threshold of approx. 2.5V to an H sync of 0 to 5V.

CXD2301Q

5. OE, SEL, Sync, BLK, CLE, Sync INT

The following pins are set on the main board: Sync, CLE, Sync INT (CXD2301Q) and BLK (CXD1171M),

OE, SEL (not used). For the pins function, refer to the specifications. The difference between Sync pin and

Sync INT pin is that you input a pulse above 3.5Vp-p to Sync INT pin. The pulse threshold is set through

VR5. For input through Sync pin, pulse is input at TTL or CMOS level. In this case cut off the junction line

between Sync pin and Sync INT pin.

At the PCB shipment the main board pins are set as follows.

· OE ........ Low

· SEL ...... Low

· Sync ..... Line junction with Sync INT pin

· CLE ...... Low (Clamp function ON)

· BLK ...... Low (Blanking OFF)

6. Clamp pulse input method

The clamp pulse is directly input to CXD2301Q as show in Application Circuit examples (1) and (2). Use the

direct input that is set at the PCB shipment.

Points on the PCB Pattern Layout

1. Set the layout not to have Digital current flow into Analog GND (Part 1). (For 1, see P.17 Component side

diagram.)

2. At CXD2301Q sub board, C

and C

capacitors serve the important role of bringing out CXD2301Q's full

performance.

These are over 0.1µF (ceramic) capacitors with good high frequency characteristics. Layout as close to the

IC as possible.

3. Analog GND (AV

) and Digital GND (DV

) are on a common voltage and power source. Keeping ADC's

(Part 2) as close as possible to the voltage supply source will provide better results. That is, a layout

where ADC is close to the voltage supply source, is recommended. (For 2, see P.17 Component side

diagram.)

4. ADC samples analog signals at the clock falling edge point. Accordingly clocks supplied to ADC should not

have any jitter.

5. The PCB layout shows ADC and DAC's Analog GND independently from the voltage supply source. The

layout aims at providing an independent evaluation of ADC and DAC, as much as possible. On the actual

board, common use will not cause any problems.

CXD2301Q

Notes on Operation

1. Reference voltage

By shorting V

and V

RTS

, V

and V

RBS

, CXD2301 has the self bias function that generates V

= about

2.6V and V

= about 0.5V. On the PCB, either self bias or the external reference voltage can be selected

depending on the junction method of the jumper line. At shipment from the factory, reference voltage is

provided in self bias. Also, to provide external reference voltage, adjust the dynamic range (V

) to

above 1.8Vp-p.

2. Clock input

There are 2 modes for the PCB clock input.

1) Provided from the external signal generator (External clock)

2) Using the crystal oscillator (built-in clock driver). (Internal clock)

The 2 modes are selected using the switch on the PCB.

3. The 2 Latch IC's (74S174) are not absolutely necessary for the evaluation of ADC and DAC. That is,

operation will still be normal if ADC output data is directly input to DAC input. However, as ADC output data

is hardly ever D/A converted without executing Digital signal processing, it was mounted to indicate an

example layout of Digital signal processing IC. When the ADC output data is used, use the output of the

latch IC.

4. When clamp is not used

Turning CLE to H will set OFF the clamp function. In this case, the DC element is cut off by means of C

the main board and DC voltage on the ADC side of C

turns to about (V

+ V

). To transfer DC elements

of input signals, short C

. At that time, it is necessary to bias input signals, but keeping R

open, Q

can

also be used as buffer. Use the open space for the bias circuit.

5. Clamp pulse latch

On the evaluation board, the clamp pulse is latched with ADC sampling CLK and then input to the CLP pin.

This is to minimize Vsag due the synchronizing of noise and clamp pulse beat elements with GND sampling

clock around ADC. If there are no problems with Vsag, latch is not necessary.

6. Peripheral through hole

There is a group of through holes on the Analog input, output and Logic. These are to be used when

mounting additional circuits to the PCB. Use when necessary.

The connector hole on DAC part is used to mount the test chassis and the mount jack.

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