Description

The CXD2302Q is an 8-bit CMOS A/D converter

for video with synchronizing clamp function. The

adoption of 2 step-parallel method achieves low

power consumption and a maximum conversion rate

of 50MSPS.

Features

· Resolution: 8 bit ± 1/2LSB (DL)

· Maximum sampling frequency: 50MSPS

· Low power consumption: 125mW (at 50MSPS typ.)

(reference current excluded)

· Synchronizing clamp function

· Clamp ON/OFF function

· Reference voltage self-bias circuit

· Input CMOS/TTL compatible

· 3-state TTL compatible output

· Single 5V power supply or dual 5V/3.3V power supply

· Low input capacitance: 15pF

· Reference impedance: 370

(typ.)

Applications

Wide range of applications that require high-speed

A/D conversion such as TV and VCR.

Structure

Silicon gate CMOS IC

Absolute Maximum Ratings (Ta = 25°C)

· Supply voltage

· Reference voltage V

+ 0.5 to Vss 0.5V

· Input voltage

+ 0.5 to Vss 0.5V

(Analog)

· Input voltage

+ 0.5 to Vss 0.5V

(Digital)

· Output voltage

+ 0.5 to Vss 0.5V

(Digital)

· Storage temperature

Tstg

55 to +150

°C

Recommended Operating Conditions

· Supply voltage

, AVss 4.75 to 5.25

, DVss

3.0 to 5.5

| DVss AVss | 0 to 100

· Reference input voltage

0 and above

2.7 and below

· Analog input

1.7Vp-p above

· Clock pulse width

PW1

, T

PW0

9ns (min) to 1.1µs (max)

· Operating ambient temperature

Topr

40 to +85

°C

CXD2302Q

E94102E78-PS

8-bit 50MSPS Video A/D Converter with Clamp Function

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

32 pin QFP (Plastic)

CXD2302Q

Block Diagram

Lower

sampling comparator

(4 BIT)

Lower

sampling comparator

(4 BIT)

Upper

sampling comparator

(4 BIT)

Lower encoder

(4 BIT)

Lower encoder

(4 BIT)

Upper encoder

(4 BIT)

Lower

data

latch

Upper

data

latch

Clock generator

Reference supply

VRBS

VRB

AVss

VRT

VRTS

DVss

(LSB)

(MSB)

TEST (OPEN)

DVss

CLE

CCP

REF

CLP

D-FF

TEST (OPEN)

CLK

CXD2302Q

Pin Description

Pin No.

Symbol

Equivalent circuit

Description

1 to 8

13, 14, 32

to D

TEST

CLP

CLE

CLK

(LSB) to D

(MSB) output

Leave open for normal use.

Digital power supply +5V or +3.3V

Leave open for normal use.
Pull-up resistor is built in.

Input the clamp pulse.
Clamps the signal voltage during
Low interval. Pull-up resistor is
built in.

The clamp function is enabled
when CLE = Low.
The clamp function is set to off
and the converter functions as a
normal A/D converter when
CLE = High.
Pull-up resistor is built in.

Clock input.
Set to Low level when no clock is
input.

16, 19, 20 AV

Analog power supply +5V

CXD2302Q

VRTS

Generates approximately +2.5V
when shorted with AV

VRT

VRB

Reference voltage (top)

Reference voltage (bottom)

Rref

Analog input

VREF

Clamp reference voltage input.
Clamps so that the reference
voltage and the input signal during
clamp interval are equal.

CCP

Integrates the clamp control
voltage.
The relationship between the
changes in CCP voltage and in V

voltage is positive phase.

Data is output when OE = Low.
Pins D

to D

are at high

impedance when OE = High.
Pull-down resistor is built in.

VRBS

Generates approximately +0.6V
when shorted with AV

22, 23

Analog ground

28, 31

Digital ground

Pin No.

Symbol

Equivalent circuit

Description

CXD2302Q

PW1

PW0

N + 1

N + 2

N + 3

N + 4

N + 1

N 1

N 2

N 3

O: Analog signal sampling point

Clock 1.3V

Analog input

Data output

1.3V

0.7DV

0.3DV

Clock

Data output

90%

10%

4ns

Timing Chart

-2.

tr = 4.5ns

tf = 4.5ns

90%

10%

1.3V

10%

90%

1.3V

(

)

(

)

Output 2

Output 1

OE input

Timing Chart

-1.

Timing Chart

-3.

Digital output

The following table shows the relationship between analog input voltage and digital output code.

Input signal

voltage

Step

Digital output code

MSB LSB

:
:
:
:

127
128

255

1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

Timing Chart

CXD2302Q

Electrical Characteristics

Analog characteristics

(Fc = 50MHz, AV

= 5V, DV

= 3 to 5.5V, V

= 0.5V, V

= 2.5V, Ta = 25°C)

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

Max. conversion rate

Min. conversion rate

Analog input band width

Differential non-linearity error

Integral non-linearity error

Offset voltage

Differential gain error

Differential phase error

Sampling delay

Clamp offset voltage

SNR

FIN = 100kHz

FIN = 500kHz

FIN = 1MHz

FIN = 3MHz

FIN = 10MHz

FIN = 25MHz

FIN = 100kHz

FIN = 500kHz

FIN = 1MHz

FIN = 3MHz

FIN = 10MHz

FIN = 25MHz

FSDR

= DC

= 10µF

pcw = 2.75µs

Fc = 14.3MHz
Fclp = 15.75kHz

REF

= 0.5V

REF

= 2.5V

Signal-to-noise ratio

Spurious free dynamic
range

Fc max.

Fc min.

100

±0.3

+0.7

1.5

0.5

±0.5

±1.5

MSPS

MHz

LSB

deg

1dB

3dB

End point

Potential difference to VRT

Potential difference to VRB

NTSC 40 IRE mod ramp
Fc =14.3MSPS

= 4.75 to 5.25V

Ta = 40 to +85°C,
V

= 0.5 to 2.5V

= 1kHz triangular wave

Envelope
R

= 33

The offset voltage EOB is a potential difference between VRB and a point of position where the voltage

drops equivalent to 1/2 LSB of the voltage when the output data changes from "00000000" to "00000001".

EOT is a potential difference between VRT and a potential of point where the voltage rises equivalent to

1/2LSB of the voltage when the output data changes from "11111111" to "11111110".

Clamp offset voltage varies individually. When using with R, G, B 3 channels, color sliding may be

generated.

CXD2302Q

DC characteristics

(Fc = 50MHz, AV

= 5V, DV

= 5V or 3.3V, V

= 0.5V, V

= 2.5V, Ta = 25°C)

Supply

Analog

current

Digital

Reference current

Reference resistance
(V

)

Self-bias voltage

Analog input resistance

Input capacitance

Output capacitance

Digital input voltage

Digital input current

Digital output current

+ I

REF

AI1

AI2

DIN

OZH

OZL

4.1

260

0.52

1.80

2.2

240

2.4

1.2

µA

240

µA

0.8

5.4

370

0.56

1.92

7.7

480

0.60

2.04

NTSC ramp
wave input
CLE = 0V

= 5V

= 3.3V

Shorts V

RTS

and AV

Shorts V

RBS

and AV

VIN

Fc = 50MHz

Fc = 35MHz

Fc = 20MHz

VIN, VIN = 1.5V + 0.07Vrms

VRTS, VRT, VRB, VRBS, VREF

TEST, CLK, CLP, CLE, OE

CCP

D0 to D7, TEST

= 4.75 to 5.25V

= 3 to 5.5V

Ta = 40 to +85°C

= 0V to AV

Ta = 40 to +85°C

OE = 0V
DV

= 5V

Ta = 40 to +85°C

OE = 3V
DV

= 3 to 5.5V

Ta = 40 to +85°C

CLK

TEST,
CLP, CLE

= DV

0.8V

= 0.4V

= DV

0.8V

= 0.4V

= DV

= 0V

Note) The voltage of up to (AV

+ 0.5V) can be input when DV

= 3.3V. But the output pin voltage is less

than the DV

voltage. When the digital output is in the high impedance mode, the IC may be damaged

by applying the voltage which is more than the (DV

+ 0.5V) voltage to the digital output.

OE = 0V
DV

= 3.3V

Ta = 40 to +85°C

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

CXD2302Q

Timing

(Fc = 50MHz, AV

= 5V, DV

= 5V or 3.3V, V

= 0.5V, V

= 2.5V, Ta = 25°C)

Output data delay

Tri-state
output enable time

Tri-state
output disable time

Clamp pulse width

CPW

9.5

8.5

11.8

7.6

4.5

6.0

7.0

5.0

5.5

2.75

µs

= 15pF

OE = 0V

= 1k

= 15pF

OE = 3V

= 1k

= 15pF

OE = 0V

Fc = 14.3MHz, C

= 10µF

for NTSC wave

= 5V

= 3.3V

= 5V

= 3.3V

= 5V

= 3.3V

5.5

4.3

2.5

3.0

3.5

2.5

1.75

12.0

16.3

8.0

9.0

7.5

8.0

3.75

The clamp pulse width is for NTSC as an example. Adjust the rate to the clamp pulse cycle (1/15.75kHz for

NTSC) for other processing systems to equal the values for NTSC.

Electrical Characteristics Measurement Circuit

Output data delay measurement circuit

Tri-state output measurement circuit

Measurement
point

To output pin

Measurement point

Note) C

includes capacitance of probes.

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

CXD2302Q

Integral non-linearity error

Differential non-linearity error

}

test circuit

Offset voltage

Analog input resistance test circuit

A < B A > B

COMPARATOR

A1
A0

B1
B0

DUT

CXD2302Q

BUFFER

S1: ON

A < B

S2: ON

B > A

CONTROLLER

DVM

000 · · · 00

111 · · · 10

CLK (50MHz)

"0"

"1"

Differential gain error

Differential phase error

}

test circuit

AMP

CXD

2302Q

TTL

ECL

10bit

D/A

5.2V

620

NTSC

SIGNAL

SOURCE

VECTOR

SCOPE

D.G
D.P.

5.2V

620

TTL

ECL

CX20202A-1

S.G.

(CW)

40 IRE
MODULATION

BURST

SYNC

2.5V

0.5V

100

IAE

CLK

Digital output current test circuit

CLK

GND

2.5V

0.5V

CLK

GND

2.5V

0.5V

+5V

CLK

0.5V

2.5V

GND

CXD2302Q

Timing Chart

S (1)

C (1)

S (2)

C (2)

S (3)

C (3)

S (4)

C (4)

MD (0)

MD (1)

MD (2)

MD (3)

RV (0)

RV (1)

RV (2)

RV (3)

(1)

(2)

(3)

(4)

S (1)

C (1)

S (3)

C (3)

H (3)

H (1)

LD (1)

C (0)

S (2)

C (2)

S (4)

H (0)

H (2)

H (4)

LD (2)

LD (0)

LD (2)

Out (2)

Out (1)

Out (0)

Out (1)

Vi (1)

Vi (2)

Vi (3)

Vi (4)

External clock

Upper comparators block

Analog input

Upper data

Lower reference voltage

Lower comparators A block

Lower data A

Lower comparators B block

Lower data B

Digital output

Operation (See Block Diagram and Timing Chart

)

1. The CXD2302Q is a 2-step parallel system A/D converter featuring a 4-bit upper comparator block and 2

lower comparator blocks of 4-bit each. The reference voltage that is equal to the voltage between V

/16 is constantly applied to the upper 4-bit comparator block. Voltage that corresponded to the upper

data is fed through the reference supply to the lower 4-bit comparator block. VRTS and VRBS pins serve

for the self generation of V

(Reference voltage top) and V

(Reference voltage bottom), and they are

also used as the sence pins as shown in the Application Circuit examples

-4 and

-5.

CXD2302Q

2. This IC uses an offset cancel type comparator which operates synchronously with an external clock. It

features the following operating modes which are respectively indicated on the timing chart

with S, H, C

symbols. That is input sampling (auto zero) mode, input hold mode and comparison mode.

3. The operation of respective parts is as indicated in the Timing Chart

. For instance input voltage Vi (1) is

sampled with the falling edge of the external clock (1) by means of the upper comparator block and the

lower comparator A block.

The upper comparator block finalizes comparison data MD (1) with the rising edge of the external clock (2).

Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to

the upper results. The lower comparator A block finalizes comparison data LD (1) with the rising edge of

the external clock (3). MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the

external clock (4). Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital

data output.

Operation Notes

1. V

, V

To reduce noise effects, separate the analog and digital systems close to the device. For both the digital

and analog V

pins, use a ceramic capacitor of about 0.1µF set as close as possible to the pin to bypass

to the respective GND's.

2. Analog input

Compared with the flash type A/D converter, the input capacitance of the analog input is rather small.

However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability.

When driving with an amplifier of low output impedance, parasitic oscillation may occur. That may be

prevented by insetting a resistance of about 33

in series between the amplifier output and A/D input.

When the V

signal of pin No. 21 is monitored, the kickback noise of clock is. However, this has no effect

on the characteristics of A/D conversion.

3. Clock input

The clock line wiring should be as short as possible also, to avoid any interference with other signals,

separate it from other circuits.

4. Reference input

Voltage V

to V

is compatible with the dynamic range of the analog input. Bypassing V

and V

pins

to GND, by means of a capacitor about 0.1µF, stable characteristics are obtained. By shorting V

and

RTS

, V

and V

RBS

respectively, the self-bias function that generates V

=about 2.5V and V

=about

0.6V, is activated.

5. Timing

Analog input is sampled with the falling edge of CLK and output as digital data synchronized with a delay

of 2.5 clocks and with the following rising edge. The delay from the clock rising edge to the data output is

about 9ns (DV

= 5V).

6. OE pin

Pins 1 to 8 (D

to D

) are in the output mode by leaving OE open or connecting it to DV

, and they are in

the high impedance mode by connecting it to DV

CXD2302Q

10p

+5V (Digital)

0.1µ

0.01µ

GND (Digital)

GND (Analog)

+5V (Analog)

0.01µ

CLOCK IN

CLAMP PULSE IN

VIDEO IN

10µ 33

0.1µ

REF

20K

0.01µ

OPEN

ACO4

10p

+5V (Digital)

0.1µ

GND (Digital)

GND (Analog)

+5V (Analog)

0.01µ

CLOCK IN

VIDEO IN

10µ

0.1µ

0.01µ

OPEN

ACO4

Subtracter

Comparator

etc.

Clamp level
setting data

DAC

PWM

etc.

Information other than

that for clamp interval
is at high impedance.

The relationship between the changes

in CCP voltage (Pin 27) and in V

voltage is positive phase.

Vin/

Vccp = 3.0 (fs = 20MSPS)

-2. Digital clamp (self-bias used)

Application Circuit

Single +5V Power Supply

-1. When clamp is used (self-bias used)

CXD2302Q

10p

GND (Analog)

+5V (Digital)

0.1µ

GND (Digital)

+5V (Analog)

0.01µ

CLOCK IN

VIDEO IN

0.1µ

0.01µ

OPEN

ACO4

-3. When clamp is not used (self-bias used)

+5V (Analog)

GND (Analog)

10p

+5V (Digital)

0.1µ

0.01µ

GND (Digital)

+5V (Analog)

0.01µ

CLOCK IN

CLAMP PULSE IN

VIDEO IN

10µ 33

0.1µ

REF

20K

0.01µ

OPEN

ACO4

VRB

VRT

-4. When clamp is used (self-bias not used)

CXD2302Q

. Dual +5V/+3.3V Power Supply

-1. When clamp is used (self-bias used)

GND (Analog)

10p

+3.3V (Digital)

0.1µ

0.01µ

GND (Digital)

+5V (Analog)

0.01µ

CLOCK IN

CLAMP PULSE IN

VIDEO IN

10µ

0.1µ

REF

20K

0.01µ

OPEN

ACO4

+5V (Analog)

GND (Analog)

10p

+5V (Digital)

0.1µ

GND (Digital)

0.01µ

CLOCK IN

VIDEO IN

0.1µ

0.01µ

OPEN

ACO4

VRB

VRT

-5. When clamp is not used (self-bias not used)

CXD2302Q

Example of Representative Characteristics

Ambient temperature vs. Supply current

Ambient temperature [°C]

Supply current [mA]

Fc = 50MHz
NTSC ramp wave input
AV

= DV

= 5V

Supply voltage vs. Supply current

Supply voltage [V]

4.75

5.25

Supply current [mA]

Fc = 50MHz
NTSC ramp wave input
AV

= DV

Ta = 25°C

Sampling frequency vs. Supply current

Sampling frequency [MSPS]

Supply current [mA]

NTSC ramp wave input
AV

= DV

= 5V

Ta = 25°C

Ambient temperature vs. Maximum operating frequency

Ambient temperature [°C]

Maximum operating rate [MSPS]

Fc = 50MHz
fin = 1kHz, triangular wave input
AV

= DV

= 5V

Ambient temperature vs. Sampling delay

Ambient temperature [°C]

Sampling delay [ns]

Fc = 50MHz
AV

= DV

= 5V

Input frequency vs. Supply current

Input frequency [MHz]

0.01

Supply current [mA]

Fc = 50MHz

Sine wave 1.9Vp-p

= DV

= 5V

Ta = 25°C

0.1

Supply voltage vs. Maximum operating frequency

Supply voltage [V]

4.75

5.25

Maximum operating rate [MSPS]

Fc = 50MHz
NTSC ramp wave input
AV

= DV

Analog input band

Analog input frequency [MHz]

0.1

100

Output level [dB]

Fc = 50MHz
Sine wave 1Vp-p input
AV

= DV

= 5V

Ta = 25°C

CXD2302Q

Analog input frequency vs. SNR, effective bit

Analog input frequency [MHz]

0.01

0.1

SNR [dB]

Fc = 50MHz
AV

= DV

= 5V

= 2Vp-p

Ta = 25°C

Effective bit [bit]

Ambient temperature vs. Output data delay

Ambient temperature [°C]

Output data delay [ns]

Fc = 10MHz
AV

= DV

= 5V

= 15pF

Load capacitance vs. Output data delay

Load capacitance [pF]

Output data delay [ns]

Fc = 10MHz
AV

= DV

= 5V

Ta = 25°C

supply voltage vs. Output data delay

supply voltage [V]

4.5

5.5

Output data delay [ns]

Fc = 10MHz
AV

= 5V

= 15pF

Ta = 25°C

3.5

Load capacitance vs. Output data delay

Load capacitance [pF]

Output data delay [ns]

Fc = 10MHz
AV

= 5V

= 3.3V

Ta = 25°C

Ambient temperature vs. Output data delay

Ambient temperature [°C]

Output data delay [ns]

Fc = 10MHz
AV

= 5V

= 3.3V

= 15pF

Analog input frequency vs. FSDR

Analog input frequency [MHz]

0.01

FSDR [dB]

Fc = 50MHz
AV

= DV

= 5V

= 2Vp-p

Ta = 25°C

0.1

0.5

1.5

2.5

Analog input voltage vs. Input current

Analog input voltage V

[V]

Analog input current I

[µ

Fc = 50MHz
AV

= DV

= 5V

= 2.5V

= 0.5V

Ta = 25°C

CXD2302Q

8-bit 50MSPS ADC and DAC Evaluation Board

Evaluation boards are available for the high speed, low power consumption CMOS converters CXD2302Q

(8-bit 50MHz A/D) and CXD1171M (8-bit 40MHz D/A).

The evaluation boards are composed of a main board, CXD2302Q sub board and CXD1171M sub board. The

each board is connected with sockets.

An input interface, clock buffer and latches are mounted on the main board. The CXD2302Q and CXD1171M

are mounted on each of the sub boards. Those ICs are mounted according to recommended print patterns

designed to provide maximum performance to the A/D and D/A converters.

Block Diagram

ANALOG CIRCUIT
MOUNT PORTION

ANALOG INPUT

INTERFACE

ANALOG CIRCUIT
MOUNT PORTION

V REF

ADC

SOCKET

DAC

SOCKET

CLOCK

BUFFER

DATA LATCH

OSC

DIGITAL

CIRCUIT MOUNT

PORTION

+5V

GND

CLOCK OE

SEL SYNC CLE

BLK

V OUT

V IN

Unnecessary
at self bias use

Characteristics

· Resolution

8bit

· Maximum conversion rate

50MHz

· Digital input level

CMOS level

· Supply voltage

±5.0V (Single +5V power supply possible at self bias use)

Supply voltage

Item

+5V
5V

185

Min.

Typ.

Max.

Unit

Clock input

CMOS compatible

Pulse width

CW1

10ns (min)

CW0

10ns (min)

CXD2302Q

Analog Output (CXD1171M)

> 10k

)

Item

Analog output

1.8

2.0

2.1

Min.

Typ.

Max.

Unit

Output Format (CXD2302Q)

The table shows the output format of AD Converter.

Analog input

voltage

:
:
:
:

127
128

255

Step

Digital output code

MSB

LSB

Analog input

External clock

AD clock

AD output

Latch output
DA input

DA clock

DA output

PD (DA)

Tdc

Tpw

PD (AD)

Timing Chart

Item

Clock High time

Clock Low time

Clock Delay

Data delay AD

Data delay (latch)

Settling time

Hold time

Data delay DA

PW1

PW0

Tdc

PD (AD)

PD (DA)

Symbol

Min.

Typ.

Max.

Unit

CXD2302Q

IREF

VREF

CLK

BLK

CLK

CLP

REF

CLE

R8 3.3k

(16R)

R7 200

(R)

V out

VR4

20k

OUTPUT

GAIN

ADJUST

510

VR2

VRT

ADJUST

VR1

510

VRB

ADJUST

SW1

SW2

0.01

SW3

VR3

20k

10µ

470µ

100k

VIDEO INPUT

CLAMP

VOLTAGE

ADJUST

47µ

+5V

GND

74S174

(LATCH)

0.01µ

CLK

CLEAR

74S174

(LATCH)

74S04

74HC04

(INV BUFFER)

0.1

OSC SWITCH

EXT/INT

BLK

SYNC

SEL

CLE

R10

47µ

0.01µ

EXTERNAL CLOCK

INPUT

SYNC INT

= 75

)

0.01

OSC out

VR5

20k

CMOS ADC/DAC Peripheral Circuit Board

(Main Board)

CXD2302Q

CMOS ADC/DAC Peripheral Circuit Board (Sub Board)

CLP

REF

CLE

CXD2302Q

CLK

0.1µ

C2 0.1µ

C1 0.01µ

REF

CXD1171M

CLK

BLK

CXD2302Q

List of Parts

resistance

100K

510

R = 200

18R

3.3K

R10

VR1

VR2

VR3

20K

VR4

20K

VR5

20K

capacitance

470µF/6.3V (chemical)

10µF/16V (chemical)

0.01µF

0.1µF

C10

0.1µF

C11

47µF/10V (chemical)

C12

47µF/10V (chemical)

C13

47µF/10V (chemical)

C14

0.1µF

transistor

2SC2785

IC1

74S174

IC2

74S174

IC3

74S04

oscillator

OSC

others

connector

BNC071

AT1D2M3

Adjustment

1. Vref adjustment (VR1, VR2)

Adjustment of A/D converter reference voltage. VRB is adjusted through VR1 and VRT through VR2.

When self bias is used, there is no need for adjustment. Reference voltage is set through self bias delivery.

2. Setting of clamp reference voltage (VR3)

Clamp reference voltage is set.

3. DAC output full scale adjustment (VR4)

Full scale voltage of D/A converter output is adjusted at the PCB shipment, the full scale voltage is

adjusted to approx. 2V.

4. Sync (clamp) pulse interface (VR5)

This adjustment enables interface with the signal generator and others at the PCB shipment, adjustment is

performed to obtain a threshold of approx. 2.5V to an H sync of 0 to 5V.

CXD2302Q

5. OE, SEL, Sync, BLK, CLE, Sync INT

The following pins are set on the main board: OE, Sync, CLE, Sync INT (CXD2302Q), BLK (CXD1171M)

and SEL (not used). For the pins function, refer to the Pin Description. The difference between Sync pin

and Sync INT pin is that a pulse above 3.5Vp-p should be input to Sync INT pin. The pulse threshold is set

through VR5. For input through Sync pin, pulse is input at TTL or CMOS level. In this case cut off the

junction line between Sync and Sync INT pin.

At the PCB shipment the main board pins are set as follows.

· OE

: Low (A/D output ON)

· SEL : Low

· Sync : Line junction Sync INT pin

· CLE : Low (Clamp function ON)

· BLK : Low (Blanking OFF)

6. Clamp pulse input method

Directly input the clamp pulse as shown in Application Circuit example

-1. As SW1 is set to direct input at

the PCB shipment, use it in this position.

Points on the PCB Pattern Layout

1. Set the layout not to have Digital current flow into Analog GND (For 1, see p.24 "Component side

diagram".).

2. The C

and C

capacitors for the CXD2302Q sub board serve the important role of bringing out ICs full

performance.

Connect over 0.1µF (ceramic) capacitors with good high frequency characteristics as close to the IC as

possible.

3. Analog GND (AV

) and Digital GND (DV

) are on a common voltage supply source. Keeping ADC's

(For 2, see p.24 "Component side diagram".) as close to the voltage supply source as possible will

provide better characteristics. That is, a layout where ADC is close to the voltage supply source, is

recommended.

4. ADC samples analog signals at the clock falling edge. Accordingly it is important that clocks supplied to

ADC do not have any jitter.

5. The PCB layout shows ADC and DAC's Analog GND independently from the voltage supply source. The

layout aims at providing an independent evaluation of ADC and DAC, as much as possible. On the actual

board, common use will not cause any problems.

CXD2302Q

Notes on Operation

1. Reference voltage

Shorting AV

and V

RTS

, AV

and V

RBS

will activate the self-bias function that generates V

= about 2.6V

and V

=about 0.5V. On the PCB, either self bias or the external reference voltage can be selected

depending on the junction method of the jumper line. At shipment from the factory, reference voltage is

provided in self bias. Also, to provide external reference voltage, adjust the dynamic range (V

) to

above 1.8Vp-p.

2. Clock input

There are 2 modes for the PCB clock input

1) Provided from the external signal generator. (External clock)

2) Using the crystal oscillator (built-in clock driver). (Internal clock)

The 2 modes are selected using the switch on the PCB.

3. The 2 Latch ICs (74S174) are not absolutely necessary for the evaluation of ADC and DAC. That is,

operation will still be normal if ADC output data is directly input to DAC input. However, as ADC output

data is hardly ever D/A converted without executing Digital signal processing, it was mounted to indicate

an example layout of Digital signal processing IC. Use the Latch IC output when the ADC output data is

used.

4. When clamp is not used

Turning CLE to H will set OFF the clamp function. In this case, the DC element is cut off by means of C

the main board and DC voltage on the ADC side of C

turns to about (V

)/2. To transfer DC elements

of input signals, short C

. At that time, it is necessary to bias input signals, but keeping R

open, Q

can

also be used as buffer. Use the open space for the bias circuit.

5. Clamp pulse latch

On the evaluation board, the clamp pulse is latched with ADC sampling CLK and then input to CLP pin.

However, the latch is incorporated in CLP pin of the CXD2302Q, so that the external latch is not required.

6. Peripheral through hole

There is a group of through holes on the Analog input, output and Logic. There are to be used when

mounting additional circuits to the PCB. Use when necessary.

The connector hole on DAC part is used to mount the test chassis mount jack.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXD2302Q

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXD2302Q