--1--

E91Y46F64-TE

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Description

The CXD2500BQ is a digital signal processing LSI

designed for use in compact disc players. It has the

following functions:

· Wide-frame jitter margin (±28 frames) realized by a

built-in 32K RAM.

· Bit clock generated by digital PLL for strobing EFM

signals. Capture range of ±150 kHz and over.

· EFM data demodulation

· Enhanced protection of EFM Frame Sync signals

· Powerful error correction based on Refined Super

Strategy

Error correction

C1: Double correction

C2: Quadruple correction

· Double-speed playback and vari-pitch playback

· Reduced noise generation at track jump

· Auto zero-cross muting

· Subcode demodulation and subcode Q data error

detection

· Digital spindle servo system (incorporating an

oversampling filter)

· 16-bit traverse counter

· Built-in asymmetry correction circuit

· CPU interface using a serial bus

· Servo auto sequencer

· Output for digital audio interface

· Built-in digital level meter and peak meter

· Bilingual

Features

· All digital signals for regeneration are processed

using one chip.

· The built-in RAM enables high-integration

mounting.

Structure

Silicon-gate CMOS IC

CD Digital Signal Processor

80 pin QFP (Plastic)

CXD2500BQ

--2--

CXD2500BQ

Absolute Maximum Ratings (Ta=25 °C)

· Supply voltage

0.3 to +7.0

· Input voltage

0.3 to +7.0

· Output voltage

0.3 to +7.0

· Operating temperature

Topr

20 to +75

°C

· Storage temperature

Tstg

40 to +125

°C

· Supply voltage differences

0.3 to +0.3

Recommended Operating Conditions

· Supply voltage

4.75

to 5.25

(5.0 V typ.)

· Operating temperature

Topr

20 to +75

°C

· Input voltage

0.3 to + V

+ 0.3

value of 4.75 V (min.) is for the double-speed playback mode at vari-pitch control reset. For the low

power consumption special playback mode, V

value is 3.6 V (min.).

In the normal-speed playback

mode V

value is 4.5 V (min.)

Low power consumption, special playback mode

Set the internal operation of LSI at the double-speed mode, and half the crystal oscillation frequency. This

will result in the normal-speed playback mode.

value of 5.25 V (max.) is for the double-speed playback mode at vari-pitch control reset. For normal-

speed playback and the low power consumption special playback mode, the V

value is 5.5 V (max.).

I/O Capacity

· Input pins

12 pF max.

· Output pins

CO 12 pF max. at high impedance

Note: Test Conditions

=0 V

=1 MHz

--3--

CXD2500BQ

C4M

C16M

PDO

VCO1

VCO0

PCO

FIL1

FIL0

CLTV

ASY1

ASY0

ASYE

WFCK

SCOR

EXCK

SBSO

EMPH

SQCK

SQSO

MON

FSW

MDP

MDS

TEST

FSTT

XTAI

XTAO

XTSL

VCKI

VPCO

Timing

Generator

Subcode

P-W

Processor

Subcode

Processor

Noise

shaper

CLV

processor

Timing

Generator 2

Peak detector

Digital out

D/A

data processor

Address

generator

Clock

generator

Digital PLL

vari-pitch

double speed

MUX

Sync

Protector

EFM

demodulator

18-times

over samplling

filter

XRST

LOCK

APTR

APTL

LRCK

WDCK

SEIN

SENS

MIRR

CNIN

FOX

Error corrector

32K RAM

Priority

encoder

CPU interface

Servo

auto

sequencer

Serial/Parallel

processor

PSSL

DAO 1 to 6

MUTE

DOUT

MD 2

DATA

CLOK

XLAT

DATO

CLKO

XLTO

Asymmetry

correction.

Block Diagram

--4--

CXD2500BQ

D2500B

EXCK

SQSO

SQCK

MUTE

SENS

XRST

DATA

XLAT

CLOK

SEIN

CNIN

DATO

XLTO

CLKO

MIRR

SBSO

SCOR

WFCK

EMPH

DOUT

MD2

C16M

C4M

FSTT

XTSL

XTAQ

XTAI

APLL

APTR

DA01

DA02

DA03

DA04

DA05

DA06

DA07

DA08

DA09

DA10

DA11

DA12

DA13

DA14

DA15

DA16

LRCK

WDCK

PSSL

ASYE

ASYO

ASYI

BIAS

FOK

FSW

MON

MDP

MDS

LOCK

VCOO

VCOI

TEST

PDO

VPCO

VCKI

FILO

FILI

PCO

CLTV

Pin Configuration

--5--

CXD2500BQ

FOK

FSW

MON

MDP

MDS

LOCK

VCOO

VCOI

TEST

PDO

VPCO

VCKI

FILO

FILI

PCO

CLTV

BIAS

ASYI

ASYO

ASYE

PSSL

WDCK

LRCK

DA16

DA15

DA14

DA13

DA12

DA11

DA10

Z, 0

1, 0

1, Z, 0

1, 0

1, Z, 0

Analog

1, Z, 0

1, 0

Focus OK input. Used for SENS output and servo auto sequencer.

Output used to switch the spindle motor output filter.

Output for spindle motor ON/OFF control

Output for spindle motor servo control

Output is "H" when the GFS signal sampled at 460 Hz is "H". Output is

"L" when the GFS signal is "L" 8 or more times in succession.

Output of oscillation circuit for analog EFM PLL

Input to oscillation circuit for analog EFM PLL f

LOCK

=8.6436 MHz

Test. Normally at 0 V (GND).

Output of charge pump for analog EFM PLL

GND

Output of charge pump for vari-pitch PLL

Clock input from external VCO for vari-pitch control. fc

center

=16.9344 MHz.

Output of filter for master PLL (Slave=Digital PLL)

Input to filter for master PLL

Output of charge pump for master PLL

Analog GND

VCO control voltage input for master PLL

Analog power supply (+5 V)

EFM signal input

Asymmetry circuit constant current input

Asymmetry comparator circuit voltage input

EFM full-swing output

Asymmetry circuit OFF at "L". Asymmetry circuit ON at "H".

Input used to switch the audio data output mode. "L" for serial output,

"H" for parallel output.

D/A interface for 48-bit slot. Word clock f=2Fs

D/A interface for 48-bit slot. LR clock f=Fs

Power supply (+5 V)

Outputs DA16 (MSB) when PSSL=1, or serial data from the 48-bit slot

(2's complements, MSB first) when PSSL=0.

Outputs DA15 when PSSL=1, or bit clock from the 48-bit slot when PSSL=0.

Outputs DA14 when PSSL=1, or serial data from the 64-bit slot (2's

complements, LSB first) when PSSL=0.

Outputs DA13 when PSSL=1, or bit clock from the 64-bit slot when PSSL=0.

Outputs DA12 when PSSL=1, or LR clock from the 64-bit slot when PSSL=0.

Outputs DA11 when PSSL=1, or GTOP when PSSL=0.

Outputs DA10 when PSSL=1, or XUGF when PSSL=0.

Pin Description

Symbol

I/O

Description

No.

--6--

CXD2500BQ

DA09

DA08

DA07

DA06

DA05

DA04

DA03

DA02

DA01

APTR

APTL

VSS

XTAI

XTAO

XTSL

FSTT

C4M

C16M

MD2

DOUT

EMPH

WFCK

SCOR

SBSO

EXCK

SQSO

SQCK

MUTE

SENS

XRST

DATA

XLAT

CLOCK

SEIN

CNIN

DATO

XLTO

CLKO

MIRR

1, 0

1, Z, 0

1, 0

Outputs DA9 when PSSL=1, or XPLCK when PSSL=0.

Outputs DA8 when PSSL=1, or GFS when PSSL=0.

Outputs DA7 when PSSL=1, or RFCK when PSSL=0.

Outputs DA6 when PSSL=1, or C2PO when PSSL=0.

Outputs DA5 when PSSL=1, or XRAOF when PSSL=0.

Outputs DA4 when PSSL=1, or MNT3 when PSSL=0.

Outputs DA3 when PSSL=1, or MNT2 when PSSL=0.

Outputs DA2 when PSSL=1, or MNT1 when PSSL=0.

Outputs DA1 when PSSL=1, or MNT0 when PSSL=0.

Control output for aperture correction. "H" for R-ch.

Control output for aperture correction. "H" for L-ch.

GND

Input for 16.9344 MHz and 33.8688 MHz X'tal oscillation circuit.

Output for 16.9344 MHz X'tal oscillation circuit.

X'tal selection input. "L" for 16.9344 MHz X'tal, "H" for 33.8688 MHz X'tal.

2/3 frequency demultiplication output for Pins 53 and 54. Unaffected by

vari-pitch control.

4.2336 MHz output. Subject to vari-pitch control.

16.9344 MHz output. Subject to vari-pitch control.

Digital-Out ON/OFF control. "H" for ON, "L" for OFF.

Digital-Out output.

"H" for playback disc provided with emphasis, "L" for without emphasis.

WFCK (Write Frame Clock) output.

"H" when subcode Sync S0 or S1 is detected.

Serial output of Sub P to W

Clock input for reading SBSO

Outputs 80-bit Sub Q and 16-bit PCM peak-level data.

Clock input for reading SQSO

"H" for muting, "L" for release.

SENS output to CPU

System reset. "L" for resetting.

Inputs serial data from CPU.

Latches serial data input from CPU at falling edge.

Power supply (+5 V)

Inputs serial data transfer clock from CPU.

Inputs SENSE from SSP.

Inputs track jump count signal.

Outputs serial data to SSP.

Latches serial data output to SSP at falling edge.

Outputs serial data transfer clock to SSP.

Inputs mirror signal to be used by auto sequencer when jumping 16 or

more tracks.

Symbol

I/O

Description

No.

--7--

CXD2500BQ

Note:

· The data at the 64-bit slot is output in 2's complements on an LSB-first basis. The data at the 48-bit slot is

output in 2's complements on an MSB-first basis.

· GTOP monitors the state of Frame Sync protection. ("H": Sync protection window released)

· XUFG is a negative Frame Sync pulse obtained from the EFM signal before Frame Sync protection is

effected..

· XPLCK is an inversion of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK

coincides with a change point of the EFM signal.

· The GFS signal turns "H" upon coincidence between Frame Sync and the timing of interpolation protection.

· RFCK is a signal generated at 136-µs periods using a crystal oscillator.

· C2PO is a signal to indicate data error.

· XRAOF is a signal issued when a jitter margin of ±28F is exceeded by the 32K RAM.

--8--

CXD2500BQ

Electrical Character

DC characteristics

=AV

=5.0 V±5 %, V

=AV

=0 V, Topr=20 to +75°C)

Item

Condition

Min.

Typ.

Max.

Unit

Related pins

Input voltage.

"H" level

Input voltage

"L" level.

Input voltage

"H" level

Input voltage

"L" level

Input voltage

Output voltage

"H" level

Output voltage

"L" level

Output voltage

"H" level

Output voltage

"L" level

Output voltage

"L" level

Output voltage

"H" level

Output voltage

"L" level

Input leak current

Tristate pin output leak

current

(1)

(2)

(3)

(1)

(2)

(3)

(4)

Schmitt circuit

input

Analog input

=1 mA

=2 mA

=0.28 mA

=0.36 mA

=0 to 5.25 V

0.7V

0.3V

0.8V

0.2V

0.5

0.4

0.5

0.4

0.5

0.4

±5

µA

±5

µA

Output

Input

voltage (4)

voltage (3)

voltage (2)

voltage (1)

voltage (3)

voltage (2)

voltage (1)

Related pins

XTSL, DATA, XLAT, MD2, PSSL

CLOK, XRST, EXCK, SQCK, MUTE, FOK, SEIN, CNIN, MIRR, VCKI, ASYE

CLTV, FILI, RF

MDP, PDO, PCO, VPCO

ASYO, DOUT, FSTT, C4M, C16M, SBSO, SQSO, SCOR, EMPH, MON, LOCK, WDCK, DATO, CLKO,

XLTO, SENS, MDS, DA01 to DA16, APTR, APTL, LRCK, WFCK

FSW

FILO

SENS, MDS, MDP, FSW, PDO, PCO, VPCO

--9--

CXD2500BQ

AC Characteristics

(1) XTAI and VCOI pins

1) During self-oscillation

(Topr=20 to +75 °C, V

=AV

=5.0 V±5 %)

2) With pulses input to XTAI and VCOI pins

(Topr=20 to +75 °C, V

=AV

=5.0 V±5 %)

3) With sine waves input to XTAI and VCOI pins via capacitor

(Topr=20 to +75 °C, V

=AV

=5.0 V±5 %)

Item

Oscillation frequency

Symbol

MAX

Min.

Typ.

Max.

Unit

MHz

Item

Input amplitude

Symbol

Min.

2.0

Typ.

Max.

+0.3

Unit

Vp-p

Item

"H" level pulse width

"L" level pulse width

Pulse period

Input "H" level

Input "L" level

Rising time

Falling time

Symbol

WHX

WLX

IHX

ILX

, t

Min.

1.0

Typ.

Max.

500

1,000

0.8

Unit

WHX

WLX

XTAI

IHX

0.9

IHX

0.1

ILX

--10--

CXD2500BQ

(1) CLOK, DATA, XLAT, CNIN, SQCK, and EXCK pins

=AV

=5.0 V±5 %, V

=AV

=0 V, Topr=20 to +75 °C

Item

Clock frequency

Clock pulse width

Setup time

Hold time

Delay time

Latch pulse width

EXCK, CNIN, SQCK frequency

EXCK, CNIN, SQCK pulse width

Symbol

WCK

Min.

750

300

750

300

Typ.

Max.

0.65

Unit

MHz

1/f

WCK

CLOK

DATA

XLAT

WCK

1/f

EXCK
CNIN
SQCK

SUBQ
SQCK

Description of Functions

§1

CPU Interface and Commands

· CPU interface

This interface is used to set various modes using DATA, CLOK, and XLAT.

The interface timing chart is shown below.

CLOK

DATA

XLAT

Data

Address

300ns max

Valid

Registers 4 to E

750ns or more

· The command addresses of the CXD2500B and the data capable of being set are shown in Table 1-1.

· When XRST is set to 0, the CXD2500B is reset, causing its internal registers to be initialized to the values

listed in Table 1-2.

--11--

CXD2500BQ

name

Command

Auto sequence

Blind (A, E), Overflow (C)

Brake (B)

KICK (D)

Auto sequencer track

jump (N) setting

MODE specification

Func specification

Audio CTRL

Traverse monitor

counter setting

Servo factor setting

CLV CRTL

CLV mode

Address

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

Data 1

AS3

AS2

AS1

AS0

0.18 ms

0.09 ms

0.045 ms

0.022 ms

0.36 ms

0.18 ms

0.09 ms

0.045 ms

11.6 ms

5.8 ms

2.9 ms

1.45 ms

32,768

16,384

8,192

4,096

CDROM

D OUT

WSEL

Mute-F

D CLV

DSPB

A SEQ

D PLL

ON-OFF

Vari

Mute

ATT

Down

32,768

16,384

8,192

4,096

Gain

MDP1

MDP0

MDS1

MDS0

DCLV

CLVS

PWM MD

Gain

CM3

CM1

CM0

Data 2

--------

2,048

1,024

512

256

--------

BiliGL

FLFC

MAIN

SUB

PCT1

PCT2

2,048

1,024

512

256

--------

Data 3

--------

128

--------

128

--------

Data 4

--------

8421

--------

8421

--------

Commands

Table 1-1

--12--

CXD2500BQ

name

Command

Auto sequence

Blind (A, E), Overflow (C)

Brake (B)

KICK (D)

Auto sequencer

track jump setting

MODE specification

Func specification

Audio CTRL

Traverse monitor

counter setting

Servo factor setting

CLV CRTL

CLV mode

Address

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

Data 1

0000

0101

0111

0000

1001

0011

0000

0110

0000

Data 2

--------

0001

--------

000

0001

--------

Data 3

--------

0000

--------

0000

--------

Data 3

--------

0000

--------

0000

--------

Reset Initialization

Table 1-2

Example:

D3=0 D2=D1=D0=1 (Initial Reset)

D=10.15ms

$7X Command

Used to set the number of auto sequencer track jumps/moves.

This command sets the value of "N" for 2N track jump and M track move execution using the auto sequencer.

--13--

CXD2500BQ

§1

Meanings of Data Set at Command Addresses

$4X Command

Command

CANCEL

FOCUS-ON

1 TRACK JUMP

10 TRACK JUMP

2N TRACK JUMP

M TRACK MOVE

AS3

AS2

AS1

AS0

RXF

Command

Blind(A, E), Overflow(C)

Brake(B)

0.18 ms

0.36 ms

0.09 ms

0.18 ms

0.045 ms

0.09 ms

0.022 ms

0.045 ms

RXF=0 FORWARD

RXF=1 REVERSE

· If a Focus-ON command ($47) is canceled during execution, $02 is issued and the auto sequence operation

is discontinued.

· If a Track Jump or Track Move command ($48 to $4F) is canceled during execution, the auto sequence

operation is discontinued.

$5X Command

Used to set timers for the auto sequencer.

Timers set: A, E, C, and B

Example:

D2=D0=1, D3=D1=0 (Initial Reset)

A=E=C=0.112 ms

B=0.225 ms

$6X Command

Used to set a timer for the auto sequencer.

Timer set: D

Command

KICK (D)

11.6 ms

5.8 ms

2.9 ms

1.45 ms

Command

Auto sequencer track

jump number setting

Data3

Data 2

Data 3

Data 4

--14--

CXD2500BQ

· The maximum number of tracks that can be counted is 65,535. However, in the case of 2N track jumps, it is

subject to mechanical restrictions due to the optical system.

· When the number of tracks to be jumped is smaller that 15, the signals input from CNIN are counted. When

it is 16 or larger, the signals input from the MIRR pin are counted. This count signal selection contributes

toward improving the accuracy of high-speed track jumping.

$8X Command

Command

MODE specification

CDROM

D. OUT

Mute-F

AS0

WSEL

Command

CDROM=1

CDROM=0

C2PO timing

1-3

Processing

CDROM mode is entered. In this mode, average value

interpolation and preceding value holding are not performed.

Audio mode is entered. In this mode, average value

interpolation and preceding value holding are performed.

Command bit

D. out Mute F=1

D. out Mute F=0

Processing

When Digital Out is ON (pin MD2=1), DA output is muted.

Da output muting is unaffected by the setting of Digital Out.

D/A Out D.out Mute with F=1

Mute-ON

Mute-OFF

MD2=1

(D. out-ON)

MD2=0

(D. out-OFF)

0dB

Command bit

WSEL=1

WSEL=0

Sync protection window width

±26 channel clock pulses

±6 channel clock pulses

Application

Anti-rolling is enhanced.

Sync window protection is enhanced.

In normal-speed playback, the channel clock frequency is 4.3218 MHz.

$9X Command

Command

Func specification

Data 1

DCLV

DSPB

A. SEQ

D. PLL

ON-OFF

Data 2

BiliGL

FLFC

MAIN

Sub

--15--

CXD2500BQ

Contents

FSW=L, MON-H, MDS-Z, MDP=servo control signal, with carrier

frequency of 230 Hz at T

=0 and 460 Hz at T

FSW=Z, MON=H, MDS=speed control signal with carrier frequency of

7.35 kHz, MDP=phase control signal with carrier frequency of 1.84 kHz

MDS= PWM polarity signal. Carrier

DCLV when

frequency=132 kHz

PWM, MD=1

MDS= PWM absolute value output (binary).

Carrier frequency=132 kHz

MDS= Z

DCLV when

MDP= ternay PWM output.

PWM, MD=0

Carrier frequency=132 kHz

CLV mode

In CLVS mode

In CLVP mode

In CLVS or

CLVP mode

Command bit

DCLV ON-OFF=0

DCLV ON-OFF=1

(FSW and MON are

unnecessary)

In the Digital CLV servo mode with DCLV ON-OFF set to 1, the sampling frequency of the internal digital filter

is switched at the same time as the switching between CLVP and CLVS.

Therefore, for CLVS, the cut-off frequency fC is 70 Hz when T

is set to 0, and 140Hz when T

is set to 1.

Set FLFC at 1 when in double-speed playback mode (exclude the low power consumption special playback

mode). However, FLFC can be set to 0 during PLL pull-in (lock). Set to 0 for all other modes.

SENS Output

Processing

Normal-speed playback. ECC quadruple error correction is made. Vari-pitch

control is enabled.

Double-speed playback. ECC double error correction is made. Vari-pitch control

is disabled.

Command bit

DSPB=0

DSPB=1

ASEQ=1

SEIN (FZC)

SEIN (A, S)

SEIN (T. Z. C)

SEIN (SSTOP)

XBUSY

FOK

SEIN (Z)

GFS

COMP

COUT

OV64

ASEQ=0

GFS

COMP

COUT

OV64

Microcomputer serial register

values (Latching unnecessary)

$0X

$1X

$2X

$3X

$4X

$5X

$6X

$AX

$BX

$CX

$EX

$7X, 8X, 9X, DX, FX

--16--

CXD2500BQ

Description of SENS signals

SENS output

SEIN

XBUSY

FOK

GFS

COMP

COUT

OV64

Meaning

SENS is at High-Z state.

SEIN signal, which was input to the CXD2500B, is output from SSP.

"L" when auto sequencer is in operation; "H" when terminated.

Output of the signal (normally FOK input from RF) input to the FOK pin. "H" when

Focus OK is received.

"H" when regenerated Frame Sync is obtained at the correct time.

Used in counting the number of tracks set in register B. "H" when the count is

latched to register B twice in succession. It is reset to "L" level when the count of

CNIN inputs equals the originally set number for register B.

Used in counting the number of tracks set in register B. "H" when the count is

latched to register B, then to register C. It is toggled every time the count of CNIN

inputs reaches the value set in register B.

"L" when after passing through the sync detection filter, the EFM signal become

longer than the 64 channel clocks.

Command bit

DPLL=0

DPLL=1

Meaning

RFPLL enters analog mode. PDO, VCOI, and VCOO are used.

RFPLL enters digital mode. PDO becomes Z.

Command bit

BiliGL SUB=0

BiliGL SUB=1

BiliGL

MAIN=0

STEREO

SUB

BiliGL

MAIN=1

MAIN

Mute

Definition of Bilingual MAIN, SUB, and STEREO

MAIN; The input L-ch signal is output to both L-ch and R-ch.

Sub: The input R-ch signal is output to both L-ch and R-ch.

STEREO: The input L-ch and R-ch signals are output to both L-ch and R-ch respectively.

--17--

CXD2500BQ

$AX Command

Command

Audio CTRL

Data 1

Vari

Mute

ATT

DWN

Data 2

PCT1

PCT2

Vari UP

Vari DWN

Pitch

XTal 0%

VCO 0% +0.1% +0.2%

+0.3%

+0.2% +0.1%

+0%

-0.1%

-0.2%

XTal 0%

Command bit

Mute=0

Mute=1

Meaning

Muting is off unless condition to make muting occurs.

Muting is on. Peak register reset.

Command bit

ATT=0

ATT=1

Meaning

Attenuation is off.

12dB

Condition for Muting

(1) Mute=1 in register A

(2) Pin Mute=1

(3) D.OUT Mute F=1 in register 8 with D.Out ON (MD2=1)

(4) Elapse of over 35 msec after GFS turns "Low"

(5) BiliGL MAIN=Sub=1 in register 9

(6) PCT1=1 and PCT2=2 in register A

In the case of (1) to (4), zero-cross muting not exceeding 1 msec is performed.

Command bit

PCT1

PCT2

Meaning

Normal mode

Level meter mode

Peak meter mode

Normal mode

PCM Gain

0 dB

Mute

0 dB

ECC correction capacity

C1: Double, C2: Quadruple

C1: Double, C2: Double

Level Meter Mode (See Timing Chart 1-4.)

· This mode makes the digital level meter function available.

· Inputting 96-bit clock pulses to SQCK will enable 96 data to be output to SQSO. Of the output data, the first

80 bits comprise Sub-Q data, which transmit the description for the data format to the Sub Code interface.

The last 16 bits are ordered LSB-first, of which the first 15 bits constitute PCM data (absolute value). The

final 1 bit is "High" if the prior PCM data was generated at the left channel; "Low" if generated at the right

channel.

· The PCM data is reset once it is read, and the L/R flag is reversed. While this state is kept until the next

read operation is started, testing for the maximum value is conducted.

--18--

CXD2500BQ

Peak Meter Mode (See Timing Chart 1-5.)

· In this mode, the maximum value of PCM data is detected whether the channel involved is L-ch or R-ch.

To read the detected maximum value, it is necessary to input 96 clock pulses to SQCK.

· When 96 clock pulses have been input to SQCK, 96 bits of data is output to SQSO. At the same time, the

data is re-set in an internal register of the LSI.

That is, the PCM peak detection register is not reset when it is read.

· To reset the PCM peak register, set both PCT1 and PCT2 to 0. Or, Set $AX mute.

· In this mode, the absolute time of Subcode Q is controlled automatical.

· Namely, every time a peak value is detected, the absolute time when the CRC was passed is stored. The

program time operation is performed in the normal way.

· The last bit (L/R flag) of the 96-bit data stays 0.

· In this mode, the preceding value holding and average value interpolation data are fixed to level (

$CS Command

Command

Servo factor setting

CLV CTRL ($DX)

Gain

MDP1

MDP0

MDS1

MDS0

Gain

CLVS

Explanation

Only DCLV=1 is effective.

DCLV=1 and DCLV=0 are both

effective.

This command is used to externally set the spindle servo gain when DCLV=1.

· Gain setting for CLVS mode: GCLVS

Gain

GCLVS

MDS1

MDS0

CLVS

12dB

6dB

0dB

+6dB

Note:

When DCLV=0, the CLVS gain is

determined as follows:

If Gain CLVS=0, then GCLVS=12 dB.

If Gain CLVS=1, then GCLVS=0 dB

· Gain setting for CLVP mode: GMDP, GMDS

Gain

GMDP

MDP1

MDP0

6 dB

0 dB

+ 6dB

Gain

GMDS

MDS1

MDS0

6dB

0dB

+6dB

--19--

CXD2500BQ

$DC Command

Command

CLV CTRL

DCLV

PWM MD

CLVS

Gain

See "$CX Command."

Command bit

DCLV PWM MD=1

DCLV PWM MD=0

Description (See Timing Chart 1-6.)

Specification of PWM mode for digital CLV. Both MDS and MDP are used.

Specification of PWM mode for digital CLV. Ternary MDP values are output.

Command bit

TB=0

TB=1

TP=0

TP=1

Description

In CLVS or CLVH mode, bottom value is held at periods of RFCK/32.

In CLVS or CLVH mode, bottom value is held at periods of RFCK/16.

In CLVS mode, peak value is held at periods of RFCK/4.

In CLVS mode, peak value is held at periods of RFCK/2.

In CLVH mode, peak holding is made at 34 kHz.

$EX Command

Command

CLV mode

CM3

CM2

CM1

CM0

CM3

CM2

CM1

CM0

Mode

STOP

KICK

BRAKE

CLVS

CLVH

CLVP

CLVA

Explanation

See Timing Chart 1-7.

See Timing Chart 1-8.

See Timing Chart 1-9.

STOP:

Spindle motor stop mode

KICK:

Spindle motor forward run mode

BRAKE: Spindle motor reverse run mode

CLVS:

Rough servo mode for use for pulling disc run into RF-PLL capture range when the RF-PLL circuit

lock has been disengaged

CLVP:

PLL servo mode

CLVA:

Automatic switching mode for CLVS and CLVS. This mode is used during normal play status.

--26--

CXD2500BQ

§2

Subcode Interface

In this section, the subcode interface will be explained.

The contents of the subcode interface can be externally read in two ways. The subcodes P through W totaling

8 bits can be read from SBSO by inputting EXCK to the CXD2500B.

Sub-Q can be read after conducting a CRC check on the 80bits of information in the subcode frame. First,

check SCOR and CRCF, then input 80 clock pulses to SQCK and read the data.

§2-1 P-W Subcode Read

These subcodes can be read by entering EXCK immediately after the fall of WFCK. (See Timing Chart 2-1.)

§2-2 80-bit Sub-Q Read

Figure 2-2 shows a block diagram of the peripheral part of the 80-bit Sub-Q register.

· The Sub Q regenerated on a bit-per-frame basis is input to the 80-bit serial/parallel register and the CRC

circuit.

· When the results of CRC of the 96-bit Sub-Q are OK, CRCF is set to 1 and the 96-bit data is output to

SQSO.

Furthermore, it is loaded into the 80-bit, parallel/serial register.

If SQSO is "H" after the output of SCOR, it can be taken that CPU has been loaded a new set of CRCOK

data.

· When 80-bit data is loaded into CXD2500B, MSB and LSB are reversed within each byte of the data.

Therefore, the bits are ordered LSB-first within each byte, even though the byte arrangement is kept

unchanged.

· When 80 bits of data are confirmed to have been loaded, SQCK is input to read the data. Subsequently in

the CXD2500B, the input of SQCK is detected and the retriggerable monostable multivibrator is reset during

Low.

· The time constant of the retriggerable monostable multivibrator ranges from 270 to 400 µs. If the time of

High for SQCK is less than this time constant, the monostable multivibrator will keep resetting, preventing the

contents of the P/S register from being loaded into the P/S register.

· While the monostable multivibrator is resetting, data loading into the peak detection parallel/serial register

and 80-bit parallel/serial register is forbidden.

Therefore, while data read operation is carried out at clock periods shorter than the time constant of the

monostable multivibrator, the contents of these registers are retained without being rewritten by CRCOK, etc.

· The CXD2500B permits the peak detection register to be connected to the shift-in of the 80-bit P/S register.

For Ring Control 1, the input and output are short-circuited during peak meter and level meter mode.

For Ring Control 2, the input and output are short-circuited during peak meter mode only.

The Ring Controls are arranged in this way in order for the registers to be reset each time their contents are

read in the level meter mode, while preventing destructive read in the peak meter mode.

To enable this control, 96 clock pulses must be input to the peak meter mode.

· As afore mentioned, in the peak meter mode, the absolute time following the generation of a peak value is

stored.

These operations are shown in Time chart 2-3.

Note: To perform the above operations, the duration of the clock pulse input to SQCK must be between 750ns

and 120 µs for both "High" and "Low".

DDRS

)

(
ASEC

)

B-

G
H

80 bi

t
S

/
P

egi

t
er

80 bi

t
P

/
S

egi

t
er

r
der

I
n

r
s

i
o

SUBQ

I
F

onos

t
abl

r
a

t
o

CRCC

ABS t

i
m

oad c

ont

r
o

f
o

r
peak

l
u

i
ng c

ont

r
o

l
1

16 bi

t
P

/
S

egi

t
er

i
ng c

ont

r
o

l
2

CRCF

eak

det

t
i
on

--28--

CXD2500BQ

Block Diagram 2-2

--30--

CXD2500BQ

§3

Other Functions

§3-1 Channel Clock Regeneration Using Digital PLL Circuit

· Demodulation of regenerated EFM signals using an optical system requires the use of channel clock pulses.

The EFM signal to be demodulated has been modulated into an integer multiple of the channel clock period

T, ranging from 3T to 11T.

To read the information conveyed by the EFM signal, it is essential to correctly recognize the integral value;

hence, the need to use channel clock pulses.

In an actual CD player, the pulse width of the EFM signal will vary, affected by fluctuations of the disc

rotation. For this reason, it is necessary to use a PLL in regenerating channel clock pulses.

Figure 3-1 shows a block diagram of the 3-stage PLL contained in the CXD2500B.

· The 1st-stage PLL is used for vari-pitch regeneration. To use this PLL, LPF and VCO are necessary as

external parts.

The minimum pitch variable possible is 0.1 %. The output of this 1st-stage PLL is used as the standard for

all the clock pulses used in the LSI.

When vari-pitch control is not in uses, connect the output pin of XTAO to VCKI.

· The 2nd-stage PLL generates high frequency clock pulses necessary for the 3rd-stage digital PLL.

· The 3rd-stage comprises a digital PLL used to regenerate the actual channel clock pulses. It realizes a

capture range of ±150 kHz (normal conditions) or more.

· The digital PLL features a secondary loop. It is controlled through the primary loop (phase) secondary loop

(frequency).

When FLFC=1, the secondary loop can be turned off.

· When high frequency components such as 3T, 4T, are deviated, turning off the secondary loop will provide

better play ability.

· However, the capture range will be 50 kHz.

--32--

CXD2500BQ

§3-2 Frame Sync Protection

· During CD player operation at normal speed, Frame Sync is recorded approximately once every 136 µs (at

7.35 kHz).

This signal can be used to identify the data within each frame. When Frame Sync cannot be recognized, the

data also cannot be identified; as a result, it is treated as an error. Therefore, correct Frame Sync

recognition is very important to ensure high play ability for the CD player.

· The CXD2500B employs window protection, front protection and rear protection to realize a powerful Frame

Sync protection. The CXD2500B offers two window widths, one for use when the player is subjected to

rotational disturbance and the other for use without such disturbance (WSEL=0/1).

The front protection counter is fixed at 13 and the rear protection counter at 3. Therefore, during normal play

back, when the frame sync cannot be detected due to damages on the disc. If the number to frames with

undetected Frame Sync exceeds 13, the window is released and the Frame Sync signal are re-synchronized.

If no Frame Sync is correctly detected in 3 successive frames immediately after Frame Sync re-

synchronization performed following a window release, the window is released at once.

§3-3 Error Correction

· On CDs, each data unit (8 bits) is formatted so that it is contained in two correction codes, C1 and C2. C1

consists of 28 bytes of information and 4-byte parity, whereas C2 is made up of 24 bytes of information and

4-byte parity. Both C1 and C2 comprise a read Solomon code with a minimum distance of 5.

· C1 realizes double corrections and C2 realizes quadruple corrections, both by the refined superstrategy

method.

· To prevent erroneous C2 corrections, C1 pointer based on the conditions of C1 error, EFM signal play back,

and player operation during C1 operation is attached to the corrected data.

· The status of error correction can be monitored from outside the LSI. It is indicated as shown in Table 3-2.

· When C2 pointer is High, this signifies uncorrectable data error. The data are either previous data held

subsitute the error, or an average value interpolation.

MNT3

MNT2

MNT1

MNT0

Description

C1: No error detected.

C1 pointer reset.

C1: 1 error corrected.

C1 pointer set.

C1: No error detected.

C1 pointer set.

C1: 1 error corrected.

C1 pointer set.

C1: 2 errors corrected.

C1 pointer set.

C1: Uncorrectable error.

C1 pointer set.

C2: No error detected.

C2 pointer reset.

C2: 1 error corrected.

C2 pointer reset.

C2: 2 errors corrected.

C2 pointer reset.

C2: 3 errors corrected.

C2 pointer reset.

C2: 4 errors corrected.

C2 pointer reset.

C2: Uncorrectable error.

C1 pointer copied.

C2: Uncorrectable error.

C2 pointer set.

Table 3-2 Indication of error correction status

--33--

CXD2500BQ

Normal - speed PB

RFCK

MNT3

MNT2

MNT1

MNT0

Strobe

t=Dependent on error

condition

C1 correction

C2 correction

Strobe

C4M

MNT0 to 3

Valid

Invalid

Valid

400 to 500nsec

Timing Chart 3-3

§3-4 DA Interface

· The CXD2500B has two modes of DA interface.

48-bit slot interface

This is an MSB-first interface made up of LRCK signals with 48-bit clock cycles per LRCK cycle. While

the LRCK signal is High, the data going through this interface is of the left channel.

64-bit slot interface

This is an LSB-first interface made up of LRCK signals with 64-bit clock cycles per LRCK cycle. While

the LRCK signal is Low, the data going through this interface is of the left channel.

176

--36--

CXD2500BQ

§3-5 Digital Out

There are three digital-out formats: type 1 for use at broadcasting stations, type 2, form 1 for use in general

civil applications, and type 2, form 2 for use in software production. The CXD2500B supports type 2, form 1.

The clock accuracy for the channel status is automatically set at Level II when the X'tal clock is used, or

Level III when vari-pitch control is made.

CRC checks are conducted on the Sub-Q data on the first 4 bits (bits 0-3). The data is input only after two

checks are passed in succession.

The X'tal clock is set to 34 MHz, and variable pitch is reset. When D out is output at DSPB=1, set MD2 to 0

and turn off D out 34.

Digital Out C bit

From sub-Q

ID0

ID1 COPY Emph

0/1

Bits 0-3: Sub-Q control bits required to pass the CRC twice in succession.

bit 29:

Varipitch: 1

X'tal: 0

Table 3-6 Digital Out C bits

§3-6 Servo Auto Sequencer

The servo auto sequencer controls a series of operation including auto-focusing and track jumping. When an

auto sequence command is received from CPU, the servo auto sequencer automatically executes auto-

focusing, 1-track jumping, 2N track jumping and M track moving.

During auto sequence execution (X Busy=Low), as SSP (servo signal processing LSI) is used exclusively,

commands from CPU are not transferred to SSP. Instead, the commands can be sent to CXD2500B.

To make this servo auto sequencer usable, connect a CPU, RF and SSP to the CXD2500B as shown in

Figure 3-7 and set A.SEQ ON-OFF of Register 9 to ON.

When the CLOK changes from Low to High while XBUSY is at Low, from that point on to a maximum of 100

µsec, X BUSY does not become High.

Due to the monostable multivibrator which is reset when CLOK is Low (XBUSY=Low), transfer of erroneous

data to SSP is prevented when XBUSY changes from Low to High.

--37--

CXD2500BQ

(a)

Auto Focus ($47)

In auto focus operation, `focus search up' is performed, FOK and FZC are checked, and the focus servo

is turned on. When $47 is received from CPU, the focus servo is turned on through the steps shown in

Figure 3-8. Since this auto focus sequence begins with `focus search up,' it requires the pickup to be

put down (focus search down) beforehand.

Blind E of Register 5 is used to eliminate chattering from FZC. The focus servo is turned on at the

trailing edge of FZC after staying High continuously for a longer period than E.

System Configuration for Auto Sequencer Operation (Example)

MIRR

FOK

C.out

SENS

DATA

CLK

XLT

MIRR

FOK

CNIN

SEIN

DATO

CLKO

XLTO

CXD2500B

DATA

CLOK

XLAT

SENS

Micro-computer

SSP

Figure 3-7

--39--

CXD2500BQ

(b) Track

Jump

Track jump operation includes 1, 10 and 2N track jumps. Do not perform this track jump unless the focus,

tracking and sled servos are on. Such steps as tracking gain up and braking are not included in this track

jump. Therefore, the commands for tracking gain up and brake ON ($17) must be issued in advance.

· 1-track jump

When a $48 is received from CPU (or a $49 from REV), the servo auto sequencer executes a FWD

(REV) 1-track jump as shown Figure 3-9. The values of blind A and brake B must be set in Register 5.

· 10-track jump

When a $4H is received from CPU (or a $4B from REV), the servo auto sequencer executes a FWD

(REV) 10-track jump as shown in Figure 3-10. The principal difference between the 1-track and 10-track

jumps is whether the sled is kicked or not. In the 10-track jump, the actuator after being kicked is braked

when CNIN has been counted 5 tracks. When the actuator has adequately slowed down as a result of

braking, the tracking and sled servos are turned on (this actuator slow-down is detected by checking

whether the CNIN period has exceeded overflow C specified in Register 5).

· 2N track jump

When a $4C is received from CPU (or a $4D from REV), the servo auto sequencer executes a FWD

(REV) 2N track jump. The number of tracks to be jumped is determined by N, set Register 7 beforehand.

The maximum permissible number is 2

. In actual use, however, it is subject to limitation imposed by the

actuator.

When N is smaller than 16, the jumps are counted by means of counting CNIN signals. If N is 16 and

above, MIRR signals are counted instead of CNIN signals.

The 2N track jump sequence is basically the same as the 10-track jump sequence. The only difference

between them is that, in the 2N track jump sequence, the sled is kept moving for time D specified in

· M track move

When a $4E is received from CPU (or a $4F from REV), the servo auto sequencer executes a FWD

(REV) M-track move as shown in Figure 3-12. The maximum value that can be set from M is 2

. The

track moves are counted in the same way as for 2N track jumps. That is, when M is smaller than 16, the

moves are counted by means of counting CNIN signals. If M is 16 and above, MIRR signals are counted

instead of the CNIN signals. In this M track move, only the sled is moved. This method is suitable for a

large track move ranging from several thousand to several tens of thousand tracks.

--44--

CXD2500BQ

§3-7 Digital CLV

The digital CLV is a digital spindle servo, of which its block diagram is shown in Figure 3-14. It is capable of

outputting MDS or MDP error signals by the PWM method after raising the sampling frequency up to 130 kHz

based on the normal speed in the CLVS, CLVP and other modes. It also permits gain setting.

Digital CLV

CLVS U/D

MDS Error

MDP Error

Measure

0, 6dB

Gain

CLV P/S

2/1 MUX

GP(Gain)

CLV P

CLV S

CLV P/S

Noise Shape

Modulation

Mode Select

DCLVMD

MDP

MDS

KICK, BRAKE STOP

Measure

Gs(Gain)

Over Sampling

Filter-1

1/2

Mux

Over Sampling

Filter-2

Figure 3-14 Block diagram

--46--

CXD2500BQ

Vee

GND

C2PO

MUTE

WDCK

DATA

BCLK

LRCK

DEMP

GND

CLK

MUTE

SCOR

SQCK

SUBQ

GFS

XLT

DATA

XRST

SENS

FOK

LDON

MNT0

MNT1

MNT2

MNT3

GND

FOK

FSW

MON

MOP

MOS

LOCK

VCOO

VCOI

TEST1

PDO

VPCO

VCKI

FILO

FILI

PCO

CLTV

MIRR
CLKO

XLTO

DATO

CNIN

SEIN

CLOK

XLAT

DATA

XRST

SENS

MUTE

SQCK

SQSO

EXCK

SBSO

SCOR

WFCK

EMPH

DOUT

MO2

C16M

C4M

FSTT

XTSL

XTAO

XTAI

APTL

APTR

MNT0

MNT1

MNT2

MNT3

RADF

C2PO

RFCK

GFS

PLCK

BIAS

ASTI

ASTO

ASYE

NC
PSSL

WDCK (48)

DATA (64)

BCLK (64)

DATA (64)

BCLK (64)

LRCK (64)
GTOP

XUGF

LRCK (48)

GND

200p

GND

RAOV

RFCK

GFS

PLCK

UGFS

STTP

GND

WFCK

DOUT

GND

TRACK-D

GND

FOCUS-D

GND

SLED-D

GND

SPIND-D

GND

SSTOP

GND

LDON

GND

SLD

SPD

C10

C23

C26

C28

C27

R10

C35

R12

R11

R14

R13

DFCT

FOK

C17

C15

C16

C14

C13

C11

C12

RV1

RV2

MIRR

FGD

FS3

FLB

FEO

FE-

SRCH

TGU

TG2

TAO

TA-

CC2

CC1

FOK

EFM

ASY

DFCT

MIRR

DGND

SENS

COUT

XRST

FDFCT

FZC

ATSC

TDFCT

TZC

DVee

RFO

RFI

SL+
SLO

SL-

FSET

ISET

SSTOP

AVee

DIRC
LOCK

CLK

XLT

DATA

CXA1372Q

CXD2500BQ

Application Circuit

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party and other right due to same.

PACKAGE STRUCTURE

SONY CODE

EIAJ CODE

JEDEC CODE

QFP-80P-L01

QFP080-P-1420-A

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

EPOXY RESIN

SOLDER PLATING

COPPER / 42 ALLOY

1.6g

23.9 ± 0.4

20.0 0.1

+ 0.4

0.8

0.35 0.1

+ 0.15

14.0 0.1

+ 0.4

17.9 ±

0.4

16.3

0.1 0.05

+ 0.2

2.75 0.15

+ 0.35

0.8 ±

0.2

0.15 0.05

+ 0.1

80PIN QFP (PLASTIC)

0.12

0.15

0° to 10°

DETAIL A

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

EPOXY RESIN

SOLDER PLATING

42 ALLOY

80PIN QFP (PLASTIC)

20.0 0.1

+ 0.4

24.0 ± 0.3

0.8

0.35 0.1

+ 0.15

± 0.12

14.0 0.1

+ 0.4

18.0 ±

0.3

0.15 0.05

+ 0.1

16.6

0.1 0.05

+ 0.2

0.7 ±

0.1

2.7 ± 0.1

3.1 MAX

0.15

0° to 10°

22.6

QFP-80P-L121

QFP080-P-1420-AX

1.6g

Package Outline Unit : mm

CXD2500BQ

--47--

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXD2500BQ