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Description

The CXD2588Q/R is a digital signal processor LSI

for CD players. This LSI incorporates a digital servo,
digital filter, zero detection circuit, 1-bit DAC and
analog low-pass filter on a single chip.

Features
Digital Signal Processor (DSP) Block
· Playback mode which supports CAV (Constant

Angular Velocity)
· Frame jitter free
· 0.5

to 4

continuous playback possible

· Allows relative rotational velocity readout
· Supports spindle external control

· Wide capture range playback mode

· Spindle rotational velocity following method
· Supports normal-speed, 4

speed playback

· 16K RAM
· EFM data demodulation
· Enhanced EFM frame sync signal protection
· SEC strategy-based error correction
· Subcode demodulation and Sub Q data error

detection

· Digital spindle servo
· 16-bit traverse counter
· Asymmetry compensation circuit
· CPU interface on serial bus
· Error correction monitor signal, etc. output from a

new CPU interface

· Servo auto sequencer
· Digital audio interface outputs
· Digital level meter, peak meter
· CD TEXT data demodulation

Digital Servo (DSSP) Block
· Microcomputer software-based flexible servo control
· Offset cancel function for servo error signal
· Auto gain control function for servo loop
· E:F balance, focus bias adjustment functions
· Surf jump function supporting micro two-axis

Digital Filter, DAC and Analog Low-Pass Filter Blocks
· DBB (digital bass boost) function
· Double-speed playback supported
· Digital de-emphasis
· Digital attenuation
· Zero detection function
· 8Fs oversampling digital filter
· S/N: 100dB or more (master clock: 384Fs, typ.)
· Logical value: 109dB
· THD + N: 0.007% or less (master clock: 384Fs, typ.)
· Rejection band attenuation: 60dB or less

Applications

CD players

Structure

Silicon gate CMOS IC

Absolute Maximum Ratings
· Supply voltage

0.3 to +7.0

· Input voltage

0.3 to +7.0

0.3V to V

+ 0.3)

· Output voltage

0.3 to +7.0

· Storage temperature Tstg

40 to +125

°C

· Supply voltage difference

0.3 to +0.3

Recommended Operating Conditions
· Supply voltage

DDNote)

+2.7 to +5.5

· Operating temperature Topr

20 to +75

°C

Note) The V

for the CXD2588Q/R varies according

to the playback speed selection.

CXD2588Q/R

E97519-PS

CD Digital Signal Processor with Built-in Digital Servo and DAC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXD2588Q

100 pin QFP (Plastic)

CXD2588R

100 pin LQFP (Plastic)

Playback
speed

CD-DSP block

DAC block

4.75 to 5.25

3.0 to 5.5

4.5 to 5.5

2.7 to 5.5

[V]

I/O Capacitance
· Input pin

11 (Max.)

· Output pin

11 (Max.)

· I/O pin

I/O

11 (Max.)

Note) Measurement conditions V

= V

= 0V

= 1MHz

For the availability of this product, please contact the sales office.

CXD2588Q/R

Block Diagram

PWM

AOUT1

AIN1

LOUT1

AOUT2

AIN2

LOUT2

3rd-Order

Noise Shaper

Over Sampling

Digital Filter

Serial-In

Interface

LMUT

RMUT

XTAO

XTAI

Timing

Logic

XRST

TEST

TES1

D/A

Interface

DOUT

EFM

demodurator

Error

Corrector

16K

RAM

Digital

OUT

Sub Code
Processor

Clock

Generator

Asymmetry

Corrector

Digital

PLL

CPU

Interface

Servo

Auto

Sequencer

DAC Block

RFAC

ASYI

ASYO

BIAS

FSTO

FILO

FILI

PCO

CLTV

MDP

PWMI

SENS

DATA

XLAT

CLOK

SPOA

SPOB

XLON

SCOR

SBSO

EXCK

SERVO

Interface

SCLK

COUT

SSTP

ATSK

MIRR

DFCT

FOK

MIRR

DFCT

FOK

SERVO DSP

FOCUS SERVO

TRACKING

SERVO

SLED SERVO

PWM GENERATOR

FOCUS PWM

GENERATOR

TRACKING PWM

GENERATOR

SLED PWM

GENERATOR

FFDR

FRDR

TFDR

TRDR

SFDR

SRDR

RFDC

IGEN

OPAmp

Analog SW

A/D

Converter

I
O

OSC

XPCK

C4M

SQSO

SQCK

LOCK

Digital

CLV

FSTI

TES2

Signal Processor
Block

Servo Block

CXD2588Q/R

Pin Configuration (CXD2588Q)

I
R

I
L

I
A

I
G

I
O

XTSL

TES1

TEST

FRDR

FFDR

TRDR

TFDR

SRDR

SFDR

FSTI

FSTO

SSTP

MDP

LOCK

FOK

DFCT

70 69 68 67

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

100

PCMDI

BCK

BCKI

EMPH

EMPHI

XTAI

XTAO

AOUT1

AIN1

LOUT1

LOUT2

AIN2

AOUT2

RMUT

CXD2588Q/R

Pin Configuration (CXD2588R)

I
L

I
A

I
G

I
O

LRCK

LRCKI

PCMD

PCMDI

BCK

BCKI

EMPH

EMPHI

XTAI

XTAO

AOUT1

AIN1

LOUT1

LOUT2

AIN2

AOUT2

RMUT

LMUT

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

100

70 69 68 67

XTSL

TES1

TEST

FRDR

FFDR

TRDR

TFDR

SRDR

SFDR

FSTI

FSTO

SSTP

MDP

LOCK

FOK

DFCT

MIRR

COUT

WDCK

CXD2588Q/R

Pin Description

CXD
2588Q

Symbol

Output

values

Description

Sub Q 80-bit, PCM peak and level data outputs. CD TEXT data
output.

SQSO readout clock input.

Sub Q P to W serial output.

SBSO readout clock input.

System reset. Reset when low.

Mute input. Muted when high.

Serial data input from CPU.

Latch input from CPU. Serial data is latched at the falling edge.

Serial data transfer clock input from CPU.

SENS output to CPU.

SENS serial data readout clock input.

Spindle motor external control input.

Digital power supply.

Anti-shock input/output.

Microcomputer extension interface (input A)

Microcomputer extension interface (input B)

Microcomputer extension interface (output)

WFCK output.

XUGF output. MINT1 or RFCK is output by switching with the command.

XPCK output. MNT0 is output by switching with the command.

GFS output. MNT3 or XROF is output by switching with the command.

C2PO output. GTOP is output by switching with the command.

Outputs a high signal when either subcode sync S0 or S1 is detected.

4.2336MHz output. In CAV-W mode, 1/4 frequency division output for VCKI.

Word clock output. f = 2Fs.

Track count signal input/output.

Mirror signal input/output.

Defect signal input/output.

Focus OK signal input/output.

GFS is sampled at 460Hz; when GFS is high, this pin outputs a
high signal. If GFS is low eight consecutive samples, this pin
outputs low. Or input when LKIN = 1.

Spindle motor servo control output.

Disc innermost track detection signal input.

2/3 frequency division output for XTAI pin.

1, 0

1, Z, 0

1, 0

I/O

SQSO

SQCK

SBSO

EXCK

XRST

SYSM

DATA

XLAT

CLOK

SENS

SCLK

PWMI

ATSK

SPOA

SPOB

XLON

WFCK

XUGF

XPCK

GFS

C2PO

SCOR

C4M

WDCK

COUT

MIRR

DFCT

FOK

LOCK

MDP

SSTP

FSTO

I/O

CXD
2588R

Pin No.

CXD2588Q/R

CXD
2588Q

Symbol

Output

values

Description

2/3 frequency division input for XTAI pin.

Sled drive output.

Tracking drive output.

Focus drive output.

Digital GND.

Test pin. Normally, GND.

Crystal selection input. Low when the crystal is 16.9344MHz; high
when the crystal is 33.8688MHz.

Center voltage input.

Focus error signal input.

Sled error signal input.

Tracking error signal input.

Center servo analog input.

RF signal input.

Test pin. No connected.

Analog GND.

Operational amplifier constant current input.

Analog power supply.

EFM full-swing output. (low = Vss, high = V

)

Asymmetry comparator voltage input.

Asymmetry circuit constant current input.

EFM signal input.

Analog GND.

Multiplier VCO1 control voltage input.

Master PLL filter output. (slave = digital PLL)

Master PLL filter input.

Master PLL charge pump output.

Analog power supply.

Wide-band EFM PLL VCO2 control voltage input.

Wide-band EFM PLL VCO2 oscillation input.

1, 0

Analog

1, 0

Analog

1, Z, 0

FSTI

SFDR

SRDR

TFDR

TRDR

FFDR

FRDR

TEST

TES1

XTSL

RFDC

ADIO

IGEN

ASYO

ASYI

BIAS

RFAC

CLTV

FILO

FILI

PCO

VCTL

VCKI

I/O

CXD
2588R

Pin No.

CXD2588Q/R

CXD
2588Q

Symbol

Output

values

Description

Wide-band EFM PLL VCO2 oscillation output.

Wide-band EFM PLL charge pump output.

Digital GND.

Test pin. Normally GND.

Digital power supply.

Digital Out output.

D/A interface. LR clock output f = Fs.

D/A interface. LR clock input.

D/A interface. Serial data output.
(two's complement, MSB first)

D/A interface. Serial data input.
(two's complement, MSB first)

D/A interface. Bit clock output.

D/A interface. Bit clock input.

Outputs a high signal when the playback disc has emphasis, and a
low signal when there is no emphasis.

Inputs a high signal when de-emphasis is on, and a low signal when
de-emphasis is off.

Master clock power supply.

Crystal oscillation circuit input. Master clock is externally input from
this pin.

Crystal oscillation circuit output.

Master clock GND.

Analog power supply.

L ch analog output.

L ch operational amplifier input.

L ch LINE output.

Analog GND.

R ch LINE output.

R ch operational amplifier output.

R ch analog output.

Analog power supply.

R ch zero detection flag.

L ch zero detection flag.

1, 0

1, Z, 0

1, 0

V16M

VPCO

TES2

DOUT

LRCK

KRCKI

PCMD

PCMDI

BCK

BCKI

EMPH

EMPHI

XTAI

XTAO

AOUT1

AIN1

LOUT1

LOUT2

AIN2

AOUT2

RMUT

LMUT

100

I/O

CXD
2588R

Pin No.

CXD2588Q/R

Notes) · PCMD is a MSB first, two's complement output.

· GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)

· XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before

sync protection.

· XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the

EFM signal transition point coincide.

· The GFS signal goes high when the frame sync and the insertion timing match.

· RFCK is derived from the crystal accuracy, and has a cycle of 136µs.

· C2PO represents the data error status.

· XROF is generated when the 16K RAM exceeds the ±4F jitter margin.

Monitor Pin Output Combinations

MTSL1

MTSL0

XUGF

MNT1

RFCK

XPCK

MNT0

XPCK

GFS

MNT3

XROF

C2PO

GTOP

Command bit

Output data

CXD2588Q/R

Electrical Characteristics

1. DC Characteristics

= AV

= 5.0V ± 5%, V

= AV

= 0V, Topr = 20 to +75°C)

Applicable pins

SYSM, DATA, XLAT, PWMI, SSTP, FSTI, XTSL, TEST, TES1, VCKI, TES2

SQCK, XRST, CLOK

LRCKI, PCMDI, BCKI, EMPHI

ASYI, RFAC, CLTV, FILI, VCTL

SQSO, SBSO, SENS, ATSK, XLON, WFCK, XUGF, XPCK, GFS, C2PO, SCOR, C4M, WDCK, COUT,

MIRR, DFCT, FOK, LOCK, FSTO, SFDR, SRDR, TFDR, TRDR, FFDR, FRDR, ASYO, DOUT, LRCK,

PCMD, BCK, EMPH, RMUT, LMUT

V16M

MDP, PCO, VPCO

FILO

VC, FE, SE, TE, CE

RFDC

EXCK, ATSK, COUT, MIRR, DFCT, FOK, LOCK

SCLK, SPOA, SPOB

Item

Input
voltage (1)

Input
voltage (2)

Input
voltage (3)

Input
voltage (4)

Output
Avoltage (1)

Output
Avoltage (2)

Output
Avoltage (3)

Output
Avoltage (4)

Input leak current (1)

Input leak current (2)

Input leak current (3)

Input leak current (4)

11,

Schmitt input

Analog input

= 2mA

= 4mA

= 8mA

= 6mA

= 4mA

= 0.28mA

= 0.36mA

= V

or V

= V

or V

= 1.5 to 3.5V

= 0 to 5.0V

High level input voltage

Low level input voltage

High level input voltage

Low level input voltage

High level input voltage

Low level input voltage

Input voltage

High level output voltage

Low level output voltage

High level output voltage

Low level output voltage

High level output voltage

Low level output voltage

High level output voltage

Low level output voltage

(1)

(2)

(3)

(4)

(1)

(2)

(3)

(4)

(1)

(2)

(3)

(4)

0.7V

0.8V

Vss

0.8

Vss

0.8

Vss

0.8

Vss

0.5

Vss

0.3V

0.2V

0.4

600

µA

Conditions

Min.

Typ.

Max.

Unit

Applicable
pins

CXD2588Q/R

2. AC Characteristics

(1) XTAI pin

(a) When using self-excited oscillation

(Topr = 20 to +75°C, V

= AV

= 5.0V ± 5%)

(b) When inputting pulses to XTAI pin

(Topr = 20 to +75°C, V

= AV

= 5.0V ± 5%)

(Topr = 20 to +75°C, V

= AV

= 5.0V ± 5%)

Oscillation
frequency

MAX

MHz

Item

Symbol

Min.

Typ.

Max.

Unit

High level pulse
width

WHX

500

Low level pulse
width

WLX

500

Pulse cycle

1,000

Input high level

IHX

1.0

Input low level

ILX

0.8

Rise time, fall
time

Item

Symbol

Min.

Typ.

Max.

Unit

Input amplitude

2.0

+ 0.3 Vp-p

Item

Symbol

Min.

Typ.

Max.

Unit

WHX

WLX

ILX

IHX

0.1

IHX

0.9

IHX

XTAI

CXD2588Q/R

(2) CLOK, DATA, XLAT, COUT, SQCK, and EXCK pins

= AV

= 5.0V ± 5%, V

= AV

= 0V, Topr = 20 to +75°C)

Note) In quasi double-speed playback mode, except when SQSO is Sub Q Read, the SQCK maximum

operating frequency is 300kHz and its minimum pulse width is 1.5µs.

(3) BCKI, LRCKI and PCMDI pins (V

= AV

= 5.0V ± 5%, V

= AV

= 0V, Topr = 20 to +75°C)

Clock frequency

Clock pulse width

Setup time

Hold time

Delay time

Latch pulse width

EXCK, SQCK frequency

EXCK, SQCK pulse width

WCK

750

300

750

Note)

0.65

Note)

MHz

Item

Symbol

Min.

Typ.

Max.

Unit

WCK

1/f

CLOK

DATA

XLAT

EXCK

SQCK

SBSO

SQSO

BCK pulse width

DATAL, R setup time

DATAL, R hold time

LRCK setup time

Item

Symbol Conditions

Typ.

Min.

Max.

Unit

(BCKI) t

(BCKI)

(PCMDI)

(LRCKI)

BCKI

PCMDI

LRCKI

CXD2588Q/R

(5) COUT, MIRR and DFCT pins

Operating frequency (V

= AV

= 5.0V ± 5%, V

= AV

= 0V, Topr = 20 to +75°C)

COUT maximum
operating frequency

MIRR maximum
operating frequency

DFCT maximum
operating frequency

COUT

MIRR

DFCTH

kHz

Item

Symbol

Min.

Typ.

Max.

Unit

Conditions

When using a high-speed traverse TZC

When the RF signal continuously satisfies the following conditions during the above traverse.

· A = 0.12V

to 0.26V

= 25%

During complete RF signal omission

When settings related to DFCT signal generation are Typ.

(4) SCLK pin

SCLK frequency

SCLK pulse width

Delay time

SCLK

SPW

DLS

31.3

MHz

µs

Item

Symbol

Min.

Typ.

Max.

Unit

SPW

DLS

1/f

SCLK

MSB

LSB

···

XLAT

SCLK

Serial Read Out Data

(SENS)

A + B

CXD2588Q/R

1-bit DAC and LPF Block Analog Characteristics

Analog characteristics (V

= AV

= 5.0V, V

= AV

= 0V, Ta = 25°C)

Fs = 44.1kHz in all cases.

The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below.

LPF external circuit diagram

Block diagram of analog characteristics measurement

Item

Total harmonic
distortion

Signal-to-noise
ratio

Symbol

THD

S/N

Conditions

1kHz, 0dB data

Crystal

1kHz, 0dB data
(Using A-weighting filter)

384Fs

768Fs

384Fs

768Fs

0.0050

0.0045

100

0.0070

0.0065

Min.

Typ.

Max.

Unit

Audio Analyzer

SHIBASOKU (AM51A)

100k

22µ

680p

12k

150p

AOUT1 (2)

AIN1 (2)

LOUT1 (2)

Audio Analyzer

CXD2588Q/R

Rch

Lch

DATA

TEST DISC

768Fs/384Fs

CXD2588Q/R

= AV

= 5.0V, V

= AV

= 0V, Topr = 20 to +75°C)

Output voltage

Load resistance

OUT

Vrms

Item

Symbol

Min.

Max.

1.12

Typ.

Applicable pins

Unit

Measurement is conducted for the LPF external circuit diagram with the sine wave output of 1kHz and 0dB.

Applicable pins

LOUT1, LOUT2

CXD2588Q/R

Contents

§1. CPU Interface

§1-1.

CPU Interface Timing ........................................................................................................................ 16

§1-2.

CPU Interface Command Table ........................................................................................................ 16

§1-3.

CPU Command Presets .................................................................................................................... 26

§1-4.

Description of SENS Signals and Commands ................................................................................... 31

§2. Subcode Interface

§2-1.

P to W Subcode Readout .................................................................................................................. 51

§2-2.

80-bit Sub Q Readout ........................................................................................................................ 51

§3. Description of Modes

§3-1.

CLV-N Mode ...................................................................................................................................... 56

§3-2.

CLV-W Mode ..................................................................................................................................... 56

§3-3.

CAV-W Mode ..................................................................................................................................... 56

§4. Description of Other Functions

§4-1.

Channel Clock Regeneration by the Digital PLL Circuit .................................................................... 58

§4-2.

Frame Sync Protection ...................................................................................................................... 60

§4-3.

Error Correction ................................................................................................................................. 60

§4-4.

DA Interface ....................................................................................................................................... 61

§4-5.

Digital Out .......................................................................................................................................... 63

§4-6.

Servo Auto Sequence ....................................................................................................................... 63

§4-7.

Digital CLV ......................................................................................................................................... 70

§4-8.

CD-DSP Block Playback Speed ........................................................................................................ 71

§4-9.

DAC Block Playback Speed .............................................................................................................. 71

§4-10. DAC Block Input Timing .................................................................................................................... 72
§4-11. Description of DAC Block Functions .................................................................................................. 72
§4-12. LPF Block .......................................................................................................................................... 76
§4-13. Asymmetry Compensation ................................................................................................................ 77
§4-14. CD Text Data Demodulation .............................................................................................................. 78

§5. Description of Servo Signal Processing System Functions and Commands

§5-1.

General Description of Servo Signal Processing System .................................................................. 80

§5-2.

Digital Servo Block Master Clock (MCK) ........................................................................................... 81

§5-3.

AVRG Measurement and Compensation .......................................................................................... 81

§5-4.

E:F Balance Adjustment Function ..................................................................................................... 83

§5-5.

FCS Bias Adjustment Function .......................................................................................................... 83

§5-6.

AGCNTL Function ............................................................................................................................. 85

§5-7.

FCS Servo and FCS Search ............................................................................................................. 87

§5-8.

TRK and SLD Servo Control ............................................................................................................. 88

§5-9.

MIRR and DFCT Signal Generation .................................................................................................. 89

§5-10. DFCT Countermeasure Circuit .......................................................................................................... 90
§5-11. Anti-Shock Circuit .............................................................................................................................. 90
§5-12. Brake Circuit ...................................................................................................................................... 91
§5-13. COUT Signal ..................................................................................................................................... 92
§5-14. Serial Readout Circuit ........................................................................................................................ 92
§5-15. Writing to the Coefficient RAM .......................................................................................................... 93
§5-16. PWM Output ...................................................................................................................................... 93
§5-17. Servo Status Changes Produced by the LOCK Signal ..................................................................... 95
§5-18. Description of Commands and Data Sets ......................................................................................... 95
§5-19. List of Servo Filter Coefficients ........................................................................................................ 110
§5-20. Filter Composition ............................................................................................................................ 112
§5-21. TRACKING and FOCUS Frequency Response .............................................................................. 119

§6. Application Circuit .................................................................................................................................. 120

Explanation of abbreviations

AVRG:

Average

AGCNTL: Auto gain control
FCS:

Focus

TRK:

Tracking

SLD:

Sled

DFCT:

Defect

CXD2588Q/R

§1. CPU Interface

§1-1. CPU Interface Timing

· CPU interface

This interface uses DATA, CLOK and XLAT to set the modes.

The interface timing chart is shown below.

· The internal registers are initialized by a reset when XRST = 0.

Note) Be sure to set SQCK to high when XLAT is low.

§1-2. CPU Interface Command Table

Total bit length for each register

0 to 2

4 to 6

8 bits

8 to 24 bits

8 bits

20 bits

28 bits

24 bits

28 bits

16 bits

8 bits

16 bits

20 bits

Total bit length

750ns or more

D18

D19

D20

D21

D22

D23

750ns or more

Valid

CLOK

DATA

XLAT

Registers

CXD2588Q/R

Command Table ($0X to 1X)

FOCUS SERVO ON

(FOCUS GAIN

NORMAL)

FOCUS SERVO ON

(FOCUS GAIN

DOWN)

FOCUS SERVO OFF,

0V OUT

FOCUS SERVO OFF,

FOCUS SEARCH

VOLTAGE OUT

FOCUS SEARCH

VOLTAGE DOWN

FOCUS SEACH

VOLTAGE UP

ANTI SHOCK ON

ANTI SHOCK OFF

BRAKE ON

BRAKE OFF

TRACKING GAIN

NORMAL

TRACKING GAIN UP

FILTER SELECT 1

TRACKING GAIN UP

FILTER SELECT 2

0 0 0 0

0 0 0 1

FOCUS

CONTROL

TRACKING

CONTROL

Command

Address

D23 to D20

Data 1

D19

D18

D17

D16

Data 2

D15

D14

D13

D12

Data 3

D11

D10

Data 4

Data 5

--: Don't care

CXD2588Q/R

Command Table ($2X to 3X)

TRACKING SERVO OFF

TRACKING SERVO ON

FORWARD TRACK JUMP

REVERSE TRACK JUMP

SLED SERVO OFF

SLED SERVO ON

FORWARD SLED MOVE

REVERSE SLED MOVE

SLED KICK LEVEL

(
±

basic value) (Default)

SLED KICK LEVEL

(
±

basic value)

SLED KICK LEVEL

(
±

basic value)

SLED KICK LEVEL

(
±

basic value)

0 0 1 0

0 0 1 1

TRACKING

MODE

SELECT

Command

Address

D23 to D20

Command

Address

D23 to D20

Data 1

D19

D18

D17

D16

Data 1

D19

D18

D17

D16

Data 2

D15

D14

D13

D12

Data 2

D15

D14

D13

D12

Data 3

D11

D10

Data 4

Data 5

Data 3

D11

D10

Data 4

Data 5

--: Don't care

CXD2588Q/R

Command Table ($340X)

KRAM DATA (K00)

SLED INPUT GAIN

KRAM DATA (K01)

SLED LOW BOOST FILTER A-H

KRAM DATA (K02)

SLED LOW BOOST FILTER A-L

KRAM DATA (K03)

SLED LOW BOOST FILTER B-H

KRAM DATA (K04)

SLED LOW BOOST FILTER B-L

KRAM DATA (K05)

SLED OUTPUT GAIN

KRAM DATA (K06)

FOCUS INPUT GAIN

KRAM DATA (K07)

SLED AUTO GAIN

KRAM DATA (K08)

FOCUS HIGH CUT FILTER A

KRAM DATA (K09)

FOCUS HIGH CUT FILTER B

KRAM DATA (K0A)

FOCUS LOW BOOST FILTER A-H

KRAM DATA (K0B)

FOCUS LOW BOOST FILTER A-L

KRAM DATA (K0C)

FOCUS LOW BOOST FILTER B-H

KRAM DATA (K0D)

FOCUS LOW BOOST FILTER B-L

KRAM DATA (K0E)

FOCUS PHASE COMPENSATE FILTER A

KRAM DATA (K0F)

FOCUS DEFECT HOLD GAIN

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

0 0 1 1

0 1 0 0

0 0 0 0

SELECT

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11

D10

Data 1

Data 2

CXD2588Q/R

Command Table ($341X)

KRAM DATA (K10)

FOCUS PHASE COMPENSATE FILTER B

KRAM DATA (K11)

FOCUS OUTPUT GAIN

KRAM DATA (K12)

ANTI SHOCK INPUT GAIN

KRAM DATA (K13)

FOCUS AUTO GAIN

KRAM DATA (K14)

HPTZC / AUTO GAIN HIGH PASS FILTER A

KRAM DATA (K15)

HPTZC / AUTO GAIN HIGH PASS FILTER B

KRAM DATA (K16)

ANTI SHOCK HIGH PASS FILTER A

KRAM DATA (K17)

HPTZC / AUTO GAIN LOW PASS FILTER B

KRAM DATA (K18)

FIX

KRAM DATA (K19)

TRACKING INPUT GAIN

KRAM DATA (K1A)

TRACKING HIGH CUT FILTER A

KRAM DATA (K1B)

TRACKING HIGH CUT FILTER B

KRAM DATA (K1C)

TRACKING LOW BOOST FILTER A-H

KRAM DATA (K1D)

TRACKING LOW BOOST FILTER A-L

KRAM DATA (K1E)

TRACKING LOW BOOST FILTER B-H

KRAM DATA (K1F)

TRACKING LOW BOOST FILTER B-L

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

0 0 1 1

0 1 0 0

0 0 0 1

SELECT

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11

D10

Data 1

Data 2

CXD2588Q/R

Command Table ($342X)

KRAM DATA (K20)

TRACKING PHASE COMPENSATE FILTER A

KRAM DATA (K21)

TRACKING PHASE COMPENSATE FILTER B

KRAM DATA (K22)

TRACKING OUTPUT GAIN

KRAM DATA (K23)

TRACKING AUTO GAIN

KRAM DATA (K24)

FOCUS GAIN DOWN HIGH CUT FILTER A

KRAM DATA (K25)

FOCUS GAIN DOWN HIGH CUT FILTER B

KRAM DATA (K26)

FOCUS GAIN DOWN LOW BOOST FILTER A-H

KRAM DATA (K27)

FOCUS GAIN DOWN LOW BOOST FILTER A-L

KRAM DATA (K28)

FOCUS GAIN DOWN LOW BOOST FILTER B-H

KRAM DATA (K29)

FOCUS GAIN DOWN LOW BOOST FILTER B-L

KRAM DATA (K2A)

FOCUS GAIN DOWN PHASE COMPENSATE FILTER A

KRAM DATA (K2B)

FOCUS GAIN DOWN DEFECT HOLD GAIN

KRAM DATA (K2C)

FOCUS GAIN DOWN PHASE COMPENSATE FILTER B

KRAM DATA (K2D)

FOCUS GAIN DOWN OUTPUT GAIN

KRAM DATA (K2E)

NOT USED

KRAM DATA (K2F)

NOT USED

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

0 0 1 1

0 1 0 0

0 0 1 0

SELECT

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11

D10

Data 1

Data 2

CXD2588Q/R

Command Table ($343X)

KRAM DATA (K30)

SLED INPUT GAIN (when SFSK = 1 TG up2)

KRAM DATA (K31)

ANTI SHOCK LOW PASS FILTER B

KRAM DATA (K32)

NOT USED

KRAM DATA (K33)

ANTI SHOCK HIGH PASS FILTER B-H

KRAM DATA (K34)

ANTI SHOCK HIGH PASS FILTER B-L

KRAM DATA (K35)

ANTI SHOCK FILTER COMPARATE GAIN

KRAM DATA (K36)

TRACKING GAIN UP2 HIGH CUT FILTER A

KRAM DATA (K37)

TRACKING GAIN UP2 HIGH CUT FILTER B

KRAM DATA (K38)

TRACKING GAIN UP2 LOW BOOST FILTER A-H

KRAM DATA (K39)

TRACKING GAIN UP2 LOW BOOST FILTER A-L

KRAM DATA (K3A)

TRACKING GAIN UP2 LOW BOOST FILTER B-H

KRAM DATA (K3B)

TRACKING GAIN UP2 LOW BOOST FILTER B-L

KRAM DATA (K3C)

TRACKING GAIN UP PHASE COMPENSATE FILTER A

KRAM DATA (K3D)

TRACKING GAIN UP PHASE COMPENSATE FILTER B

KRAM DATA (K3E)

TRACKING GAIN UP OUTPUT GAIN

KRAM DATA (K3F)

NOT USED

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

0 0 1 1

0 1 0 0

0 0 1 1

SELECT

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11

D10

Data 1

Data 2

CXD2588Q/R

Command Table ($344X)

KRAM DATA (K40)

TRACKING HOLD FILTER INPUT GAIN

KRAM DATA (K41)

TRACKING HOLD FILTER A-H

KRAM DATA (K42)

TRACKING HOLD FILTER A-L

KRAM DATA (K43)

TRACKING HOLD FILTER B-H

KRAM DATA (K44)

TRACKING HOLD FILTER B-L

KRAM DATA (K45)

TRACKING HOLD FILTER OUTPUT GAIN

KRAM DATA (K46)

TRACKING HOLD INPUT GAIN (when THSK = 1 TG up2)

KRAM DATA (K47)

NOT USED

KRAM DATA (K48)

FOCUS HOLD FILTER INPUT GAIN

KRAM DATA (K49)

FOCUS HOLD FILTER A-H

KRAM DATA (K4A)

FOCUS HOLD FILTER A-L

KRAM DATA (K4B)

FOCUS HOLD FILTER B-H

KRAM DATA (K4C)

FOCUS HOLD FILTER B-L

KRAM DATA (K4D)

FOCUS HOLD FILTER OUTPUT GAIN

KRAM DATA (K4E)

NOT USED

KRAM DATA (K4F)

NOT USED

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

0 0 1 1

0 1 0 0

SELECT

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11

D10

Data 1

Data 2

CXD2588Q/R

Command Table ($34FX to 3FX)

0 0 1 1

FOCUS BIAS LIMIT

FOCUS BIAS DATA

TRVSC DATA

FOCUS SEARCH SPEED/

VOLTAGE/AUTO GAIN

DTZC/TRACK JUMP

VOLTAGE/AUTO GAIN

FZSL/SLED MOVE/

Voltage/AUTO GAIN

LEVEL/AUTO GAIN/

DFSW/ (Initialize)

SERIAL DATA READ

MODE/SELECT

FOCUS BIAS

Operation for MIRR/

DFCT/FOK

TZC/COUT

BOTTOM/MIRR

SLED FILTER

Filter

Others

0 0 1 1

FBL9

FB9

TV9

FBL8

FB8

TV8

FBL7

FB7

TV7

FBL6

FB6

TV6

FBL5

FB5

TV5

FBL4

FB4

TV4

FBL3

FB3

TV3

FBL2

FB2

TV2

FBL1

FB1

TV1

TV0

FT1

TDZC

FZSH

VCLM

DAC

SFO2

FT0

DTZC

FZSL

VCLC

SD6

FBON

SFO1

FS5

TJ5

SM5

FLM

SD5

FBSS

SDF2

FS4

TJ4

SM4

FLC0

SD4

FBUP

SDF1

FS3

TJ3

SM3

RFLM

SD3

FBV1

MAX2

FS2

TJ2

SM2

RFLC

SD2

FBV0

MAX1

FS1

TJ1

SM1

AGF

SD1

SFOX

FS0

TJ0

SM0

AGT

SD0

TJD0

BTF

FTZ

SFJP

AGS

DFSW

FPS1

D2V2

FG6

TG6

AGJ

LKSW

FPS0

D2V1

FG5

TG5

AGGF

TBLM

TPS1

D1V2

FG4

TG4

AGGT

TCLM

TPS0

D1V1

FG3

TG3

AGV1

FLC1

RINT

FG2

TG2

AGV2

TLC2

SJHD

FG1

TG1

AGHS

TLC1

INBK

FG0

TG0

AGHT

TLC0

MTI0

F1NM

F1DM

AGG4

F3NM

XT4D

F3DM

XT2D

T1NM

T1UM

DRR2

T3NM

DRR1

T3UM

DRR0

DFIS

TLCD

ASFG

FTQ

LKIN

LPAS

COIN

SRO1

MDFI

MIRI

AGHF

XT1D

ASOT

COSS

SFID

COTS

SFSK

CETZ

THID

CETF

THSK

COT2

COT1

TLD2

MOT2

TLD1

TLD0

BTS1

BTS0

MRC1

MRC0

SELECT

Command

Address 1

D23 to D20

D19

D18

D17

D16

Address 2

D15

D14

D13

D12

Data 1

D11

D10

Data 2

Data 3

Address

D23 to D20

D19

D18

D17

D16

Data 1

D15

D14

D13

D12

Data 2

D11

D10

Data 3

Data 4

--: Don't care

CXD2588Q/R

Instruction Table

Auto sequence

Blind (A, E),

Overflow (C)

Brake (B)

KICK (D)

Auto sequence (N)

track jump

count setting

MODE

specification

Function

specification

Audio CTRL

Serial bus

CTRL

Spindle servo

coefficient setting

CLV CTRL

CLV mode

2048

VCO

SEL1

TRMI

VP7

EPWM

1024

TRMO

VP6

SPDC

512

SOCT

OPSL2

MTSL1

VP5

ICAP

256

VCO

SEL2

SYCOF

EMPH

MTSL0

VP4

SFSL

128

KSL3

OPSL1

SMUT

VP3

VC2C

KSL2

MCSL

VP2

HIFC

KSL1

AD9

VP1

LPWR

KSL0

AD8

VP0

VPON

ZDPL

AD7

Gain

CAV1

ZMUT

AD6

Gain

CAV0

VCO2

THRU

AD5

AD4

AD3

DCOF

AD2

AD1

AD0

TXON

FMUT

TXOUT

LRWO

OUTL1

BSBST

OUTL0

BBSL

AS3

0.18ms

0.36ms

11.6ms

32768

CDROM

SL1

Gain

MDP1

CM3

AS2

0.09ms

0.18ms

5.8ms

16384

DOUT

Mute

DSPB

ON/OFF

DSPB

ON/OFF

SL0

Gain

MDP0

CM2

AS1

0.05ms

0.09ms

2.9ms

8192

DOUT

ON/OFF

Mute

CPUSR

Gain

MDS1

CM1

AS0

0.02ms

0.05ms

1.45ms

4096

WSEL

ATT

Gain

MDS0

Gain

CLVS

CM0

Command

Address

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

CXD2588Q/R

FOCUS SERVO OFF,

0V OUT

TRACKING GAIN UP

FILTER SELECT 1

TRACKING SERVO OFF

SLED SERVO OFF

SLED KICK LEVEL

(
±

basic value) (Default)

KRAM DATA

($3400XX to $344fXX)

0 0 0 0

0 0 0 1

0 0 1 0

FOCUS

CONTROL

TRACKING

CONTROL

TRACKING

MODE

Command

Address

D23 to D20

Data 1

D19

D18

D17

D16

Data 2

D15

D14

D13

D12

Data 3

D11

D10

Data 4

Data 5

Command

SELECT

Address

D23 to D20

0 0 1 1

See "Coefficient ROM Preset Values Table".

Data 1

D19

D18

D17

D16

Data 2

D15

D14

D13

D12

Data 3

D11

D10

Data 4

Data 5

Address 1

D23 to D20

D19

D18

D17

D16

Address 2

D15

D14

D13

D12

Address 3

D11

D10

Data 1

Data 2

§1-3. CPU Command Presets

Command Preset Table ($0X to 34X)

--: Don't care

CXD2588Q/R

Command Preset Table ($34FX to 3FX)

0 0 1 1

FOCUS BIAS LIMIT

FOCUS BIAS DATA

TRVSC DATA

FOCUS SEARCH SPEED/

VOLTAGE AUTO GAIN

DTZC/TRACK JUMP

VOLTAGE AUTO GAIN

FZSL/SLED MOVE/

Voltage/AUTO GAIN

LEVEL/AUTO GAIN/

DFSW/ (Initialize)

SERIAL DATA READ

MODE/SELECT

FOCUS BIAS

Operation for MIRR/

DFCT/FOK

TZC/COUT

BOTTOM/MIRR

SLED FILTER

0 0 1 1

Filter

Others

SELECT

Command

Address 1

D23 to D20

D19

D18

D17

D16

Address 2

D15

D14

D13

D12

Data 1

D11

D10

Data 2

Data 3

Address

D23 to D20

D19

D18

D17

D16

Data 1

D15

D14

D13

D12

Data 2

D11

D10

Data 3

Data 4

--: Don't care

CXD2588Q/R

Reset Initialization

Auto sequence

Blind (A, E),

Overflow (C)

Brake (B)

KICK (D)

Auto sequence (N)

track jump

count setting

MODE

specification

Function

specification

Audio CTRL

Serial bus

CTRL

Spindle servo

coefficient setting

CLV CTRL

CLV mode

Command

Address

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

CXD2588Q/R

<Coefficient ROM Preset Values Table (1)>

ADDRESS

K00
K01
K02
K03
K04
K05
K06
K07
K08
K09

K0A
K0B

K0C
K0D

K0E

K0F

81
23

10
14
30

46
81

58
82

SLED INPUT GAIN
SLED LOW BOOST FILTER A-H
SLED LOW BOOST FILTER A-L
SLED LOW BOOST FILTER B-H
SLED LOW BOOST FILTER B-L
SLED OUTPUT GAIN
FOCUS INPUT GAIN
SLED AUTO GAIN
FOCUS HIGH CUT FILTER A
FOCUS HIGH CUT FILTER B
FOCUS LOW BOOST FILTER A-H
FOCUS LOW BOOST FILTER A-L
FOCUS LOW BOOST FILTER B-H
FOCUS LOW BOOST FILTER B-L
FOCUS PHASE COMPENSATE FILTER A
FOCUS DEFECT HOLD GAIN

K10
K11
K12
K13
K14
K15
K16
K17
K18
K19

K1A
K1B

K1C
K1D

K1E

K1F

K20
K21
K22
K23
K24
K25
K26
K27
K28
K29

K2A
K2B

K2C
K2D

K2E

K2F

32
20
30
80
77
80
77
00

F1
7F

81
44

FOCUS PHASE COMPENSATE FILTER B
FOCUS OUTPUT GAIN
ANTI SHOCK INPUT GAIN
FOCUS AUTO GAIN
HPTZC / Auto Gain HIGH PASS FILTER A
HPTZC / Auto Gain HIGH PASS FILTER B
ANTI SHOCK HIGH PASS FILTER A
HPTZC / Auto Gain LOW PASS FILTER B
Fix

TRACKING INPUT GAIN
TRACKING HIGH CUT FILTER A
TRACKING HIGH CUT FILTER B
TRACKING LOW BOOST FILTER A-H
TRACKING LOW BOOST FILTER A-L
TRACKING LOW BOOST FILTER B-H
TRACKING LOW BOOST FILTER B-L

82
44
18
30

46
81

66
82
44

4E
1B

00
00

TRACKING PHASE COMPENSATE FILTER A
TRACKING PHASE COMPENSATE FILTER B
TRACKING OUTPUT GAIN
TRACKING AUTO GAIN
FOCUS GAIN DOWN HIGH CUT FILTER A
FOCUS GAIN DOWN HIGH CUT FILTER B
FOCUS GAIN DOWN LOW BOOST FILTER A-H
FOCUS GAIN DOWN LOW BOOST FILTER A-L
FOCUS GAIN DOWN LOW BOOST FILTER B-H
FOCUS GAIN DOWN LOW BOOST FILTER B-L
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
FOCUS GAIN DOWN DEFECT HOLD GAIN
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
FOCUS GAIN DOWN OUTPUT GAIN
NOT USED
NOT USED

DATA

CONTENTS

Fix indicates that normal preset values should be used.

CXD2588Q/R

<Coefficient ROM Preset Values Table (2)>

ADDRESS

K30
K31
K32
K33
K34
K35
K36
K37
K38
K39

K3A
K3B

K3C
K3D

K3E

K3F

80
66
00

80
44

77
86

57
00

SLED INPUT GAIN (Only when TRK Gain Up2 is accessed with SFSK = 1.)
ANTI SHOCK LOW PASS FILTER B
NOT USED
ANTI SHOCK HIGH PASS FILTER B-H
ANTI SHOCK HIGH PASS FILTER B-L
ANTI SHOCK FILTER COMPARATE GAIN
TRACKING GAIN UP2 HIGH CUT FILTER A
TRACKING GAIN UP2 HIGH CUT FILTER B
TRACKING GAIN UP2 LOW BOOST FILTER A-H
TRACKING GAIN UP2 LOW BOOST FILTER A-L
TRACKING GAIN UP2 LOW BOOST FILTER B-H
TRACKING GAIN UP2 LOW BOOST FILTER B-L
TRACKING GAIN UP PHASE COMPENSATE FILTER A
TRACKING GAIN UP PHASE COMPENSATE FILTER B
TRACKING GAIN UP OUTPUT GAIN
NOT USED

K40
K41
K42
K43
K44
K45
K46
K47
K48
K49

K4A
K4B

K4C
K4D

K4E

K4F

7F
7F

79
17

00
00
02

7F
7F

79
17
54
00
00

TRACKING HOLD FILTER INPUT GAIN
TRACKING HOLD FILTER A-H
TRACKING HOLD FILTER A-L
TRACKING HOLD FILTER B-H
TRACKING HOLD FILTER B-L
TRACKING HOLD FILTER OUTPUT GAIN
TRACKING HOLD FILTER INPUT GAIN (Only when TRK Gain Up2 is a accessed with THSK = 1.)
NOT USED
FOCUS HOLD FILTER INPUT GAIN
FOCUS HOLD FILTER A-H
FOCUS HOLD FILTER A-L
FOCUS HOLD FILTER B-H
FOCUS HOLD FILTER B-L
FOCUS HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED

DATA

CONTENTS

CXD2588Q/R

§1-4. Description of SENS Signals and Commands

SENS output

The SENS output can be read from the SQSO pin when SOUT = 0, SL1 = 1 and SL0 = 0.

$38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement.

SSTP is output in all other cases.

Microcomputer serial register
(latching not required)

$0X

$1X

$2X

$30 to 37

$38

$3904

$3908

$390C

$391C

$391D

$391F

$3A

$3B to 3F

$4X

$5X

$6X, 7X, 8X, 9X

$AX

$BX

$CX

$DX

$EX

$FX

SENS output

FZC

As (Anti Shock)

TZC

SSTP

AGOK

XA VEBSY

TE Avrg Reg.

FE Avrg Reg.

VC Avrg Reg.

TRVSC Reg.

FB Reg.

RFDC Avrg. Reg.

FBIAS count STOP

SSTP

XBUSY

FOK

GFS

COUT frequency division

OV64

Output data length

9bit

8bit

Description of SENS Signals

Low while the auto sequencer is in operation, high when operation terminates.

Outputs the same signal as the FOK pin.
High for "focus OK".

High when the regenerated frame sync is obtained with the correct timing.

Counts the number of tracks with frequency division ratio set by $B.
High when $C is latched, and toggles each time COUT is counted just for the frequency
division ratio set by $B.

Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing
through the sync detection filter.

XBUSY

FOK

GFS

COUT
frequency
division

OV64

SENS output

Contents

CXD2588Q/R

The meaning of the data for each address is explained below.

$4X commands

RXF = 0 FORWARD

RXF = 1 REVERSE

· When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted.

· When the Track jump/Move commands ($48 to $4F) are canceled, $25 is sent and the auto sequence is

interrupted.

$5X commands

Auto sequence timer setting

Set timers: A, E, C, B

e.g.) D2 = D0 = 1, D3 = D1 = 0 (Initial Reset)

A = E = C = 0.11ms

B = 0.23ms

$6X commands

Auto sequence timer setting

Set timer: D

e.g.) D3 = 0, D2 = D1 = D0 = 1 (Initial Reset)

D = 10.15ms

$7X commands

Auto sequence track jump/move count setting (N)

This command is used to set N when a 2N-track jump or N-track move is executed for auto sequence.

· The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count

depends on the mechanical limitations of the optical system.

· The number of tracks jumped is counted according to the COUT signals.

CANCEL

FOCUS-ON

1 TRACK JUMP

10 TRACK JUMP

2 NTRACK JUMP

N TRACK MOVE

RXF

Command

AS3

AS2

AS1

AS0

Blind (A, E), Over flow (C)

Brake (B)

0.18ms

0.36ms

0.09ms

0.18ms

0.05ms

0.09ms

0.02ms

0.05ms

Command

D23

D22

D21

D20

KICK (D)

11.6ms

5.8ms

2.9ms

1.45ms

Command

Data 1

Data 2

Data 3

Data 4

Auto sequence track jump
count setting

D23

D22

D21

D20

CXD2588Q/R

Command bit

C2PO timing

CDROM = 1

CDROM = 0

See Timing

Chart 1-1.

See Timing

Chart 1-1.

CDROM mode; average value interpolation and pre-value hold
are not performed.

Audio mode; average value interpolation and pre-value hold
are performed.

Processing

Command bit

DOUT Mute = 1

DOUT Mute = 0

Digital Out output is muted. (DA output is not muted.)

If other mute conditions are not set, Digital Out is not muted.

Processing

Command bit

DOUT ON/OFF = 1

DOUT ON/OFF = 0

Digital Out is output from the DOUT pin.

Digital Out is not output from the DOUT pin.

Processing

Command bit

Sync protection window width

WSEL = 1

WSEL = 0

±26 channel clock

±6 channel clock

Anti-rolling is enhanced.

Sync window protection is enhanced.

Application

In normal-speed playback, channel clock = 4.3218MHz.

Command

CDROM

DOUT

Mute

DOUT

ON/OFF

WSEL

VCO

SEL1

SOCT

VCO

SEL2

KSL3

KSL2

KSL1

KSL0

Data 1

Data 2

Mode
specification

Data 3

VCO2

THRU

TXON TXOUT OUTL1 OUTL0

Data 4

Data 5

Data 6

$8X commands

See "$BX Commands".

CXD2588Q/R

Command bit

VCOSEL1

Multiplier PLL VCO1 is set to normal speed, and the output is 1/1
frequency-divided.

Multiplier PLL VCO1 is set to normal speed, and the output is 1/2
frequency-divided.

Multiplier PLL VCO1 is set to normal speed, and the output is 1/4
frequency-divided.

Multiplier PLL VCO1 is set to normal speed, and the output is 1/8
frequency-divided.

Multiplier PLL VCO1 is set to high speed

, and the output is 1/1

frequency-divided.

Multiplier PLL VCO1 is set to high speed

, and the output is 1/2

frequency-divided.

Multiplier PLL VCO1 is set to high speed

, and the output is 1/4

frequency-divided.

Multiplier PLL VCO1 is set to high speed

, and the output is 1/8

frequency-divided.

KSL3

KSL2

Processing

Approximately twice the normal speed

Command bit

VCOSEL2

Wide-band PLL VCO2 is set to normal speed, and the output is 1/1
frequency-divided.

Wide-band PLL VCO2 is set to normal speed, and the output is 1/2
frequency-divided.

Wide-band PLL VCO2 is set to normal speed, and the output is 1/4
frequency-divided.

Wide-band PLL VCO2 is set to normal speed, and the output is 1/8
frequency-divided.

Wide-band PLL VCO2 is set to high speed

, and the output is 1/1

frequency-divided.

Wide-band PLL VCO2 is set to high speed

, and the output is 1/2

frequency-divided.

Wide-band PLL VCO2 is set to high speed

, and the output is 1/4

frequency-divided.

Wide-band PLL VCO2 is set to high speed

, and the output is 1/8

frequency-divided.

KSL1

KSL0

Processing

Approximately twice the normal speed

CXD2588Q/R

Command bit

VCO2 THRU = 0

Processing

V16M output is internally connected to VCKI. Set VCKI to low.

V16M output is not internally connected. Input the clock from VCKI.

These bits select the internal or external connection for the VCO2 used in CAV-W mode.

VCO2 THRU = 1

Command bit

TXON = 0

Processing

When CD TEXT data is not demodulated, set TXON to 0.

When CD TEXT data is demodulated, set TXON to 1.

See "$4-14. CD TEXT Data Demodulation"

TXON = 1

Command bit

TXOUT = 0

Processing

Various signals except for CD TEXT is output from the SQSO pin.

CD TEXT data is output from the SQSO pin.

See "$4-14. CD TEXT Data Demodulation"

TXOUT = 1

Command bit

OUTL1 = 0

Processing

WFCK, XPCK C4M, WDCK and FSTO are output. The signal input to FSTI is supplied
to the digital servo block.

WFCK, XPCK C4M, WDCK and FSTO outputs are set to low. FSTO and FSTI are
internally connected. Set FSTI to low.

OUTL1 = 1

Command bit

OUTL0 = 0

OUTL0 = 1

Processing

PCMD, BCK, LRCK and EMPH are output.

PCMD, BCK, LRCK and EMPH outputs are low.
PCMD and PCMDI, BCK and BCKI, LRCK and LRCKI and EMPH and EMPHI are
internally connected. Set PCMDI, BCKI, LRCKI and EMPHI to low.

CXD2588Q/R

Timing Chart 1-1

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CXD2588Q/R

$9X commands (OPSL1= 0)

Data 2 D0 and subsequent data are for DF/DAC function settings.

Command bit

DSPB = 1

DSPB = 0

Double-speed playback (CD-DSP block)

Normal-speed playback (CD-DSP block)

Processing

Command bit

SYCOF = 1

SYCOF = 0

LRCK asynchronous mode

Normal operation

Processing

Command bit

OPSL1 = 1

OPSL1 = 0

DCOF can be set.

DCOF cannot be set.

Processing

Command bit

MCSL = 1

MCSL = 0

DF/DAC block master clock selection. Crystal = 768Fs (33.8688MHz)

DF/DAC block master clock selection. Crystal = 384Fs (16.9344MHz)

Processing

Command

Data 1

DSPB

ON/OFF

MCSL

ZDPL ZMUT

Data 3

Data 4

Data 2

Function
specification

000 SYCOF

D3 to D1

OPSL1

Data 5

$9X commands (OPSL1= 1)

Data 2 D0 and subsequent data are for DF/DAC function settings.

Command

Data 1

DSPB

ON/OFF

MCSL

ZDPL ZMUT

Data 3

Data 4

Data 2

Function
specification

000 SYCOF

D3 to D1

OPSL1

DCOF

Data 5

Set SYCOF = 0 in advance when setting the $AX command LRWO to 1.

CXD2588Q/R

Command bit

ZDPL = 1

ZDPL = 0

LMUT and RMUT pins are high when muted.

LMUT and RMUT pins are low when muted.

Processing

See "Mute flag output" for the mute flag output conditions.

Command bit

DCOF = 1

DCOF = 0

DC offset is off.

DC offset is on.

Processing

DCOF can be set when OPSL1 = 1.

Set DC offset to off when zero detection mute is on.

Command bit

ZMUT = 1

ZMUT = 0

Zero detection mute is on.

Zero detection mute is off.

Processing

$AX commands (OPSL2 = 0)

Data 2 and subsequent data are for DF/DAC function settings.

Command

Data 1

Mute

ATT

EMPH

Data 2

Data 3

Audio CTRL

SMUT

OPSL2

Data 4

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

Data 5

Data 6

Data 3

AD9

AD8

$AX commands (OPSL2 = 1)

Data 2 and subsequent data are for DF/DAC function settings.

Command

Data 1

Mute

ATT

EMPH

Data 2

Data 3

Audio CTRL

SMUT

OPSL2

Data 4

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0 FMUT LRWO BSBST BBSL

Data 5

Data 6

Data 3

AD9

AD8

CXD2588Q/R

The attenuation data consists of 11 bits, and is set as follows.

Attenuation data

400h

3FEh

3FDh

001h

000h

0dB

0.0085dB
0.0170dB

60.206dB

Audio output

Command bit

EMPH = 1

EMPH = 0

De-emphasis is on.

De-emphasis is off.

Processing

If either the EMPHI pin or EMPH is high, de-emphasis is on.

If either the SMUT pin or SMUT is high, soft mute is on.

Command bit

SMUT = 1

SMUT = 0

Soft mute is on.

Soft mute is off.

Processing

Command bit

AD10 to 0

Attenuation data.

Meaning

Command bit

Mute = 1

Mute = 0

CD-DSP block mute is on. 0 data is output from the CD-DSP block.

CD-DSP block mute is off.

Processing

Command bit

ATT = 1

ATT = 0

CD-DSP block output is attenuated (12dB).

CD-DSP block output attenuation is off.

Processing

Command bit

OPSL2 = 1

OPSL2 = 0

FMUT, LRWO, BSBST and BBSL can be set.

FMUT, LRWO, BSBST and BBSL cannot be set.

Meaning

The attenuation data (AD10 to AD0) consists of 11bits,

and can be set in 1024 different ways in the range of

000h to 400h.

The audio output from 001h to 400h is obtained using

the following equation.

Audio output = 20log [dB]

Attenuation data

1024

CXD2588Q/R

Command bit

FMUT = 1

FMUT = 0

Forced mute is on.

Forced mute is off.

Meaning

FMUT can be set when OPSL2 = 1.

Command bit

BSBST = 1

BSBST = 0

Bass boost is on.

Bass boost is off.

Processing

BSBST can be set when OPSL2 = 1.

Command bit

BBSL = 1

BBSL = 0

Bass boost is Max.

Bass boost is Mid.

Processing

BBSL can be set when OPSL2 = 1.

Command bit

LRWO = 1

LRWO = 0

Forced synchronization mode

Note)

Normal operation.

Meaning

LRWO can be set when OPSL2 = 1.

Note) Synchronization is performed at the first falling edge of LRCK during reset, so there is normally no need

to set this mode. However, synchronization can be forcibly performed by setting LRWO = 1.

CXD2588Q/R

Command

SL1

SL0

CPUSR

TRM1

TRM0

MTSL1

MTSL0

Data 1

Data 2

Serial bus

CTRL

$BX commands

SOCT

SubQ

Peak meter

SENS

SubQ

SL1

SL0

mode

The SQSO pin output can be switched to the various

signals by setting the SOCT command of $8X and the SL1

and SL0 commands of $BX. Set SQCK to high at the

falling edge of XLAT.

Except for Sub Q and peak meter, the signals are loaded

to the register when they are set at the falling edge of

XLAT. Sub Q is loaded to the register with each SCOR,

and Peak meter is loaded when a peak is detected.

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CXD2588Q/R

Signal

PER0 to 7

FOK

GFS

LOCK

EMPH

ALOCK

VF0 to 7

SPOA, B

WFCK

SCOR

GTOP

RFCK

XRAOF

L0 to L7,

R0 to R7

RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB.

Focus OK

High when the frame sync and the insertion protection timing match.

GFS is sampled at 460Hz; when GFS is high, a high signal is output. If GFS is low eight
consecutive samples, a low signal is output.

High when the playback disc has emphasis.

GFS is sampled at 460Hz; when GFS is high eight consecutive samples, a high signal is
output. If GFS is low eight consecutive samples, a low signal is output.

Used in CAV-W mode. Results of measuring the disc rotational velocity. (See Timing Chart 2-3.)
VF0 = LSB, VF7 = MSB.

SPOA and B pin inputs.

Write frame clock output.

High when either subcode sync S0 or S1 is detected.

High when the sync protection window is open.

Read frame clock output.

Low when the built-in 16K RAM exceeds the ±4 frame jitter margin.

Peak meter register output. L0 to 7 are the left-channel and R0 to 7 are the right-channel peak
data. L0 and R0 are LSB.

Description

C1F1

No Error

Single Error Correction

Irretrievable Error

C1F2

C1 correction status

C2F1

No Error

Single Error Correction

Irretrievable Error

C2F2

C2 correction status

Command bit

CPUSR = 1

CPUSR = 0

XLON pin is high.

XLON pin is low.

Processing

CXD2588Q/R

Peak meter

SQSO

XLAT

SQCK

(Peak meter)

Setting the SOCT command of $8X to 0 and the SL1 and SL0 commands of $BX to 0 and 1, respectively,

results in peak detection mode. The SQSO output is connected to the peak register. The maximum PCM data

values (absolute value, upper 8bits) for the left and right channels can be read from SQSO by inputting 16

clocks to SQCK. Peak detection is not performed during SQCK input, and the peak register does not change

during readout. This SQCK input judgment uses a retriggerable monostable multivibrator with a time constant

of 270µs to 400µs. The time during which SQCK input is high should be 270µs or less. Also, peak detection is

restarted 270µs to 400µs after SQCK input.

The peak register is reset with each readout (16 clocks input to SQCK).

The maximum value in peak detection mode is detected and held in this status until the next readout. When

switching to peak detection mode, readout should be performed one time initially to reset the peak register.

Peak detection can also be performed for previous value hold and average value interpolation data.

Traverse monitor count value setting

These bits are set when monitoring the traverse condition of the SENS output according to the COUT

frequency division.

Command bit

1/64 frequency division

1/128 frequency division

1/256 frequency division

1/512 frequency division

TRM1

XUGF

MNT1

RFCK

XUGF

XPCK

MNT0

XPCK

GFS

MNT3

XROF

GFS

C2PO

GTOP

C2PO

MTSL1

Command bit

MTSL0

Symbol

TRM0

Processing

Output data

Monitor output switching

The monitor output can be switched to the various signals by setting the MTSL1 and MTSL0 commands of $B.

CXD2588Q/R

$CX commands

· CLV mode gain setting: GCLVS

· CLVP mode gain setting: GMDP: GMDS

Servo coefficient setting

CLV CTRL ($DX)

Gain

MDP1

Gain

MDP0

Gain

MDS1

Gain

MDS0

Gain

CLVS

Gain

MDS1

Gain

MDS0

Gain

CLVS

GCLVS

12dB

6dB

0dB

+6dB

Command

Gain

MDP1

Gain

MDP0

GMDP

6dB

0dB

+6dB

Gain

MDS1

Gain

MDS0

GMDS

6dB

0dB

+6dB

CXD2588Q/R

$DX commands

Command bit

Description

TB = 0

TB = 1

TP = 0

TP = 1

Bottom hold at a cycle of RFCK/32 in CLVS mode.

Bottom hold at a cycle of RFCK/16 in CLVS mode.

Peak hold at a cycle of RFCK/4 in CLVS mode.

Peak hold at a cycle of RFCK/2 in CLVS mode.

Command

Gain

CLVS

VP7

VP6

VP5

VP4

VP3

VP2

VP1

VP0

Data 1

Data 2

CLV CTRL

Data 3

See the $CX commands.

The rotational velocity R of the spindle can be

expressed with the following equation.

R =

256 n

R: Relative velocity at normal speed = 1

n: VP0 to 7 setting value

Note) · Values in parentheses are for when DSPB is 1.

· Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTSL is high.

· VP0 to 7 setting values are valid in CAV-W mode.

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1.5

0.5

VP0 to 7 setting value [HEX]

DSP

B = 0

2.5

3.5

Fig. 1-1

Command bit

Description

VP0 to 7 = F0 (H)

VP0 to 7 = E0 (H)

VP0 to 7 = C0 (H)

Playback at half (normal) speed

Playback at normal (double)
speed

Playback at (quadruple) speed

CXD2588Q/R

$EX commands

Command

Data 1

CLV mode

CM3

CM2

CM1

CM0

Data 2

EPWM SPDC

ICAP

SFSL

Data 3

VC2C

HIFC

LPWR VPON

Command bit

CM3

CM2

CM1

Description

Spindle stop mode.

Spindle forward rotation mode.

Spindle reverse rotation mode. Valid only when LPWR = 0
in any mode.

Rough servo mode. When the RF-PLL circuit isn't locked,
this mode is used to pull the disc rotations within the RF-
PLL capture range.

PLL servo mode.

Automatic CLVS/CLVP switching mode.
Used for normal playback.

CM0

Mode

STOP

KICK

BRAKE

CLVS

CLVP

CLVA

See Timing Charts 1-2 to 1-6.

Command bit

EPWM SPDC

ICAP

Description

Crystal reference CLV servo.

Used for normal-speed
playback in CLV-W mode.

Spindle control with VP0 to 7.

Spindle control with the external
PWM.

SFSL

VC2C

HIFC

LPWR

VPON

Mode

CLV-N

CLV-W

CAV-W

Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode.

CXD2588Q/R

Command

Data 4

SPD mode

Gain

CAV1

Gain

CAV0

Gain

CAV1

Gain

CAV0

Gain

0dB

6dB

12dB

18dB

· This sets the gain when controlling the spindle with the phase comparator

in CAV-W mode.

Mode

CLV-N

CLV-W

CAV-W

LPWR

Command

KICK

BRAKE

STOP

KICK

BRAKE

STOP

KICK

BRAKE

STOP

KICK

BRAKE

STOP

KICK

BRAKE

STOP

1-2 (a)

1-2 (b)

1-2 (c)

1-3 (a)

1-3 (b)

1-3 (c)

1-4 (a)

1-4 (b)

1-4 (c)

1-5 (a)

1-5 (b)

1-5 (c)

1-6 (a)

1-6 (b)

1-6 (c)

Timing chart

Mode

CLV-N

CLV-W

CAV-W

LPWR

1-7

1-8

1-9

1-10 (EPWM = 0)

1-11 (EPWM = 0)

1-12 (EPWM = 1)

1-13 (EPWM = 1)

Timing chart

CXD2588Q/R

Timing Chart 1-2

CLV-N mode LPWR = 0

KICK

MDP

(a) KICK

BRAKE

MDP

(b) BRAKE

STOP

MDP

Timing Chart 1-3

CLV-W mode (when following the spindle rotational velocity) LPWR = 0

KICK

MDP

(a) KICK

BRAKE

MDP

(b) BRAKE

STOP

MDP

Timing Chart 1-4

CLV-W mode (when following the spindle rotational velocity) LPWR = 1

KICK

MDP

(a) KICK

BRAKE

MDP

(b) BRAKE

STOP

MDP

Timing Chart 1-5

CAV-W mode LPWR = 0

KICK

MDP

(a) KICK

BRAKE

MDP

(b) BRAKE

STOP

MDP

Timing Chart 1-6

CAV-W mode LPWR = 1

KICK

MDP

(a) KICK

BRAKE

MDP

(b) BRAKE

STOP

MDP

CXD2588Q/R

Timing Chart 1-10

CAV-W mode EPWM = LPWR = 0

MDP

Acceleration

Deceleration

264kHz

3.8µs

Timing Chart 1-7

CLV-N mode LPWR = 0

MDP

Acceleration

Deceleration

132kHz

7.6µs

n · 236 (ns) n = 0 to 31

Timing Chart 1-8

CLV-W mode LPWR = 0

MDP

Acceleration

Deceleration

264kHz

3.8µs

Timing Chart 1-9

CLV-W mode LPWR = 1

MDP

Acceleration

264kHz

3.8µs

The BRAKE pulse is masked when LPWR = 1.

Timing Chart 1-11

CAV-W mode EPWM = LPWR = 1

MDP

Acceleration

264kHz

3.8µs

The BRAKE pulse is masked when LPWR = 1.

CXD2588Q/R

Timing Chart 1-12

CAV-W mode EPWM = 1, LPWR = 0

PWMI

MDP

Acceleration

Deceleration

Timing Chart 1-13

CAV-W mode EPWM = LPWR = 1

PWMI

MDP

Acceleration

The BRAKE pulse is masked when LPWR = 1.

CXD2588Q/R

§2. Subcode Interface

This section explains the subcode interface.

There are two methods for reading out a subcode externally.

The 8-bit subcodes P to W can be read from SBSO by inputting EXCK to the CXD2588Q/R.

Sub Q can be readout after checking the CRC of the 80 bits in the subcode frame.

Sub Q can be readout from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes

correctly and CRCF is high.

§2-1. P to W Subcode Readout

Data can be readout by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.)

§2-2. 80-bit Sub Q Readout

Fig. 2-1 shows the peripheral block of the 80-bit Sub Q register.

· First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check

circuit.

· 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are

loaded into the parallel/serial register.

When SQSO goes high 400µs (monostable multivibrator time constant) or more after subcode readout, the

CPU determines that new data (which passed the CRC check) has been loaded.

· The CRCF reset is performed by inputting SQCK. When the subcode data is discontinuous after track jump,

etc. CRCF is reset by inputting SQCK. Then, if CRCF =1, the CPU determines that the new data has been

loaded.

· When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result,

although the sequence of bytes is the same, the bits within the bytes are now ordered LSB first.

· Once the 80-bit data load is confirmed, SQCK is input so that the data can be read.

The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low.

· The retriggerable monostable multivibrator has a time constant from 270µs to 400µs. When the duration

when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this

interval, the serial/parallel register is not loaded into the parallel/serial register.

· While the monostable multivibrator is being reset, data cannot be loaded in the 80-bit parallel/serial register.

In other words, while reading out with a clock cycle shorter than this time constant, the register will not be

rewritten by CRCOK and others. (See Timing Chart 2-2.)

· The high and low intervals for SQCK should be between 750ns and 120µs.

CXD2588Q/R

Timing Chart 2-1

Internal
PLL clock
4.3218 ±

MHz

WFCK

SCOR

EXCK

SBSO

400ns max

S0 · S1

WFCK

SCOR

EXCK

SBSO

S0·S1 Q R S T U V W

S0·S1

Q R S T U V W

Same

Sub Code P.Q.R.S.T.U.V.W Read Timing

CXD2588Q/R

Fig. 2-1. Block Diagram

I
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(
A

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(
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(
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CXD2588Q/R

Timing Chart 2-2

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CXD2588Q/R

Timing Chart 2-3

Measurement interval (approximately 3.8µs)

Reference window

(132.2kHz)

Measurement pulse

(VCKI/2)

Measurement counter

VF0 to 7

Load

The relative velocity R of the disc can be expressed with the following equation.

R = (R: Relative velocity, m: Measurement results)

VF0 to 7 is the result obtained by counting VCKI/2 pulses while the reference signal (132.2kHz) generated

from the crystal (384Fs) is high. This count is 31 when the disc is rotating at normal speed and 63 when it is

rotating at double speed (when DSPB is low).

m + 1

CXD2588Q/R

§3. Description of Modes

This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations

for each mode are described below.

§3-1. CLV-N Mode

This mode is compatible with the CXD2507AQ, and operation is the same as for the conventional control. The

PLL capture range is ±150kHz.

§3-2. CLV-W Mode

This is the wide capture range mode. This mode allows the PLL to follow the rotational velocity of the disc. This

rotational following control has two types: using the built-in VCO2 or providing an external VCO. The spindle is

the same CLV servo as for the conventional series. Operation using the built-in VCO2 is described below.

(When using an external VCO, input the signal from the VPCO pin to the low-pass filter, use the output from

the low-pass filter as the control voltage for the external VCO, and input the oscillation output from the VCO to

the VCKI pin.)

When starting to rotate the disc and/or speeding up to the lock range from the condition where the disc is

stopped, CAV-W mode should be used. Specifically, first send $E6650 to set CAV-W mode and kick the disc,

then send $E60C0 to set CLV-W mode if ALOCK is high, which can be readout serially from the SQSO pin.

CLV mode can be used while ALOCK is high. The microcomputer monitors the serial data output, and must

return the operation to the speed adjusting state (CAV-W mode) when ALOCK becomes low. The control flow

according to the microcomputer software is shown in Fig. 3-2.

In CLV-W mode (normal), low power consumption is achieved by setting LPWR to high. Control was formerly

performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is set

to high, deceleration pulses are not output, thereby achieving low power consumption mode.

Note) The capture range for CLV-W mode has theoretically the range up to the signal processing limit.

§3-3. CAV-W Mode

This is CAV mode. In this mode, the external clock is fixed and it is possible to control the spindle to variable

rotational velocity. The rotational velocity is determined by the VP0 to 7 setting values or the external PWM.

When controlling the spindle with VP0 to 7, setting CAV-W mode with the $E6650 command and controlling

VP0 to 7 with the $DX commands allows the rotational velocity to be varied from low speed to double speed.

(See the $DX commands.) Also, when controlling the spindle with the external PWM, the PWMI pin is binary

input which becomes KICK during high intervals and BRAKE during low intervals.

The microcomputer can know the rotational velocity using V16M. The reference for the velocity measurement

is a signal of 132.2kHz obtained by 1/128-frequency dividing the crystal (384Fs). The velocity is obtained by

counting V16M/2 pulses while the reference is high, and the result is output from the new CPU interface as

8 bits (VF0 to 7). These measurement results are 31 when the disc is rotating at normal speed or 63 when it is

rotating at double speed. These values match those of the 256-n for control with VP0 to 7.

In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire

system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and all other

output signals from this LSI change according to the rotational velocity of the disc.

Note) The capture range for this mode is theoretically up to the signal processing limit.

CXD2588Q/R

CAV-W

CLVS

CLV-W

CLVP

Rotational velocity

Target velocity

Operation mode

Spindle mode

Time

KICK

LOCK

ALOCK

Fig. 3-1. Disc Stop to Normal Condition in CLV-W Mode

CLV-W Mode

YES

KICK $E8000
Mute OFF $A0XXXXX

ALOCK = H ?

YES

ALOCK = L ?

CLV-W MODE

START

CAV-W $E6650

(CLVA)

CLV-W $E60C0

(CLVA)

(WFCK PLL)

Fig. 3-2. CLV-W Mode Flow Chart

CXD2588Q/R

§4. Description of Other Functions

§4-1. Channel Clock Regeneration by the Digital PLL Circuit

· The channel clock is necessary for demodulating the EFM signal regenerated by the optical system.

Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to

11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result,

T, that is the channel clock, is necessary.

In an actual player, the PLL is necessary to regenerate the channel clock because the fluctuation in the

spindle rotation alters the width of the EFM signal pulses.

The block diagram of this PLL is shown in Fig. 4-1.

The CXD2588Q/R has a built-in three-stage PLL.

· The first-stage PLL is for the wide-band PLL. When the internal VCO2 is used, an external LPF is necessary;

when not using the internal VCO2, external LPF and VCO are required.

The output of this first-stage PLL is used as a reference for all clocks within the LSI.

· The second-stage PLL generates the high-frequency clock needed by the third-stage digital PLL.

· The third-stage PLL is a digital PLL that regenerates the actual channel clock.

· A new digital PLL has been provided for CLV-W mode to follow the rotational velocity of the disc in addition

to the conventional secondary loop.

CXD2588Q/R

Block Diagram 4-1

X'tal

XTSL

OSC

1/2

1/32

1/n

1/2

Microcomputer

control

n = 1 to 256

(VP7 to 0)

1/K

(KSL1, 0)

CLV-W
CAV-W

Spindle rotation information

CLV-N

CLV-W
CAV-W

/CLV-N

r
a

t
o

l
e

t
o

LPF

2/1 MUX

VPON

1/M

1/N

VCOSEL2

VCO2

r
a

t
o

VCO1

VCOSEL1

1/K

(KSL3, 2)

Digital PLL

RFPLL

VPCO

VCTL

V16M

VCKI

PCO

FILI

FILO

CLTV

CXD2588Q/R

CXD2588Q/R

§4-2. Frame Sync Protection

· In normal-speed playback, a frame sync is recorded approximately every 136µs (7.35kHz). This signal is

used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be

recognized, the data is processed as error data because the data cannot be recognized. As a result,

recognizing the frame sync properly is extremely important for improving playability.

· In the CXD2588Q/R, window protection and forward protection/backward protection have been adopted for

frame sync protection. These functions achieve very powerful frame sync protection. There are two window

widths: one for cases where a rotational disturbance affects the player and the other for cases where there is

no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the

backward protection counter to 3. Concretely, when the frame sync is being played back normally and then

cannot be detected due to scratches etc., a maximum of 13 frames are inserted. If the frame sync cannot be

detected for 13 frames or more, the window opens to resynchronize the frame sync.

In addition, immediately after the window opens and the resynchronization is executed, if a proper frame

sync cannot be detected within 3 frames, the window opens immediately.

§4-3. Error Correction

· In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code

is created with 28-byte information and 4-byte C1 parity.

For C2 correction, the code is created with 24-byte information and 4-byte parity.

Both C1 and C2 are Reed-Solomon codes with a minimum distance of 5.

· The CXD2588Q/R's SEC strategy uses powerful frame sync protection and C1 and C2 error correction to

achieve high playability.

· The correction status can be monitored externally.

See Table 4-2.

· When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an

average value interpolation was made for the data.

MNT3

MNT1

MNT0

Description

No C1 errors

One C1 error corrected

C1 correction impossible

No C2 errors

One C2 error corrected

C2 correction impossible

Table 4-2.

CXD2588Q/R

Timing Chart 4-3

Normal-speed PB

MNT3

MNT1

MNT0

t = Dependent on error
condition

C1 correction

C2 correction

Strobe

§4-4. DA Interface

· The CXD2588Q/R DA interface is as described below.

This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is

high, the data is for the left channel.

CXD2588Q/R

Timing Chart 4-4

(
4

.
1

)

(
2

.
1

)

(
8

.
2

)

(
4

.
2

)

-
b

i
t

s

l
o

t

N

r
m

l
-
S

l
a

(
1

)

(
1

)

-
b

i
t

s

l
o

t

D

l
e

-
S

l
a

CXD2588Q/R

§4-5. Digital Out

There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use,

and the type 2 form 2 format for the manufacture of software.

The CXD2588Q/R supports type 2 form 1.

Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bits 0 to 3)

of the channel status.

Table 4-5.

§4-6. Servo Auto Sequence

This function performs a series of controls, including auto focus and track jumps. When the auto sequence

command is received from the CPU, auto focus, 1-track jump, 2N-track jump and N-track move are executed

automatically.

The commands which enable transfer to the CXD2588Q/R during the execution of auto sequence are $4X to

$EX.

When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of

100µs after that point.

0/1

ID0

ID1 COPY Emph

From sub Q

176

Bits 0 to 3 Sub Q control bits that matched twice with CRCOK
Bit 29

1 when VPON = 1

Digital Out C bit

CXD2588Q/R

(a) Auto focus ($47)

Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on.

If $47 is received from the CPU, the focus servo is turned on according to Fig. 4-3. The auto focus starts with

focus search-up, and note that the pickup should be lowered beforehand (focus search down). In addition,

blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling

edge of FZC after FZC has been continuously high for a longer time than E.

Fig. 4-6-(a). Auto Focus Flow Chart

Auto focus

Focus search up

FOK=H

YES

FZC = H

YES

FZC = L

YES

END

Focus servo ON

(Check whether FZC is continuously high
for the period of time E set with register 5.)

CXD2588Q/R

Fig. 4-6-(b). Auto Focus Timing Chart

(b) Track jump

1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled

servos are on. Note that tracking gain-up and braking-on should be sent beforehand because they are not

involved in this sequence.

· 1-track jump

When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance

with Fig. 4-7. Set blind A and brake B with register 5.

· 10-track jump

When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in accordance

with Fig. 4-8. The principal difference from the 1-track jump is to kick the sled. In addition, after kicking the

actuator, when 5 tracks have been counted through COUT, the brake is applied to the actuator. Then, when

the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than

the overflow C set with register 5), the tracking and sled servos are turned on.

· 2N-track jump

When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance

with Fig. 4-9. The track jump count N is set with register 7. Although N can be set to 2

tracks, note that the

setting is actually limited by the actuator. COUT is used for counting the number of jumps.

Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is

that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6.

· N-track move

When $4E ($4F for REV) is received from the CPU, a FWD (REV) N-track move is performed in accordance

with Fig. 4-10. N can be set to 2

tracks. COUT is used for counting the number of jumps. The N-track move

is executed only by moving the sled, and is therefore suited for moving across several thousand to several

ten-thousand tracks.

XLAT

FOK

(FZC)

BUSY

Command for

DSSP

$47latch

$03

Blind E

$08

CXD2588Q/R

Fig. 4-7-(a). 1-Track Jump Flow Chart

Track

YES

END

Track FWD kick

sled servo OFF

WAIT

(Blind A)

COUT =

Track REV

kick

WAIT

(Brake B)

Track, sled

servo ON

(FWD kick for
REV jump)

(REV kick for
REV jump)

Fig. 4-7-(b). 1-Track Jump Timing Chart

XLAT

COUT

BUSY

Command for

DSSP

$48 (REV = $49) latch

$28 ($2C)

Blind A

Brake B

$2C ($28)

$25

CXD2588Q/R

Fig. 4-8-(a). 10-Track Jump Flow Chart

10 Track

YES

END

Track, sled

FWD kick

WAIT

(Blind A)

COUT = 5 ?

Track, REV

kick

Track sled

servo ON

(Check whether the COUT cycle
is longer than overflow C.)

(Counts COUT

YES

C = Overflow ?

Fig. 4-8-(b). 10-Track Jump Timing Chart

XLAT

COUT

BUSY

Command for

DSSP

$4A (REV = $4B) latch

Blind A

$2A ($2F)

COUT 5 count

$2E ($2B)

Overflow C

$25

CXD2588Q/R

Fig. 4-9-(a). 2N-Track Jump Flow Chart

2N Track

YES

END

Track, sled

FWD kick

WAIT

(Blind A)

COUT = N

Track REV

kick

Track servo

YES

C = Overflow

WAIT

(Kick D)

Sled servo

Fig. 4-9-(b). 2N-Track Jump Timing Chart

XLAT

BUSY

Command for

DSSP

Blind A

$2A ($2F)

COUT N count

$2E ($2B)

Overflow C

Kick D

$26 ($27)

$25

$4C (REV = $4D) latch

COUT

CXD2588Q/R

Fig. 4-10-(a). N-Track Move Flow Chart

N Track move

YES

END

Track servo OFF

Sled FWD kick

WAIT

(Blind A)

COUT = N

END

Track, sled

servo OFF

Fig. 4-10-(b). N-Track Move Timing Chart

XLAT

BUSY

Command for

DSSP

$22 ($23)

Blind A

COUT N count

$20

$4E (REV = $4F) latch

COUT

CXD2588Q/R

§4-7. Digital CLV

Fig. 4-11 shows the block diagram. Digital CLV outputs MDS error and MDP error with PWM, with the

sampling frequency increased up to 130Hz during normal-speed playback in CLVS, CLVP and other modes.

In addition, the digital spindle servo gain is variable.

MDP

Digital CLV

CLVS U/D

MDS Error

MDP Error

CLV P/S

Measure

2/1 MUX

Oversampling

Filter-1

Gain
MDS

1/2

MUX

CLV P/S

Oversampling

Filter-2

Noise Shape

Modulation

KICK, BRAKE, STOP

MDS

Mode Select

Gain
MDP

DCLVMD, LPWR

PWMI

Fig. 4-11. Block Diagram

CLVS U/D : Up/down signal from CLVS servo
MDS error : Frequency error for CLVP servo
MDP error : Phase error for CLVP servo
PWMI

: Spindle drive signal from the microcomputer

CXD2588Q/R

§4-8. CD-DSP Block Playback Speed

In the CXD2588Q/R, the following playback modes can be selected through different combinations of the

crystal, XTSL pin and the DSPB command of $9X.

CD-DSP block playback speed

Crystal

768Fs

384Fs

XTSL

DSPB

CD-DSP block playback speed

Fs = 44.1kHz.

In 4

speed playback, the timer value for the auto sequence is halved.

Low power consumption mode. The CD-DSP processing speed is halved, allowing power consumption

to be reduced.

§4-9. DAC Block Playback Speed

The operation speed for the DAC block is determined by the crystal and the MCSL command of $9X

regardless of the CD-DSP operating conditions noted above. This allows the playback modes for the DAC and

CD-DSP blocks to be set independently.

1-bit DAC block playback speed

Crystal

768Fs

384Fs

MCSL

DAC block playback speed

Fs = 44.1kHz.

CXD2588Q/R

§4-10. DAC Block Input Timing

Timing Chart 4-12 shows the DAC block input timing chart.

In the CXD2588Q/R, the data can be transferred from the CD signal processor block to the DAC block via the

outside of the LSI. This allows the data to be sent to the DAC block via the audio DSP, etc.

As for the data input to the DAC block without using the audio DSP, there are two methods: one is to connect

directly EMPH, LRCK, BCK and PCMD with EMPHI, LRCKI, BCKI and PCMDI outside the LSI; and the other

is to set OUTL0 of $8X to 1. Note that the outputs of EMPH, LRCK, BCK and PCMD become low when OUTL0

of $8X is set to 0 .

§4-11. Description of DAC Block Functions

Zero data detection

When the condition where the lower 4 bits of the input data are DC and the remaining upper bits are all "0" or

all "1" has continued about for 300ms, zero data is detected. Zero data detection is performed independently

for the left and right channels.

Mute flag output

The LMUT and RMUT pins go active when any one of the following conditions is met.

The polarity can be selected with the ZDPL command of $9X.

· When zero data is detected

· When a high signal is input to the SYSM pin

· When the SMUT command of $AX is set

Attenuation operation

Assuming attenuation data X1, X2 and X3 (X1 > X3 > X2), the corresponding audio outputs are Y1, Y2 and Y3

(Y1 > Y3 > Y2). First, X1 is sent, followed by X2. If X2 is sent before X1 reaches Y1 (A in the figure), X1

continues approaching Y2. Next, if X3 is sent before X1 reaches Y2 (B or C in the figure), X1 then approaches

Y3 from the value (B or C in the figure) at that point.

23.2 [ms]

00 (H)

0dB

7F (H)

CXD2588Q/R

DAC block mute operation

Soft mute

Soft mute results and the input data is attenuated to zero when any one of the following conditions is met.

· When attenuation data of "000" (high) is set

· When the SMUT command of $AX is set to 1

· When a high signal is input to the SYSM input pin

Forced mute

Forced mute results when the FMUT command of $AX is set to 1.

Forced mute fixes the PWM output that is input to the LPF block to low.

When setting FMUT, set OPSL2 to 1. (See the $AX commands.)

Zero detection mute

Forced mute is applied when the ZMUT command of $9X is set to 1 and the zero data is detected for the

left and right channels.

(See "Zero data detection".)

When the ZMUT command of $9X is set to 1, the forced mute is applied even if the mute flag output

condition is met. When the zero detection mute is on, set the DCOF command of $9X to 1.

Soft mute on

Soft mute off

23.2 [ms]

0dB

CXD2588Q/R

Input Timing DAC Block

r
m

l
-
S

l
a

(
4

.
1

)

(
2

.
1

)

(
1

)

(
8

.
2

)

(
4

.
2

)

l
e

-
S

l
a

(
1

)

Timing Chart 4-12

CXD2588Q/R

Normal

DBB MID

DBB MAX

10.00

4.00

6.00

4.00

2.00

0.00

2.00

8.00

6.00

8.00

10.00

12.00

14.00

100

300

10k

30k

Digital Bass Boost Frequency Response [Hz]

[
d

]

Graph 4-13.

LRCK Synchronization
Synchronization is performed at the first falling edge of the LRCK input during reset.
After that, synchronization is lost when the LRCK input frequency changes and resynchronization must be
performed.
The LRCK input frequency changes when the master clock of the LSI is switched and the playback speed
changes such as the following cases.

· When the XTSL pin switches between high and low
· When the DSPB command of $9X setting changes
· When the MCSL command of $9X setting changes

LRCK switching may also be performed if there are other ICs between the CD-DSP block and the DAC
block. Resynchronization must be performed in this case as well.
For resynchronization, set the LRWO command of $AX to 1, wait for one LRCK cycle or more, and then set
LRWO to 0.

When setting LRWO, set OPSL2 to 1. (See the $AX commands.)

SYCOF
When LRCK, PCMD and BCK are connected directly with LRCKI, PCMDI and BCKI, respectively, playback
can be performed easily in CAV-W mode by setting SYCOF of address 9 to 1.
Normally, the memory proof, etc. is used for playback in CAV-W mode.
In CAV-W mode, the LRCK output conforms not to the crystal but to the VCO. Therefore, synchronization is
frequently lost.
Setting SYCOF of address 9 to 1 ignores that the LRCKI input synchronization is lost, facilitating playback.
However, the playback is not perfect because pre-value hold or data skip occurs due to the wow flutter in the
LRCKI input.

Set SYCOF to 0 except when connecting LRCK, PCMD and BCK directly with LRCKI, PCMDI and BCKI,
respectively, and performing playback in CAV-W mode.

Digital Bass Boost
Bass boost without external parts is possible using the built-in digital filter. The boost strength has two levels:
Mid. and Max. BSBST and BBSL of address A are used for the setting.
See Graph 4-13 for the digital bass boost frequency response.

CXD2588Q/R

Analog out

680p

12k

150p

AOUT1 (2)

AIN1 (2)

LOUT1 (2)

Fig. 4-14. LPF External Circuit

§4-12. LPF Block

The CXD2588Q/R contains an initial-stage secondary active LPF with numerous resistors and capacitors and

an operational amplifier with reference voltage.

The resistors and capacitors are attached externally, allowing the cut-off frequency fc to be determined flexibly.

The reference voltage (V

) is (AV

)

0.43.

The LPF block application circuit is shown below.

In this circuit, the cut-off frequency is fc

40kHz.

The external capacitors' values when fc = 30kHz and 50kHz are noted below as a reference.

The resistors' values do not change at this time.

· When fc

30kHz:

C1 = 200pF, C2 = 910pF

· When fc

50kHz:

C1 = 120pF, C2 = 560pF

LPF Block Application Circuit

CXD2588Q/R

§4-13. Asymmetry Compensation

Fig. 4-15 shows the block diagram and circuit example.

RFAC

ASYO

ASYI

R1 2
R2 5

BIAS

CXD2588Q/R

Fig. 4-15. Asymmetry Compensation Application Circuit

CXD2588Q/R

§4-14. CD TEXT Data Demodulation

· In order to demodulate the CD TEXT data, set the command $8 Data 6 D3 TXON to 1. During TXON = 1,

connect EXCK to low and do not use the data output from SBSO because the CD TEXT demodulation circuit

uses EXCK and the SBSO pin exclusively.

It requires 26.7ms (max.) to demodulate the CD TEXT data correctly after TXON is set to 1.

· The CD TEXT data is output by switching the SQSO pin with the command. The CD TEXT data output is

enabled by setting the command $8 Data 6 D2 TXOUT to 1. To read data, the readout clock should be input

to SQCK.

· The readable data are the CRC counting results for the each pack and the CD TEXT data (16 bytes) except

for CRC data.

· When the CD TEXT data is read, the order of the MSB and LSB is inverted within each byte. As a result,

although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.

· Data which can be stored in the LSI is 1 packet (4 packs).

Fig. 4-16. Block Diagram of CD TEXT Demodulation Circuit

SQCK

SQSO

TXOUT

Subcode

Decoder

CD TEXT

Decoder

TXON

SBSO

EXCK

CXD2588Q/R

t
a

I
D

(
P

)

I
D

(
P

)

I
D

(
P

)

t
e

i
t

t
a

(
c

)

(
c

)

l
o

Fig. 4-17. CD TEXT Data Timing Chart

CXD2588Q/R

§5. Description of Servo Signal Processing System Functions and Commands

§5-1. General Description of Servo Signal Processing System (V

: Supply voltage)

Focus servo

Sampling rate:

88.2kHz (when MCK = 128Fs)

Input range:

0.3V

to 0.7V

Output format:

7-bit PWM

Others:

Offset cancel

Focus bias adjustment

Focus search

Gain-down function

Defect countermeasure

Auto gain control

Tracking servo

Sampling rate:

88.2kHz

Input range:

0.3V

to 0.7V

Output format:

7-bit PWM

Others:

Offset cancel

E:F balance adjustment

Track jump

Gain-up function

Defect countermeasure

Drive cancel

Auto gain control

Vibration countermeasure

Sled servo

Sampling rate:

345Hz (MCK = 128Fs)

Input range:

0.3V

to 0.7V

Output format:

7-bit PWM

Others:

Sled move

FOK, MIRR, DFCT signals generation

RF signal sampling rate:

1.4MHz (MCK = 128Fs)

Input range:

0.43V

to V

Others:

RF zero level automatic measurement

CXD2588Q/R

§5-2. Digital Servo Block Master Clock (MCK)

The internal master clock (MCK) is generated by dividing the frequency of the signal input to FSTI. The

frequency division ratio is 1, 1/2 or 1/4.

Table 5-1 below shows the hypothetical case where the crystal clock generated from the digital signal

processor block is 2/3 frequency-divided and input to the FSTI pin by externally connecting the FSTI pin and

the FSTO pin. By setting $8X command D1 OUTL1 to 1, FSTI and FSTO can be internally connected. (See

$8X commands.)

The XT4D and XT2D command settings can be made with D13 and D12 of $3F, and XT1D with D1 of $3E.

(Default = 0)

The digital servo block is designed with an MCK frequency of 5.6448MHz.

Fs = 44.1kHz,

: Don't care

Table 5-1.

§5-3. AVRG (Average) Measurement and Compensation

The CXD2588Q/R has a circuit that measures the average of RFDC, VC, FE, and TE and a circuit that

compensates them to control servo effectively.

AVRG measurement and compensation is necessary to initialize the CXD2588Q/R, and is able to cancel the

offset.

The level applied to the VC, FE, RFDC and TE pins can be measured by setting D15 (VLCM), D13 (FLM), D11

(RFLM) and D4 (TCLM) of $38 respectively to 1.

AVRG measurement consists of digitally measuring the level applied to each analog input pin by taking the

average of 256 samples, and then loading these values into the AVRG register.

AVRG measurement requires approximately 2.9ms to 5.8ms after the command is received.

During AVRG measurement, if the upper 8 bits of the command register are 38 (Hex), the completion of AVRG

measurement operation can be confirmed through the SENS pin. (See Timing Chart 5-2.)

XLAT

SENS
(= XAVEBSY)

Max. 1µs

Completion of AVRG measurement

2.9 to 5.8ms

Timing Chart 5-2.

Mode

384Fs

768Fs

256Fs

512Fs

1/2

1/4

256Fs

128Fs

512Fs

256Fs

128Fs

Crystal

FSTO (FSTI)

XTSL XT4D XT2D XT1D

Frequency division ratio

MCK

CXD2588Q/R

<Measurement>

· VC AVRG

The offset can be canceled by measuring the VC level which is the center voltage for the system and using

that value to apply compensation to each input error signal.

· FE AVRG

The FE signal DC level is measured. In addition, compensation is applied to the FZC comparator level output

from the SENS pin during FCS SEARCH (focus search) using these measurement results.

· TE AVRG

The TE signal DC level is measured.

· RF AVRG

The MIRR, DFCT and FOK signals are generated from the RF signal. Since the FOK signal is generated by

comparing the RF signal at a certain level, it is necessary to establish a zero level which becomes the

comparator level reference. Therefore, the RF signal is measured before playback, and is compensated to

take this level as the zero level.

An example of sending AVRG measurement and compensation commands is shown below.

(Example)

$380800 (RF AVRG measurement on)

$382000 (FE AVRG measurement on)

$380010 (TE AVRG measurement on)

$388000 (VC AVRG measurement on)

(Complete each AVRG measurement before starting the next.)

$38140A (RFLC, FLC0, FLC1 and TLC1 commands on)

(The required compensation should be turned on together; see Fig. 5-3.)

An interval of 5.8ms (when MCK = 128Fs) or more must be maintained between each command, or the SENS

pin must be monitored to confirm that the previous command has been completed before the next AVRG

command is sent.

<Compensation>

See Fig. 5-3 for the contents of each compensation below.

· RFLC

The difference by which the RF signal exceeds the RF AVRG value is input to the RF In register.

(00 is input when the RF signal is lower than the RF AVRG value.)

· TCL0

The value obtained by subtracting the VC AVRG value from the TE signal is input to the TRK In register.

· TCL1

The value obtained by subtracting the TE AVRG value from the TE signal is input to the TRK In register.

· VCLC

The value obtained by subtracting the VC AVRG value from the FE signal is input to the FCS In register.

· FLC1

The value obtained by subtracting the FE AVRG value from the FE signal is input to the FCS In register.

· FLC0

The value obtained by subtracting the FE AVRG value from the FE signal is input to the FZC register.

CXD2588Q/R

§5-4. E:F Balance Adjustment Function

When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search),

the traverse waveform appears in the TE signal due to disc eccentricity.

In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold

filter by setting D5 (TBLM) of $38 to 1.

The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC

Next, setting D2 (TLC2) of $38 to 1 compensates TE and SE values with the TRVSC register value

(subtraction), resulting the E:F balance offset to be adjusted. (See Fig. 5-3.)

§5-5. FCS Bias (Focus Bias) Adjustment Function

The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See

Fig. 5-3.)

When the FBIAS register value is set when D11 = 0 and D10 = 1 with $34F, data can be written using the 9-bit

value of D9 to D1 (D9: MSB).

In addition, the RF jitter can be monitored by setting the SOCT command of $8 to 1. (See "DSP Block Timing

Chart".)

The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to 1. The FBIAS register functions

as an up counter when D12 (FBUP) of $3A = 1, and as a down counter when D12 (FBUP) of $3A = 0.

The number of up and down steps can be changed by setting D11 and D10 (FBV1 and FBV0) of $3A.

When using the FBIAS register as a counter, the counter stops if the FBIAS value and the value set

beforehand in FBL9 to 1 of $34 matches. Also, if the upper 8 bits of the command register are $3A at this time,

SENS becomes high and the counter stop can be monitored.

FBIAS setting value (FB9 to 1)

LIMIT value (FBL9 to 1)

SENS pin

A: Register mode
B: Counter mode
C: Counter mode (when stopped)

Here, assume the FBIAS setting value FB9 to 1

and the FBIAS LIMIT value FBL9 to 1 like status

A. For example, if command registers FBUP = 0,

FBV1 = 0, FBV0 = 0 and FBSS = 1 are set from

this status, down count starts from status A and

approaches the set LIMIT value. When the

FBIAS value matches FBL9 to 1, the counter

stops and the SENS pin goes to high. Note that

the up/down counter counts at each sampling

cycle of the focus servo filter. The number of

steps by which the count value changes can be

selected from 1, 2, 4 or 8 steps by FBV1 and

FBV0. When converted to FE input, 1 step

corresponds to 1/512

0.4.

CXD2588Q/R

r
e

i
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t
e

r
e

i
s

t
e

t
o

I
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e

i
s

t
e

r
e

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s

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e

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o

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e

I
A

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e

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s

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o

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n

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e

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e

t
o

r
e

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s

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o

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o

I
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r
e

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s

t
e

f
r
o

/
D

r
e

i
s

t
e

t
o

I
n

r
e

i
s

t
e

f
r
o

/
D

·

T

Fig. 5-3.

CXD2588Q/R

§5-6. AGCNTL (Automatic Gain Control) Function

The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate gain with

the servo loop. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but

also obtains the optimal gain for each disc.

The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of

the command register are 38 (Hex), the completion of AGCNTL operation can be confirmed through the SENS

pin. (See Timing Chart 5-4 and "Description of SENS Signals".)

Setting D9 and D8 of $38 to 1 set FCS (focus) and TRK (tracking) respectively to AGCNTL operation.

Note) During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described

hereafter) must be disabled.

XLAT

SENS
(= AGOK)

Max. 11.4µs

AGCNTL completion

Timing Chart 5-4.

Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 change for AGT (tracking

AGCNTL) due to AGCNTL.

These coefficients change from 01 to 7F (Hex), and they must also be set within this range when written

externally.

After AGCNTL operation has completed, these coefficient values can be confirmed by reading them out from

the SENS pin with the serial readout function (described hereafter).

AGCNTL related settings

The following settings can be changed with $35, $36 and $37.

FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (Hex)

TG6 to TG0; AGT convergence gain setting, effective setting range: 00 to 57 (Hex)

AGS;

Self-stop on/off

AGJ;

Convergence completion judgment time

AGGF;

Internally generated sine wave amplitude (AGF)

AGGT;

Internally generated sine wave amplitude (AGT)

AGV1;

AGCNTL sensitivity 1 (during rough adjustment)

AGV2;

AGCNTL sensitivity 2 (during fine adjustment)

AGHS;

Rough adjustment on/off

AGHT;

Fine adjustment time

Note) Converging servo loop gain values can be changed with the FG6 to 0 and TG6 to 0 setting values. In

addition, these setting values must be within the effective setting range. The default settings aim for 0

dB at 1kHz. However, since convergence values vary according to the characteristics of each

constituent element of the servo loop, FG and TG values should be set as necessary.

CXD2588Q/R

AGCNTL and default operation have two stages.

In the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select

256/128ms with AGHT, when MCK = 128Fs), and the AGCNTL coefficient approaches the appropriate value.

The sensitivity at this time can be selected from two types with AGV1.

In the second stage, the AGCNTL coefficient is finely adjusted to approach more appropriate value with

relatively low sensitivity. The sensitivity for the second stage can be selected from two types with AGV2. In the

second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops

changing, the CXD2588Q/R confirms that the AGCNTL coefficient has not changed for a certain period of time

(select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self-stop mode)

This self-stop mode can be canceled by setting AGS to 0.

In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0.

An example of AGCNTL coefficient transitions during AGCNTL in various settings are shown in Fig. 5-5.

Initial value

SENS

AGCNTL
Start

AGCNTL
completion

Convergence value

AGCNTL
coefficient value

Slope AGV1

AGHT

AGJ

Slope AGV2

Fig. 5-5.

Note) Fig. 5-5 shows the example where the AGCNTL coefficient value converges to the smaller value from

the initial value.

CXD2588Q/R

§5-7. FCS Servo and FCS Search (Focus Search)

The FCS servo is controlled by the 8-bit serial command $0X. (See Table 5-6.)

D23 to D20

D19 to D16

1 0

1 1

1 0

1 1

FOCUS SERVO ON (FOCUS GAIN NORMAL)

FOCUS SERVO ON (FOCUS GAIN DOWN)

FOCUS SERVO OFF, 0V OUT

FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT

FOCUS SEARCH VOLTAGE DOWN

FOCUS SEARCH VOLTAGE UP

0 0 0 0

FOCUS
CONTROL

Table 5-6.

FCS Search

FCS search is required in the course of turning on the FCS servo.

Fig. 5-7 shows the signals for sending commands $00

$02

$03 and performing only FCS search operation.

Fig. 5-8 shows the signals for sending $08 (FCS on) after that.

FCSDRV

FOK

FZC

FZC comparator level

$00 $02

$03

FCSDRV

FOK

FZC

$00 $02

$03

$08

Fig. 5-7.

Fig. 5-8.

: Don't care

CXD2588Q/R

§5-8. TRK (Tracking) and SLD (Sled) Servo Control

The TRK and SLD servos are controlled by the 8-bit command $2X. (See Table 5-9.)

When the upper 4 bits of the serial data are 2 (Hex), TZC is output to the SENS pin.

D23 to D20

D19 to D16

0 0

0 1

1 0

1 1

0 0

0 1

1 0

1 1

TRACKING SERVO OFF

TRACKING SERVO ON

FORWARD TRACK JUMP

REVERSE TRACK JUMP

SLED SERVO OFF

SLED SERVO ON

FORWARD SLED MOVE

REVERSE SLED MOVE

0 0 1 0

TRACKING
MODE

Table 5-9.

TRK Servo

The TRK JUMP (track jump) level can be set with 6 bits (D13 to D8) of $36.

In addition, when the TRK servo is on and D17 of $1 is set to 1, the TRK servo filter switches to gain-up mode.

The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected with the

anti-shock circuit (described hereafter) enabled.

CXD2588Q/R has 2 types of filters in TRK gain-up mode which can be selected by setting D16 of $1. (See

Table 5-17.)

SLD Servo

The SLD MOV (sled move) output, composed of a basic value from 6 bits (D13 to D8) of $37, is determined by

multiplying this value by 1

, 2

, 3

or 4

magnification set using D17 and D16 when D18 = D19 = 0 is set with

$3. (See Table 5-10.)

SLD MOV must be performed continuously for 50µs or more. In addition, if the LOCK input signal goes low

when the SLD servo is on, the SLD servo turns off.

Note) When the LOCK signal is low, the TRK servo switches to gain-up mode and the SLD servo is turned off

by the default. These operations are disabled by setting D6 (LKSW) of $38 to 1.

D23 to D20

D19 to D16

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

SLED KICK LEVEL (basic value

±1)

SLED KICK LEVEL (basic value

±2)

SLED KICK LEVEL (basic value

±3)

SLED KICK LEVEL (basic value

±4)

0 0 1 1

SELECT

Table 5-10.

: Don't care

CXD2588Q/R

§5-9. MIRR and DFCT Signal Generation
The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz (when MCK = 128Fs) and
loaded. The MIRR and DFCT signals are generated from this RF signal.

MIRR Signal Generation
The loaded RF signal is applied to peak hold and bottom hold circuits.
An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is
generated from the average of this envelope waveform.
The MIRR signal is generated by comparing the waveform generated by subtracting the bottom hold value
from the peak hold value with this MIRR comparator level. (See Fig. 5-11.)
The bottom hold speed and mirror sensitivity can be selected from 4 values using D7 and 6, and D5 and 4,
respectively, of $3C.

Peak Hold

Bottom Hold

Peak Hold
Bottom Hold

MIRR

MIRR Comp
(Mirror comparator level)

Peak Hold1

Peak Hold2

Peak Hold1

DFCT

(Defect comparator level)

SDF

Fig. 5-11.

DFCT Signal Generation
The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is
generated by comparing the difference between these two peak hold waveforms with the DFCT comparator
level. (See Fig. 5-12.)
The DFCT comparator level can be selected from four values using D13 and D12 of $3B.

Fig. 5-12.

CXD2588Q/R

§5-10. DFCT Countermeasure Circuit

The DFCT countermeasure circuit maintains the directionality of the servo so that the servo does not become

easily dislocated due to scratches or defects on discs.

Specifically, these operations are achieved by detecting scratch and defect with the DFCT signal generation

circuit, and when DFCT goes high, applying the low-frequency component of the error signal before DFCT

went high to the FCS and TRK servo filter inputs. (See Fig. 5-13.)

In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of $38

to 1.

Input register

Hold register

Hold Filter

Servo Filter

Error signal

DFCT

Fig. 5-13.

§5-11. Anti-Shock Circuit

When vibrations occurs in the CD player, this circuit forces the TRK filter to switch to gain-up mode so that the

servo does not become easily dislocated. This circuit is for systems which require vibration countermeasures.

Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is

increased. (See Fig. 5-14.)

The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator

level is practically variable by adjusting the value of the anti-shock filter output coefficient K35.

This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See

Table 5-17.)

This circuit can also support an external vibration detection circuit, and can set the TRK servo filter to gain-up

mode by inputting high level to the ATSK pin.

When the upper 4 bits of the command register are 1 (Hex), vibration detection can be monitored from the

SENS pin. It also can be monitored from the ATSK pin by setting the ASOT command of $3F.

Anti Shock

Filter

TRK Gain Up

Filter

TRK Gain Normal

Filter

TRK

PWM Gen

ATSK

SENS

Comparator

Fig. 5-14.

CXD2588Q/R

§5-12. Brake Circuit

Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to

turn on.

The brake circuit prevents these phenomenon.

The brake circuit is to use tracking drive as a brake by cutting unnecessary portions of it utilizing the 180°

offset in the RF envelope and tracking error phase relationship which occurs when the actuator traverses the

track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 5-15 and 5-16.)

Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by

loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal.

The brake circuit can be turned on and off by D18 of $1. (See Fig. 5-17.)

TRK
DRV

FWD

JMP

REV
JMP

Servo ON

RF
Trace

MIRR

TZC
Edge

TRKCNCL

TRK
DRV

SENS
TZC out

Inner track Outer track

TRK
DRV

REV
JMP

FWD

JMP

Servo ON

RF
Trace

MIRR

TZC
Edge

TRKCNCL

TRK
DRV

SENS
TZC out

Outer track Inner track

Fig. 5-15.

Fig. 5-16.

D23 to D20

D19 to D16

1 0

ANTI SHOCK ON

ANTI SHOCK OFF

BRAKE ON

BRAKE OFF

TRACKING GAIN NORMAL

TRACKING GAIN UP

TRACKING GAIN UP FILTER SELECT 1

TRACKING GAIN UP FILTER SELECT 2

0 0 0 1

TRACKING
CONTROL

Fig. 5-17.

: Don't care

CXD2588Q/R

§5-13. COUT Signal
The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by
loading the MIRR signal at both edges of the TZC signal. And the used TZC signal can be selected among
three different phases for each COUT signal application.

· HPTZC: For 1-track jumps

Fast phase COUT signal generation with a fast phase TZC signal. (The TZC phase is advanced by a
cut-off 1kHz digital HPF; when MCK = 128Fs.)

· STZC: For COUT signal generation when MIRR is externally input and for applications other than

COUT generation.
This is generated from sampling TE at 700kHz. (when MCK = 128Fs)

· DTZC: For high-speed traverse

Reliable COUT signal generation with a delayed phase STZC signal.

Since it takes some time to generate the MIRR signal, it is necessary to delay the TZC signal in accordance
with the MIRR signal delay during high-speed traverse.
The COUT signal output method is switched with D15 and 14 of $3C.

When D15 = 1

: STZC

When D15 = 0 and D14 = 0 : HPTZC
When D15 = 0 and D14 = 1 : DTZC

When the DTZC is selected, the delay can be selected from two values with D14 of $36.

§5-14. Serial Readout Circuit
The following measurement and adjustment results can be readout from the SENS pin by inputting the readout
clock to the SCLK pin by $39. (See Fig. 5-18, Table 5-19 and "Description of SENS Signals".)

Specified commands

$390C: VC AVRG measurement result
$3908: FE AVRG measurement result
$3904: TE AVRG measurement result
$391F: RF AVRG measurement result
$3953: FCS AGCNTL coefficient result
$3963: TRK AGCNTL coefficient result
$391C: TRVSC adjustment result
$391D: FBIAS register value

···

DLS

SPW

1/f

SCLK

MSB

LSB

XLAT

SCLK

Serial Readout Data
(SENS)

Item

Symbol

Min.

Typ.

Max.

Unit

SCLK frequency

SCLK pulse width

Delay time

SCLK

SPW

DLS

31.3

MHz

µs

Table 5-19.

During readout, the upper 8 bits of the command register must be 39 (Hex).

Fig. 5-18.

CXD2588Q/R

§5-15. Writing to the Coefficient RAM

The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and

transfer from the ROM to the RAM is completed approximately 40µs (when MCK = 128Fs) after the XRST pin

rises. (The coefficient RAM cannot be rewritten during this period.)

After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address

of the coefficient RAM.

The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and

D7 to D0 as data. Coefficient rewriting is completed 11.3µs (when MCK = 128Fs) after the command is

received. When rewriting multiple coefficients, be sure to wait 11.3µs (when MCK = 128Fs) before sending the

next rewrite command.

§5-16. PWM Output

FCS, TRK and SLD outputs are output as PWM waveforms.

In particular, FCS and TRK permit accurate drive by using a double oversampling noise shaper.

Timing Chart 5-20 and Fig. 5-21 show examples of output waveforms and drive circuits.

MCK

180ns

Timing Chart 5-20.

64t

MCK

64t

MCK

64t

MCK

SFDR

SRDR

SLD

32t

MCK

32t

MCK

32t

MCK

32t

MCK

32t

MCK

32t

MCK

FCS/TRK

FFDR/
TFDR

FRDR/
TRDR

Output value +A

Output value A

Output value 0

MCK

MCK
(5.6448MHz)

5.6448MHz

CXD2588Q/R

Example of Driver Circuit

RDR

FDR

22k

DRV

Fig. 5-21. Driver Circuit

CXD2588Q/R

§5-17. Servo Status Changes Produced by the LOCK Signal

When the LOCK signal becomes low, the TRK servo switches to the gain-up mode and the SLD servo turns off

in order to prevent SLD free-running.

Setting D6 (LKSW) of $38 to 1 deactivates this function.

In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low.

This enables microcomputer control.

§5-18. Description of Commands and Data Sets

The following description contains portions which convert internal voltages into the values when they are

output externally and describe them as input conversion or output conversion.

Input conversion converts these voltages into the voltages entering input pins before A/D conversion.

Output conversion converts PWM output values into analog voltage values.

CXD2588Q/R

D15

D14

D13

D12

D11

D10

KA6

KA5

KA4

KA3

KA2

KA1

KA0

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

When D15 = 0

KA6 to KA0: Coefficient address

KD7 to KD0: Coefficient data

D15

D14

D13

D12

D11

D10

FB9

FB8

FB7

FB6

FB5

FB4

FB3

FB2

FB1

When D15 = D14 = D13 = D12 = 1 ($34F)

D11 = 0, D10 = 1

FBIAS register write

FB9 to FB1: Data; FB9 is MSB two's complement data.

For FE input conversion, FB9 to FB1 = 011111111 corresponds to 255/256

/5 and

FB9 to FB1 = 100000000 to 256/256

/5 respectively. (V

: supply voltage)

D15

D14

D13

D12

D11

D10

FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1

When D15 = D14 = D13 = D12 = D11 = 1 ($34F)

D10 = 0

FBIAS LIMIT register write

FBL9 to FBL1: Data; data compared with FB9 to 1, FBL9 = MSB.

When using the FBIAS register in counter mode, counter operation stops when the

value of FB9 to 1 matches with FBL9 to 1.

D15

D14

D13

D12

D11

D10

TV9

TV8

TV7

TV6

TV5

TV4

TV3

TV2

TV1

TV0

When D15 = D14 = D13 = D12 = 1 ($34F)

D11 = 0, D10 = 0

TRVSC register write

TV9 to TV0: Data; TV9 is MSB two's complement data.

For TE input conversion, TV9 to TV0 = 0011111111 corresponds to 255/256

and TV9 to TV0 = 1100000000 to 256/256

/5 respectively. (V

: supply voltage)

Note) · When the TRVSC register is readout, the data length is 9 bits. At this time, data corresponding to

each bit TV8 to TV0 during external write are readout.

· When reading out internally measured values and then writing these values externally, set TV9 the

same as TV8.

$34

CXD2588Q/R

$35 (preset: $35 58 2D)

D15

D14

D13

D12

D11

D10

FT1

FT0

FS5

FS4

FS3

FS2

FS1

FS0

FTZ

FG6

FG5

FG4

FG3

FG2

FG1

FG0

FT1, FT0, FTZ: Focus search-up speed

Default value: 010 (0.673

V/s)

Focus drive output conversion

FT1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
0
1
1
1
1

1.35

0.673

0.449

0.336

1.79

1.08

0.897

0.769

FT0

FTZ

Focus search speed [V/s]

FS5 to FS0:

Focus search limit voltage

Default value: 011000 (±24/64

, V

: PWM driver supply voltage)

Focus drive output conversion

FG6 to FG0: AGF convergence gain setting value

Default value: 0101101

$36 (preset: $36 0E 2E)

D15

D14

D13

D12

D11

D10

TDZC DTZC TJ5

TJ4

TJ3

TJ2

TJ1

TJ0 SFJP TG6

TG5

TG4

TG3

TG2

TG1

TG0

TDZC:

Selects the TZC signal for generating the TRKCNCL signal during brake circuit operation.

TDZC = 0: the edge of the HPTZC or STZC signal, whichever has the faster phase, is used.

TDZC = 1: the edge of the HPTZC or STZC signal or the tracking drive signal zero-cross,

whichever has the faster phase, is used. (See §5-12.)

DTZC:

DTZC delay (8.5/4.25µs, when MCK = 128Fs)

Default value: 0 (4.25µs)

TJ5 to TJ0:

Track jump voltage

Default value: 001110 (

±14/64

, V

: PWM driver supply voltage)

Tracking drive output conversion

SFJP:

Surf jump mode on/off

The tracking PWM output is made by adding the tracking filter output and TJReg (TJ5 to 0), by

setting D7 to 1 (on)

TG6 to TG0:

AGT convergence gain setting value

Default value: 0101110

: preset, V

: PWM driver supply voltage

CXD2588Q/R

$37 (preset: $37 50 BA)

D15

D14

D13

D12

D11

D10

FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS

AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT

FZSH, FZSL: FZC (Focus Zero Cross) slice level

Default value: 01 (1/8

0.4, V

: supply voltage); FE input conversion

FZSH

0
0
1
1

0
1
0
1

1/4

0.4

1/8

0.4

1/16

0.4

1/32

0.4

FZSL

Slice level

SM5 to SM0: Sled move voltage

Default value: 010000 (

±16/64

, V

: PWM driver supply voltage)

Sled drive output conversion

AGS:

AGCNTL self-stop on/off

Default value: 1 (on)

AGJ:

AGCNTL convergence completion judgment time during low sensitivity adjustment (31/63ms,

when MCK = 128Fs)

Default value: 0 (63ms)

AGGF:

Focus AGCNTL internally generated sine wave amplitude (small/large)

Default value: 1 (large)

AGGT:

Tracking AGCNTL internally generated sine wave amplitude (small/large)

Default value: 1 (large)

AGGF

0 (small)
1 (large)

1/32

0.4

1/16

0.4

1/16

0.4

1/8

0.4

AGGT

0 (small)
1 (large)

FE/TE input conversion

AGV1:

AGCNTL convergence sensitivity during high sensitivity adjustment; high/low

Default value: 1 (high)

AGV2:

AGCNTL convergence sensitivity during low sensitivity adjustment; high/low

Default value: 0 (low)

AGHS:

AGCNTL high sensitivity adjustment on/off

Default value: 1 (on)

AGHT:

AGCNTL high sensitivity adjustment time (128/256ms, when MCK = 128Fs)

Default value: 0 (256ms)

: preset

CXD2588Q/R

$38 (preset: $38 00 00)

D15

D14

D13

D12

D11

D10

VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0

VCLM: VC level measurement (on/off)

VCLC: VC level compensation for FCS In register (on/off)

FLM:

Focus zero level measurement (on/off)

FLC0:

Focus zero level compensation for FZC register (on/off)

RFLM: RF zero level measurement (on/off)

RFLC: RF zero level compensation (on/off)

AGF:

Focus auto gain adjustment (on/off)

AGT:

Tracking auto gain adjustment (on/off)

DFSW: Defect disable switch (on/off)

Setting this switch to 1 (on) disables the defect countermeasure circuit.

LKSW: Lock switch (on/off)

Setting this switch to 1 (on) disables the sled free-running prevention circuit.

TBLM: Traverse center measurement (on/off)

TCLM: Tracking zero level measurement (on/off)

FLC1:

Focus zero level compensation for FCS In register (on/off)

TLC2:

Traverse center compensation (on/off)

TLC1:

Tracking zero level compensation (on/off)

TLC0:

VC level compensation for TRK/SLD In register (on/off)

Note) Commands marked with are accepted every 2.9ms. (when MCK = 128Fs)

All commands are on when set to 1.

100

CXD2588Q/R

SD6

Data RAM data for address = SD4 to SD0

Coefficient RAM data for address = SD5 to SD0

SD4

SD3 to SD0

1 1 1 1
1 1 1 0
1 1 0 1
1 1 0 0
0 0 1 1
0 0 1 0
0 0 0 1

1 1

1 0

0 1

0 0 1 1
0 0 1 0
0 0 0 1
0 0 0 0

RF AVRG register
RFDC input signal
FBIAS register
TRVSC register
RFDC envelope (bottom)
RFDC envelope (peak)
RFDC envelope

(peak) (bottom)

VC AVRG register
FE AVRG register
TE AVRG register
FE input signal
TE input signal
SE input signal
VC input signal

8 bits
8 bits
9 bits
9 bits
8 bits
8 bits
8 bits

9 bits
9 bits
9 bits
8 bits
8 bits
8 bits
8 bits

$399F
$399E
$399D
$399C
$3993
$3992
$3991

$398C
$3988
$3984
$3983
$3982
$3981
$3980

8 bits

16 bits

SD5

Readout data

Readout data length

Note) Coefficients K40 to K4F cannot be readout.

: Don't care

See the description for SRO1 of $3F concerning readout methods for the above data.

D15

D14

D13

D12

D11

D10

DAC

SD6

SD5

SD4

SD3

SD2

SD1

SD0

DAC:

Serial data readout DAC mode (on/off)

SD6 to SD0: Serial readout data select

$39

101

CXD2588Q/R

$3A (preset: $3A 00 00)

D15

D14

D13

D12

D11

D10

FBON FBSS FBUP FBV1 FBV0

TJD0 FPS1 FPS0 TPS1 TPS0

SJHD INBK MTI0

FBON:

FBIAS (focus bias) register addition (on/off)

The FBIAS register value is added to the signal loaded into the FCS In register by FBON = 1

(on).

FBSS:

FBIAS (focus bias) register/counter switching

FBSS = 0: register, FBSS = 1: counter.

FBUP:

FBIAS (focus bias) counter up/down operation switching

This performs counter up/down control when FBSS = 1. FBUP = 0: down counter,

FBUP = 1: up counter.

FBV1, FBV0:

FBIAS (focus bias) counter voltage switching

The number of FCS BIAS count-up/-down steps per cycle is decided by these bits.

TJD0:

This sets the tracking servo filter data RAM to 0 when switched from track jump to servo on

only when SFJP = 1 (during surf jump operation).

FPS1, FPS0:

Gain setting when transferring data from the focus filter to the PWM block.

TPS1, TPS0:

Gain setting when transferring data from the tracking filter to the PWM block.

This is effective for increasing the overall gain in order to widen the servo band.

Operation when FPS1, FPS0 (TPS1, TPS0) = 00 is the same as usual (7-bit shift). However,

6dB, 12dB and 18dB can be selected independently for focus and tracking by setting the

relative gain to 0dB when FPS1, FPS0 (TPS1, TPS0) = 00.

SJHD:

This holds the tracking filter output at the value when surf jump starts during surf jump.

INBK:

When INBK = 0 (off), the brake circuit masks the tracking drive signal with TRKCNCL which is

generated by taking the MIRR signal at the TZC edge. When INBK = 1 (on), the tracking filter

input is masked instead of the drive output.

MTI0:

The tracking filter input is masked when the MIRR signal is high by setting MTI0 = 1 (on).

The counter changes once for each

sampling cycle of the focus servo filter.

When MCK is 128Fs, the sampling

frequency is 88.2kHz. When converted

to FE input, 1 step is approximately 1/2

0.4, V

= supply voltage.

FBV1

FBV0

Number of steps per cycle

FPS1

FPS0

0dB

+6dB

+12dB

+18dB

Relative gain

TPS1

TPS0

0dB

+6dB

+12dB

+18dB

Relative gain

: preset

102

CXD2588Q/R

$3B (preset: $3B E0 50)

SFOX, SFO2, SFO1: FOK slice level

Default value: 011 (28/256

0.57, V

= supply voltage)

RFDC input conversion

SFOX

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

16/256

0.57

20/256

0.57

24/256

0.57

28/256

0.57

32/256

0.57

40/256

0.57

48/256

0.57

50/256

0.57

SFO2

0
1
0
1
0
1
0
1

SFO1

Slice level

D15

D14

D13

D12

D11

D10

SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT

: preset

103

CXD2588Q/R

SDF2, SDF1: DFCT slice level

Default value: 10 (0.0313

1.14V)

RFDC input conversion

SDF2

0
0
1
1

0
1
0
1

0.0156

1.14

0.0234

1.14

0.0313

1.14

0.0391

1.14

SDF1

Slice level

MAX2, MAX1: DFCT maximum time (MCK = 128Fs)

Default value: 00 (no timer limit)

MAX2

0
0
1
1

0
1
0
1

No timer limit
2.00ms
2.36
2.72

MAX1

DFCT maximum time

BTF:

Bottom hold double-speed count-up mode for MIRR signal generation
On/off (default: off)
On when set to 1.

D2V2, D2V1:

Peak hold 2 for DFCT signal generation
Count-down speed setting
Default value: 01 (0.086

1.14V/ms, 44.1kHz)

[V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the
operating frequency of the internal counter.

D1V2, D1V1:

Peak hold 1 for DFCT signal generation
Count-down speed setting
Default value: 01 (0.688

1.14V/ms, 352.8kHz)

[V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the
operating frequency of the internal counter.

RINT:

This initializes the initial-state registers of the circuits which generate MIRR, DFCT and FOK.

D2V2

0
0
1
1

0
1
0
1

22.05
44.1
88.2

176.4

0.0431

1.14

0.0861

1.14

0.172

1.14

0.344

1.14

D2V1

Count-down speed

[V/ms]

[kHz]

: preset, V

: supply voltage

D2V2

0
0
1
1

0
1
0
1

176.4
352.8
705.6

1411.2

0.344

1.14

0.688

1.14

1.38

1.14

2.75

1.14

D2V1

Count-down speed

[V/ms]

[kHz]

: preset, V

: supply voltage

: preset, V

: supply voltage

: preset

104

CXD2588Q/R

$3C (preset: $3C 00 80)

D15

D14

D13

D12

D11

D10

COSS COTS CETZ CETF COT2 COT1 MOT2

BTS1 BTS0 MRC1 MRC0

COSS, COTS: These select the TZC signal used when generating the COUT signal.

Preset = HPTZC.

STZC is the TZC generated by sampling the TE signal at 700kHz. (when MCK = 128Fs)
DTZC is the delayed phase STZC. (The delay amount can be selected by D14 of $36.)
HPTZC is the fast phase TZC passed through a HPF with a cut-off frequency of 1kHz.
See §5-13.

CETZ:

The input from the TE pin normally enters the TRK filter and is used to generate the TZC
signal. However, the input from the CE pin can also be used. This function is for the center
error servo.
When CETZ = 0, the TZC signal is generated by using the TE input signal.
When CETZ = 1, the TZC signal is generated by using the CE input signal.

CETF:

When CETF = 0, the signal input to the TE pin is input to the TRK servo filter.
When CETF = 1, the signal input to the CE pin is input to the TRK servo filter.

These commands output the TZC signal.
COT2, COT1: This outputs the TZC signal from the COUT pin.

COSS

1
0
0

0
1

STZC
HPTZC
DTZC

COTS

TZC

: preset, --: don't care

BTS1

0
0
1
1

0
1
0
1

1
2
4
8

BTS0

Number of count-up steps per cycle

MRC1

0
0
1
1

0
1
0
1

5.669

11.338
22.675
45.351

MRC0

Setting time [µs]

: preset (when MCK = 128Fs)

MOT2:

The STZC signal is output from the MIRR pin by setting MOT2 to 1.

These commands set the MIRR signal generation circuit.
BTS1, BTS0:

This sets the count-up speed for the bottom hold value of the MIRR generation circuit.
The time per step is approximately 708 ns (when MCK = 128Fs). The preset value is BTS1 = 1,
BTS0 = 0. However, this is valid only when BTF of $3B is 0.

MRC1, MRC0: This sets the minimum pulse width for masking the MIRR signal of the MIRR generation circuit.

As noted in §5-9, the MIRR signal is generated by comparing the waveform obtained by
subtracting the bottom hold value from the peak hold value with the MIRR comparator level.
Strictly speaking, however, for MIRR to become high, these levels must be compared
continuously for a certain time. This sets that time.
The preset value is MRC1 = 0, MRC0 = 0.

COT2

1
0
0

1
0

STZC
HPTZC
COUT

COT1

COUT pin output

: preset, --: don't care

105

CXD2588Q/R

$3D (preset: $3D 00 00)

D15

D14

D13

D12

D11

D10

SFID SFSK THID THSK

TLD2 TLD1 TLD0

SFID:

SLED servo filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK
filter second-stage output.
When the low-frequency component of the tracking error signal obtained from the RF amplifier
is attenuated, the low frequency can be amplified and input to the SLD servo filter.

SFSK:

Only during TRK servo gain up2 operation, coefficient K30 is used instead of K00. Normally
the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain
up2, and error occurs in the DC level at M0D. In this case, the DC level of the signal
transmitted to M00 can be kept uniform by adjusting the K30 value even during the above
switching.

THID:

TRK hold filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK
filter second-stage output.
When signals other than the tracking error signal from the RF amplifier are input to the SE input
pin, the signal transmitted from the TE pin can be obtained as TRK hold filter input.

THSK:

Only during TRK servo gain up2 operation, coefficient K46 is used instead of K40. Normally
the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up
2, and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted
to M18 can be kept uniform by adjusting the K46 value even during the above switching.

Please refer to § 5-21. Filter Composition, for further information on SFID, SFSK, THID and
THSK commands.

TLD0 to 2:

SLD filter correction turns on and off independently of the TRK filter.
Please refer also to $38 (TLC0 to 2) and Figure 5-3.

TLC0

OFF

TLD0

VC level correction

TRK filter

SLD filter

: preset, -- : Don't care

TLC1

OFF

TLD1

Tracking zero level correction

TRK filter

SLD filter

TLC2

OFF

TLD2

Traverse center correction

TRK filter

SLD filter

106

CXD2588Q/R

· Input coefficient inversion when SFID = 1 and THID = 1

The preset coefficients for the TRK filter are negative for input and positive for output. With this, the error input

and servo that outputs reversed phase drive can be hypothesized.

TRK Filter

Negative input coefficient

Positive output coefficient

SLD Filter

Negative input coefficient

Positive output coefficient

TRK Hold Filter

Positive input coefficient

Positive output coefficient

TRK Hold

When SFID = 1, the TRK filter negative input coefficient is applied to the SLD filter, so invert the SLD input

coefficient (K00) code.

For the same reason, when THID = 1, invert the TRK hold input coefficient (K40) code.

TRK Filter

Negative input coefficient

Positive output coefficient

SLD Filter

Positive input coefficient

Positive output coefficient

TRK Hold Filter

Negative input coefficient

Positive output coefficient

TRK Hold

M0D

Please refer also to § 5-20. Filter Composition.

107

CXD2588Q/R

$3E (preset: $3E 00 00)

F1NM, F1DM: Quasi double accuracy setting for FCS servo filter first-stage

On when set to 1; default = 0.
F1NM: Gain normal
F1DM: Gain down

T1NM, T1UM: Quasi double accuracy setting for TRK servo filter first-stage

On when set to 1; default = 0.
T1NM: Gain normal
T1UM: Gain up

F3NM, F3DM: Quasi double accuracy setting for FCS servo filter third-stage

On when set to 1; default = 0.
Generally, the advance amount of the phase becomes large by partially setting the FCS servo
third-stage filter which is used as the phase compensation filter to double accuracy.
F3NM: Gain normal
F3DM: Gain down

T3NM, T3UM: Quasi double accuracy setting for TRK servo filter third-stage

On when set to 1; default = 0.
Generally, the advance amount of the phase becomes large by partially setting the TRK servo
third-stage filter which is used as the phase compensation filter to double accuracy.
T3NM: Gain normal
T3UM: Gain up

Note) Filter first- and third-stage quasi double accuracy settings can be set individually.

See "Filter Composition" at the end of this specification concerning quasi double accuracy.

DFIS:

FCS hold filter input extraction node selection
0: M05 (Data RAM address 05); default
1: M04 (Data RAM address 04)

TLCD:

This command masks the TLC2 command set by D2 of $38 only when FOK is low.
On when set to 1; default = 0

LKIN:

When 0, the internally generated LOCK signal is output to the LOCK pin. (default)
When 1, the LOCK signal can be input from an external source to the LOCK pin.

COIN:

When 0, the internally generated COUT signal is output to the COUT pin. (default)
When 1, the COUT signal can be input from an external source to the COUT pin.
The MIRR, DFCT and FOK signals can also be input from an external source.

MDFI:

When 0, the MIRR, DFCT and FOK signals are generated internally. (default)
When 1, the MIRR, DFCT and FOK signals can be input from an external source through the
MIRR, DFCT and FOK pins.

MIRI:

When 0, the MIRR signal is generated internally. (default)
When 1, the MIRR signal can be input from an external source through the MIRR pin.

D15

D14

D13

D12

D11

D10

F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD

LKIN COIN MDFI MIRI XT1D

XT1D:

The clock input from FSTI can be used without being frequency-divided as the master clock for
the servo block by setting D0 to 1. This command takes precedence over the XTSL pin, XT2D
and XT4D. See the description of $3F for XT2D and XT4D.

MDFI

MIRR, DFCT and FOK are all generated internally.

MIRR only is input from an external source.

MIRR, DFCT and FOK are all input from an external source.

MIRI

: preset, --: don't care

108

CXD2588Q/R

$3F (preset: $3F 00 00)

D15

D14

D13

D12

D11

D10

AGG4 XT4D XT2D

DRR2 DRR1 DRR0

ASFG FTQ LPAS SRO1

AGHF ASOT

XT4D, XT2D: MCK (digital servo master clock) frequency division setting

This command forcibly sets the frequency division ratio to 1/4, 1/2 or 1/1 when MCK is
generated from the signal input to the FSTI pin. See the description of $3E for XT1D.

AGG4:

This varies the amplitude of the internally generated sine wave using the AGGF and AGGT
commands during AGC.
When AGG4 = 0, the default is used. When AGG4 = 1, the setting is as shown in the table below.

AGGF (MSB)

1/64

0.4 [V]

1/32

0.4

1/16

0.4

1/8

0.4

AGGT (LSB)

TE/FE input conversion

DRR2 to DRR0: Partially clears the Data RAM values (0 write).

The following values are cleared when set to 1 (on) respectively; default = 0
DRR2: M08, M09, M0A
DRR1: M00, M01, M02
DRR0: M00, M01, M02 only when LOCK = low
Note) Set DRR1 and DRR0 on for 50µs or more.

ASFG:

When vibration detection is performed during anti-shock circuit operation, FCS servo filter is
forcibly set to gain normal status.
On when set to 1; default = 0

LPAS:

Built-in analog buffer low-current consumption mode
This mode reduces the total analog buffer current consumption for the VC, TE, SE and FE
input analog buffers by using a single operational amplifier.
On when set to 1; default = 0
Note) When using this mode, first check whether each error signal is properly A/D converted

using the SRO1 and SRO0 commands of $3F.

SRO1:

These commands are used to output various data externally continuously which have been
specified with the $39 command. (However, D15 (DAC) of $39 must be set to 1.)
Digital output (SOCK, XOLT and SOUT) can be obtained from three specified pins by setting
these commands to 1 respectively. The default is 0, 0. (no readout)

The output pins for each case are shown below.

SOCK
XOLT
SOUT

LMUT pin
WFCK pin
RMUT pin

SRO1 = 1

(See "Description of Data Readout" on the following page.)

AGHF:

This halves the frequency of the internally generated sine wave during AGC.

FTQ:

The slope of the output during focus search is a quarter of the conventional output slope. ON
when set to 1, default = 0.

ASOT:

The anti-shock signal, which is internally detected, is output from the ATSK pin. Output when
set to 1; default = 0.
Vibration detection when a high signal is output for the anti-shock signal output.

These settings are the same for
both focus auto gain control and
tracking auto gain control.

: preset, --: don't care

XT1D

XT2D

XT4D

According to XTSL

1/1

1/2

1/4

Frequency division ratio

: preset

109

CXD2588Q/R

Description of Data Readout

SOCK

(5.6448MHz)

XOLT

(88.2kHz)

SOUT

MSB

LSB

· · ·

MSB

LSB

· · ·

16-bit register for

serial/parallel

conversion

16-bit register

for latch

SOUT

SOCK

XOLT

CLK

MSB

LSB

To the 7-segment LED

Data is connected to the 7-segment LED by
4-bits at a time. This enables Hex display
using four 7-segment LEDs.

MSB

LSB

SOUT

SOCK

XOLT

Serial data input

Clock input

Latch enable input

Analog
output

D/A

To an oscilloscope, etc.

Offset adjustment,
gain adjustment

Waveforms can be monitored with an oscilloscope using
a serial input-type D/A converter as shown above.

110

CXD2588Q/R

§5-19. List of Servo Filter Coefficients

<Coefficient Preset Value Table (1)>

Fix indicates that normal preset values.

ADDRESS

K00
K01
K02
K03
K04
K05
K06
K07
K08
K09

K0A
K0B

K0C
K0D

K0E

K0F

81
23

10
14
30

46
81

58
82

K10
K11
K12
K13
K14
K15
K16
K17
K18
K19

K1A
K1B

K1C
K1D

K1E

K1F

K20
K21
K22
K23
K24
K25
K26
K27
K28
K29

K2A
K2B

K2C
K2D

K2E

K2F

32
20
30
80
77
80
77
00

F1
7F

81
44

TRACKING INPUT GAIN
TRACKING HIGH CUT FILTER A
TRACKING HIGH CUT FILTER B
TRACKING LOW BOOST FILTER A-H
TRACKING LOW BOOST FILTER A-L
TRACKING LOW BOOST FILTER B-H
TRACKING LOW BOOST FILTER B-L

82
44
18
30

46
81

66
82
44

4E
1B

00
00

DATA

CONTENTS

111

CXD2588Q/R

<Coefficient Preset Value Table (2)>

ADDRESS

K30
K31
K32
K33
K34
K35
K36
K37
K38
K39

K3A
K3B

K3C
K3D

K3E

K3F

80
66
00

80
44

77
86

57
00

K40
K41
K42
K43
K44
K45
K46
K47
K48
K49

K4A
K4B

K4C
K4D

K4E

K4F

7F
7F

79
17

00
00
02

7F
7F

79
17
54
00
00

TRACKING HOLD FILTER INPUT GAIN
TRACKING HOLD FILTER A-H
TRACKING HOLD FILTER A-L
TRACKING HOLD FILTER B-H
TRACKING HOLD FILTER B-L
TRACKING HOLD FILTER OUTPUT GAIN
TRACKING HOLD FILTER INPUT GAIN (Only when TRK Gain Up2 is accessed with THSK = 1.)
NOT USED
FOCUS HOLD FILTER INPUT GAIN
FOCUS HOLD FILTER A-H
FOCUS HOLD FILTER A-L
FOCUS HOLD FILTER B-H
FOCUS HOLD FILTER B-L
FOCUS HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED

DATA

CONTENTS

112

CXD2588Q/R

§5-20. Filter Composition

The internal filter composition is shown below.

and M

indicate coefficient RAM and Data RAM address values respectively.

FCS Servo Gain Normal fs = 88.2kHz

K0D

K0C

K0E

K10

K0B

K09

K0A

K08

M04

M03

M05

M06

K11

K13

K0F

FCS

Hold Reg 1

FCS

AUTO Gain

FCS PWM

FCS SRCH

M07

K06

AGFON

K06

DFCT

FCS

Hold Reg 2

FCS

In Reg

Sin ROM

FCS Servo Gain Down fs = 88.2kHz

K29

K28

K2A

K2C

K27

K25

K26

K24

M04

M03

M05

M06

K2D

K13

K2B

FCS

Hold Reg 1

FCS

AUTO Gain

FCS PWM

FCS SRCH

M07

K06

DFCT

FCS

Hold Reg 2

FCS

In Reg

Note) Set the MSB bit of the K0B and K0D coefficients to 0.

Note) Set the MSB bit of the K27 and K29 coefficients to 0.

113

CXD2588Q/R

TRK Servo Gain Normal fs = 88.2kHz

K1F

K1E

K20

K21

K1D

K1B

K1C

K1A

M0C

M0B

M0D

M0E

K22

K23

TRK

AUTO Gain

TRK PWM

TRK JMP

M0F

K19

AGTON

K19

DFCT

TRK

Hold Reg

TRK

In Reg

Sin ROM

To SLD Servo, TRK Hold

Note) Set the MSB bit of the K1D and K1F coefficients to 0.

TRK Servo Gain Up 1 fs = 88.2kHz

K3D

K1B

K3C

K1A

M0C

M0B

M0E

K3E

K23

TRK

AUTO Gain

TRK PWM

TRK JMP

M0F

K19

DFCT

TRK

Hold Reg

TRK

In Reg

114

CXD2588Q/R

TRK Servo Gain Up 2 fs = 88.2kHz

K3B

K3A

K3C

K3D

K39

K37

K38

K36

M0C

M0B

M0D

M0E

K3E

K23

TRK

AUTO Gain

TRK PWM

TRK JMP

M0F

K19

DFCT

TRK

Hold Reg

TRK

In Reg

To SLD Servo, TRK Hold

Note) Set the MSB bit of the K39 and K3B coefficients to 0.

SLD Servo fs = 345Hz

K04

K03

K02

K01

K00

M00

M01

K05

K07

TRK

AUTO Gain

SLD PWM

SLD MOV

M02

SLD

In Reg

K30

SFSK (only when TGUP2 is used)

SFID

M0D

TRK SERVO FILTER
Second-stage output

Note) Set the MSB bit of the K02 and K04 coefficients to 0.

HPTZC/Auto Gain fs = 88.2kHz

K15

K17

K14

M08

M09

M0A

AUTO Gain

Reg

AGTON
AGFON

AGFON

FCS

In Reg

TRK

In Reg

Sin ROM

Slice

TZC Reg

Slice

115

CXD2588Q/R

Anti Shock fs = 88.2kHz

K34

K33

K31

K16

M09

M08

M0A

K35

Comp

K12

Anti Shock

Reg

TRK

In Reg

Note) Set the MSB bit of the K34 coefficient to 0.

The comparator input is 1/16 the maximum amplitude of the comparator input.

AVRG fs = 88.2kHz

M08

AVRG Reg

VC, TE, FE,

RFDC

TRK Hold fs = 345Hz

K44

K43

K42

K41

K40

M18

M19

K45

TRK

Hold Reg

SLD

In Reg

K46

THSK (only when TGUP2 is used)

THID

M0D

TRK SERVO FILTER
Second-stage output

Note) Set the MSB bit of the K42 and K44 coefficients to 0.

FCS Hold fs = 345Hz

K4C

K4B

K4A

K49

K48

M10

M11

K4D

FCS

Hold Reg 1

FCS

Hold Reg 2

Note) Set the MSB bit of the K4A and K4C coefficients to 0.

116

CXD2588Q/R

FCS Servo Gain Normal; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EAXX0)

K0D

K0C

80H

K10

K0B

7FH

K0A

81H

M04

M03

M05

M06

K11

K13

K0F

FCS

Hold Reg 1

FCS

AUTO Gain

FCS PWM

FCS SRCH

M07

K06

AGFON

K06

DFCT

FCS

Hold Reg 2

FCS

In Reg

Sin ROM

K08

K09

K0E

81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.

Note) Set the MSB bit of the K0B and K0D coefficients during normal operation, and of the K08, K09

and K0E coefficients during quasi double accuracy to 0.

FCS Servo Gain Down; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3E5XX0)

K29

K28

80H

K2C

K27

7FH

K26

81H

M04

M03

M05

M06

K2D

K13

K2B

FCS

Hold Reg 1

FCS

AUTO Gain

FCS PWM

FCS SRCH

M07

K06

DFCT

FCS

Hold Reg 2

FCS

In Reg

K24

K25

K2A

81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.

Note) Set the MSB bit of the K27 and K29 coefficients during normal operation, and of the K24, K25

and K2A coefficients during quasi double accuracy to 0.

117

CXD2588Q/R

TRK Servo Gain Normal; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EXAX0)

K1F

K1E

80H

K21

K1D

7FH

K1C

81H

M0C

M0B

M0D

M0E

K22

K23

TRK

AUTO Gain

TRK PWM

TRK JMP

M0F

K19

AGTON

K19

DFCT

TRK

Hold Reg

TRK

In Reg

Sin ROM

K1A

K1B

K20

81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.

Note) Set the MSB bit of the K1D and K1F coefficients during normal operation, and of the K1A, K1B

and K20 coefficients during quasi double accuracy to 0.

TRK Servo Gain up 1; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0)

K3D

K3C

7FH

80H

81H

M0C

M0B

M0E

K3E

K23

TRK

AUTO Gain

TRK PWM

TRK JMP

M0F

K19

DFCT

TRK

Hold Reg

TRK

In Reg

K1A

K1B

81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.

Note) Set the MSB bit of the K1A, K1B and K3C coefficients during quasi double accuracy to 0.

118

CXD2588Q/R

TRK Servo Gain up 2; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0)

K3B

K3A

80H

K3D

K39

7FH

K38

81H

M0C

M0B

M0D

M0E

K3E

K23

TRK

AUTO Gain

TRK PWM

TRK JMP

M0F

K19

DFCT

TRK

Hold Reg

TRK

In Reg

K36

K37

K3C

81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.

Note) Set the MSB bit of the K39 and K3B coefficients during normal operation, and of the K36, K37

and K3C coefficients during quasi double accuracy to 0.

119

CXD2588Q/R

§5-21. TRACKING and FOCUS Frequency Response

20K

100

2.1

20K

100

2.1

f Frequency [Hz]

i
n

[
d

]

180°

[
d

r
e

]

0°

180°

90°

f Frequency [Hz]

i
n

[
d

]

180°

[
d

r
e

]

0°

180°

90°

TRACKING frequency response

FOCUS frequency response

NORMAL
GAIN UP

NORMAL
GAIN DOWN

120

CXD2588Q/R

I
R

FIL

BIA

I
N

1
0

I
R

r
i
v

r

C

i
r
c

i
t

§6. Application Circuit

Application circuits shown are typical examples illustrating the operation of the

devices. Sony cannot assume responsibility for any problems arising out of the use of

these circuits or for any infringement of third party patent and other right due to same.

121

CXD2588Q/R

Package Outline

Unit: mm

CXD2588Q

CXD2588R

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

EPOXY RESIN

SOLDER PLATING

COPPER / 42 ALLOY

PACKAGE STRUCTURE

23.9 ± 0.4

QFP-100P-L01

DETAIL A

100PIN QFP (PLASTIC)

20.0 0.1

+ 0.4

0° to 15°

0.15 0.05

+ 0.1

.
8

.
4

.
9

.
4

.
0

.
4

2.75 0.15

+ 0.35

0.65

±0.12

0.15

.
8

.
2

(
1

.
3

)

QFP100-P-1420-A

1.4g

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

EPOXY/PHENOL RESIN

SOLDER PLATING

42 ALLOY

PACKAGE STRUCTURE

DETAIL A

LQFP-100P-L01

QFP100-P-1414-A

100PIN LQFP (PLASTIC)

16.0 ± 0.2

14.0 ± 0.1

0.5 ± 0.08

0.18 0.03

+ 0.08

(0.22)

1.5 0.1

+ 0.2

0.127 0.02

+ 0.05

.
5

.
2

(
1

.
0

)

0° to 10°

0.1 ± 0.1

.
5

.
2

100

0.1

NOTE: Dimension "

" does not include mold protrusion.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXD2588R

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXD2588R