CD Digital Signal Processor with Built-in Digital Servo and DAC
Description
The CXD3021R is a digital signal processor LSI for
CD players. This LSI incorporates a digital servo,
digital filter and 1-bit DAC.
Features
All digital signal processing during playback is
performed with a single chip
Highly integrated mounting possible due to a built-
in RAM
Digital Signal Processor (DSP) Block
Playback mode supporting CAV (Constant Angular
Velocity)
Frame jitter free
0.5
to 32
continuous playback possible with a
low external clock
Allows relative rotational velocity readout
Wide capture range playback mode
Spindle rotational velocity following method
Supports 1
to 32
playback by switching the
built-in VCO
The bit clock, which strobes the EFM signal, is
generated by the digital PLL.
Digital PLL master clock can be set to 2/3 the
conventional one.
EFM data demodulation
Enhanced EFM frame sync signal protection
Refined super strategy-based powerful error
correction
C1: double correction, C2: quadruple correction
Supported during 32
playback
Noise reduction during track jumps
Auto zero-cross mute
Subcode demodulation and Sub-Q data error
detection
Digital CLV spindle servo (built-in oversampling filter)
16-bit traverse counter
Asymmetry correction circuit
CPU interface on serial bus
Error correction monitor signal, etc. output from a
new CPU interface
Servo auto sequencer
Fine search performs track jumps with high
accuracy
Digital audio interface outputs
Digital level meter, peak meter
Bilingual compatible
VCO control mode
Digital Out can be generated from the audio serial
inputs.
Supports three types of DA interface
(48 bits/64 bits/32 bits)
DSP, servo and DAC blocks support sleep mode.
Digital Servo (DSSP) Block
Microcomputer software-based flexible servo control
Offset cancel function for servo error signal
Auto gain control function for servo loop
E:F balance, focus bias adjustment function
Surf jump and surf brake functions supporting micro
two-axis
Tracking filter: 6 stages
Focus filter: 5 stages
Servo drive DAC output possible
Digital Filter and DAC Blocks
Digital de-emphasis
Digital attenuation
8fs oversampling filter
Adoption of a tertiary
noise shaper
Supports double-speed playback
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
Supply voltage
V
DD
0.3 to +4.4
V
Input voltage
V
I
0.3 to +4.4
V
(V
SS
0.3 to V
DD
+ 0.3) V
Output voltage
V
O
0.3 to +4.4
V
Storage temperature
Tstg
40 to +125 C
Supply voltage difference V
SS
AV
SS
0.3 to +0.3
V
V
DD
AV
DD
0.3 to +0.3
V
Recommended Operating Conditions
Supply voltage
V
DD
3.0 to 4.0
V
Operating temperature Topr
20 to +75 C
The V
DD
(min.) for the CXD3021R varies according
to the playback speed and built-in VCO selection.
The V
DD
(min.) for the CXD3021R under various
conditions are as shown on the following page.
1
E98209A9Z-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXD3021R
120 pin LQFP (Plastic)
For the availability of this product, please contact the sales office.
2
CXD3021R
The Maximum Operating Speed graph shows the playback speed V
DD
(min.) at various temperatures.
The playback conditions are that the high-speed VCO1 selects No.4 and VCO2 selects high speed in CAV-W
mode with DSPB = 1.
Maximum Operating Speed
+25C
+55C
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
27
28
29
30
31
32
33
34
35
36
[V]
[
M
u
l
t
i
p
l
e
]
+75C
3
CXD3021R
Block Diagram
Noise
Shaper
Peak
detector
32K RAM
S
e
r
i
a
l
/
p
a
r
a
l
l
e
l
p
r
o
c
e
s
s
o
r
Digital PLL
Vari-Pitch
double
speed
18-times
oversampling
filter
Subcode
P to W
processor
Timing
Generator1
Subcode Q
processor
Servo
auto
sequencer
CPU interface
8Fs Digital Filter
+
1 bit DAC
EFM
Demodulator
Sync
protector
Priority
encoder
D/A data
processor
Digital out
R
e
g
i
s
t
e
r
Address
generator
8
X
T
L
O
X
T
L
I
V
P
C
O
1
R
M
U
T
O
V
P
C
O
2
X
T
S
L
DAC Block
Signal Processor Block
MCKO
V16M
FSTIO
C4M
C16M
VCTL
PDO
VCOI
VCOO
PCO
FILI
FILO
CLTV
RFAC
ASYI
ASYO
ASYE
WFCK
SCOR
MON
FSW
MDP
MDS
SQCK
SQSO
PWMI
VCKI
OSC
TEST
PWMLN
PWMRP
PSSL
DA011
to DA1
MUTE
PWMLP
PWMRN
31 to 35,
37 to 42
SENS
DATA
CLOK
XLAT
DOUT
MD2
DA16 (48PCM)
DA15 (48BCK)
DA14 (64PCM)
DA13 (64BCK)
DA12 (64LRCK)
Servo Block
A
V
D
D
6
A
V
D
D
1
A
V
D
D
2
A
V
D
D
3
A
V
D
D
4
A
V
D
D
5
D
V
S
S
5
A
V
S
S
1
A
V
S
S
2
A
V
S
S
3
A
V
S
S
4
B
S
S
D
D
V
D
D
5
A
V
S
S
5
A
V
S
S
6
MIRR
Servo
Interface
DFCT
FOK
D
V
S
S
4
D
V
S
S
3
D
V
S
S
2
D
V
S
S
1
D
V
D
D
4
D
V
D
D
3
D
V
D
D
2
D
V
D
D
1
DAC
FOCUS
TRACKING
SLED
OpAmp
FAO
TAO
SAO
SERVO DSP
FOCUS SERVO
TRACKING SERVO
SLED SERVO
COUT
MIRR
DFCT
FOK
OpAmp
AnaSw
A/D
CONVERTER
RFDC
TE
SE
FE
VC
CE
ADIO
TES2
TES3
XRST
P
C
M
D
I
B
C
K
I
L
R
C
K
I
EXCK
SBSO
L
M
U
T
O
D
T
S
0
X
W
O
MUX
Error
corrector
Error Rate
counter
Clock
Generator
: Asymmetry Correction
36
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
23
24
25
26
27
28
29
30
1
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
60
70
69
68
67
63
64
65
66
61 62
71
72
97
96
95
94
91
92
93
99
98
102
103
104
105
106
107
108
73
74
81
82
83
84
75
76
77
78
88
87
86
85
90
111
109
110
112
113
114
116
117
118
119
120
Timing
Generator2
CLV processor
4
CXD3021R
Pin Configuration
36
35
34
31
32
33
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1
40
39
38
37
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
70 69 68 67
63
64
65
66
61
62
71
72
97
96
95
94
91
92
93
100
99
98
101
102
103
104
105
106
107
108
73
74
81
82
83
84
75
76
77
78
88 87 86 85
79
80
89
90
111
109
110
112
113
114
115
116
117
118
119
120
C16M
C4M
FSTIO
MCKO
XTSL
DV
SS
2
DA01
DA03
DA04
DA05
DA06
DV
DD
2
DA07
DA08
DA09
DA10
DA11
EXCK
SBSO
SCOR
WFCK
MUTE
DOUT
MD2
DV
DD
3
XRST
SCSY
SQCK
SQSO
DA02
F
S
W
F
O
K
D
F
C
T
M
I
R
R
C
O
U
T
C
L
O
K
X
L
A
T
L
M
U
T
O
D
A
T
A
A
T
S
K
S
C
L
K
S
E
N
S
D
V
D
D
4
A
V
D
D
3
A
V
S
S
3
A
V
S
S
5
X
T
L
I
X
T
L
O
A
V
D
D
5
A
V
D
D
4
P
W
M
R
N
A
V
S
S
4
D
V
S
S
3
X
W
O
T
E
S
O
D
V
S
S
4
P
W
M
R
P
BSSD
AV
DD
6
MON
MDP
MDS
LOCK
SSTP
DV
SS
5
TES2
TES3
DV
DD
5
VCOO
VCOI
TEST
PDO
VCKI
V16M
AV
DD
2
IGEN
AV
SS
2
ADIO
RFDC
CE
TE
FAO
S
E
V
P
C
O
2
V
C
T
L
F
I
L
O
F
I
L
I
P
C
O
C
L
T
V
A
V
S
S
1
R
F
A
C
B
I
A
S
A
S
Y
I
A
S
Y
O
A
V
D
D
1
D
V
D
D
1
D
V
S
S
1
A
S
Y
E
P
S
S
L
W
D
C
K
L
R
C
K
L
R
C
K
I
D
A
1
6
P
C
M
D
I
D
A
1
5
D
A
1
3
D
A
1
2
V
C
V
P
C
O
1
F
E
D
A
1
4
B
C
K
I
TAO
SAO
AV
SS
6
R
M
U
T
O
DTS0
PWMI
P
W
M
L
N
P
W
M
L
P
5
CXD3021R
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
I
I
I
O
O
I
O
I
O
I
I
I
I
O
I
I
O
O
I
O
I
O
I
O
O
O
O
O
O
1, Z, 0
1, Z, 0
Analog
1, Z, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
Sled error signal input.
Focus error signal input.
Center voltage input.
Wide-band EFM PLL VCO2 charge pump output.
Wide-band EFM PLL VCO2 charge pump output 2. Turned on and off by $EX
command FCSW.
Wide-band EFM PLL VCO2 control voltage input.
Master PLL filter output (slave = digital PLL).
Master PLL filter input.
Master PLL charge pump output.
Multiplier VCO control voltage input.
Analog GND.
EFM signal input.
Asymmetry circuit constant current input.
Asymmetry comparator voltage input.
EFM full-swing output (low = V
SS
, high = V
DD
).
Analog power supply.
Digital power supply.
Digital GND.
Asymmetry circuit on/off (low = off, high = on).
Audio data output mode switching input (low: serial, high: parallel).
D/A interface for 48-bit slot. Word clock f = 2Fs.
D/A interface for 48-bit slot. LR clock f = Fs.
LR clock input to DAC (48-bit slot).
DA16 (MSB) output when PSSL = 1, 48-bit slot serial data output (two's
complement, MSB first) when PSSL = 0.
Audio data input to DAC (48-bit slot).
DA15 output when PSSL = 1, 48-bit slot bit clock output when PSSL = 0.
Bit clock input to DAC (48-bit slot).
DA14 output when PSSL = 1, 32-bit/64-bit slot serial data output (two'
complement, LSB first) when PSSL = 0.
DA13 output when PSSL = 1, 32-bit/64-bit slot bit clock output when PSSL = 0.
DA12 output when PSSL = 1, 32-bit/64-bit slot LR clock output when PSSL = 0.
DA11 output when PSSL = 1, GTOP output when PSSL = 0.
DA10 output when PSSL = 1, XUGF output when PSSL = 0.
DA09 output when PSSL = 1, XPLCK output when PSSL = 0.
SE
FE
VC
VPCO1
VPCO2
VCTL
FILO
FILI
PCO
CLTV
AV
SS
1
RFAC
BIAS
ASYI
ASYO
AV
DD
1
DV
DD
1
DV
SS
1
ASYE
PSSL
WDCK
LRCK
LRCKI
DA16
PCMDI
DA15
BCKI
DA14
DA13
DA12
DA11
DA10
DA09
Symbol
I/O
Description
6
CXD3021R
Pin
No.
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
O
O
O
O
O
O
O
O
I
O
I/O
O
O
I
O
I
O
O
O
I
O
I
I
I
I
O
O
O
O
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, Z, 0
1, Z, 0
DA08 output when PSSL = 1, GFS output when PSSL = 0.
DA07 output when PSSL = 1, RFCK output when PSSL = 0.
Digital power supply.
DA06 output when PSSL = 1, C2PO output when PSSL = 0.
DA05 output when PSSL = 1, XRAOF output when PSSL = 0.
DA04 output when PSSL = 1, MNT3 output when PSSL = 0.
DA03 output when PSSL = 1, MNT2 output when PSSL = 0.
DA02 output when PSSL = 1, MNT1 output when PSSL = 0.
DA01 output when PSSL = 1, MNT0 output when PSSL = 0.
Digital GND.
Crystal selection input.
Clock output. Inverted output of XTLI.
Digital servo clock input/output.
(2/3 frequency division for XTLI pin is internally connected.)
1/4 frequency division output for XTLI pin. Changes with variable pitch.
16.9344MHz output. Changes simultaneously with variable pitch.
Digital power supply.
Digital Out on/off control (low = off, high = on).
Digital Out output.
Mute (low: off, high: on).
WFCK (Write Frame Clock) output.
Outputs a high signal when either subcode sync S0 or S1 is detected.
Sub P to W serial output.
SBSO readout clock input.
Sub-Q 80-bit, PCM peak and level data 16-bit outputs.
SQSO readout clock input.
GRSCOR resynchronization input. Normally low, resynchronization is
executed when high.
System reset. Reset when low.
Audio DAC sync window open input. Normally high, window open when low.
Audio DAC right channel zero detection flag.
Audio DAC left channel zero detection flag.
Digital GND.
Analog GND.
Audio DAC PWM output. Right channel, reversed phase.
Audio DAC PWM output. Right channel, forward phase.
DA08
DA07
DV
DD
2
DA06
DA05
DA04
DA03
DA02
DA01
DV
SS
2
XTSL
MCKO
FSTIO
C4M
C16M
DV
DD
3
MD2
DOUT
MUTE
WFCK
SCOR
SBSO
EXCK
SQSO
SQCK
SCSY
XRST
XWO
RMUTO
LMUTO
DV
SS
3
AV
SS
4
PWMRN
PWMRP
Symbol
I/O
Description
7
CXD3021R
Pin
No.
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
O
I
O
O
O
I
I
I
I
I
I/O
I/O
I/O
I/O
O
O
O
O
O
I
O
O
O
I/O
1, 0
1, Z, 0
1, Z, 0
1, Z, 0
1, 0
1, 0
1, 0
1, 0
1, Z, 0
1, 0
1, Z, 0
1, Z, 0
1, 0
Analog power supply.
Master clock power supply.
Master clock crystal oscillation circuit output.
Master clock crystal oscillation circuit input.
Master clock GND.
Analog GND.
Audio DAC PWM output. Left channel, forward phase.
Audio DAC PWM output. Left channel, reversed phase.
Analog power supply.
Digital power supply.
SENS output to CPU.
SENS serial data readout clock input. Set to high when not used.
Anti-shock pin. Set to low when not used.
Serial data input from CPU.
Latch input from CPU. Serial data is latched at the falling edge.
Serial data transfer clock input from CPU.
Digital GND.
Track count signal I/O.
Mirror signal I/O.
Defect signal I/O.
Focus OK signal I/O.
Test pin. Leave this open.
Spindle motor output filter switching output.
GRSCOR output when $8 command SCOR SEL = high.
Analog GND.
Sled filter DAC analog output.
Tracking filter DAC analog output.
Focus filter DAC analog output.
Constant current input for servo filter DAC analog output.
Analog power supply.
Spindle motor on/off control output.
Spindle motor servo control output.
Spindle motor servo control output.
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.
If GFS is low eight consecutive samples, this pin outputs low. Input when
LKIN = high. (See $3E.)
AV
DD
4
AV
DD
5
XTLO
XTLI
AV
SS
5
AV
SS
3
PWMLP
PWMLN
AV
DD
3
DV
DD
4
SENS
SCLK
ATSK
DATA
XLAT
CLOK
DV
SS
4
COUT
MIRR
DFCT
FOK
TESO
FSW
AV
SS
6
SAO
TAO
FAO
BSSD
AV
DD
6
MON
MDP
MDS
LOCK
Symbol
I/O
Description
8
CXD3021R
Notes) The 32-bit/64-bit slot is a LSB first, two's complement output. The 48-bit slot is a MSB first, two's
complement output.
GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync
protection.
XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the
EFM signal transition point coincide.
The GFS signal goes high when the frame sync and the insertion protection timing match. (See $348.)
RFCK is derived from the crystal accuracy, and has a cycle of 136s. (during normal speed)
C2PO represents the data error status.
XRAOF is generated when the 32K RAM exceeds the 28F jitter margin.
Pin
No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
I
I
I
I
I
O
I
I
O
I
O
I
O
I
I
I
1, 0
1, Z, 0
1, 0
Disc innermost track detection signal input.
Digital GND.
Test pin. Normally fixed to low.
Test pin. Normally fixed to low.
Test pin. Normally fixed to low.
Spindle motor external pin input.
Digital power supply.
Analog EFM PLL oscillation circuit output.
Analog EFM PLL oscillation circuit input. flock = 8.6436MHz.
Test pin. Normally fixed to low.
Analog EFM PLL charge pump output.
Variable pitch clock input from the external VCO. fcenter = 16.9344MHz.
Set VCKI to low when the external clock is not input to this pin.
Wide-band EFM PLL VCO2 oscillation output.
Analog power supply.
Connects the operational amplifier current source reference resistance.
Analog GND.
Operational amplifier output.
RF signal input.
Center servo analog input.
Tracking error signal input.
SSTP
DV
SS
5
DTS0
TES2
TES3
PWMI
DV
DD
5
VCOO
VCOI
TEST
PDO
VCKI
V16M
AV
DD
2
IGEN
AV
SS
2
ADIO
RFDC
CE
TE
Symbol
I/O
Description
9
CXD3021R
Electrical Characteristics
1. DC Characteristics
(V
DD
= AV
DD
= 3.3V 10%, Vss = AVss = 0V, Topr = 20 to +75C)
Item
Input leak current (1)
Input leak current (2)
Tri-state pin output leak current
High level input voltage
Low level input voltage
High level input voltage
Low level input voltage
High level input voltage
Low level input voltage
High level input voltage
Low level input voltage
Input voltage
Input voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
Low level output voltage
High level output voltage
Low level output voltage
Input voltage (1)
Input voltage (2)
Input voltage (3)
Input voltage (4)
Input voltage (5)
Input voltage (6)
Output voltage (1)
Output voltage (2)
Output voltage (3)
Output voltage (4)
Output voltage (5)
V
IH
(1)
V
IL
(1)
V
IH
(2)
V
IL
(2)
V
IH
(3)
V
IL
(3)
V
IH
(4)
V
IL
(4)
V
IN
(5)
V
IN
(6)
V
OH
(1)
V
OL
(1)
V
OH
(2)
V
OL
(2)
V
OH
(3)
V
OL
(3)
V
OL
(4)
V
OH
(5)
V
OL
(5)
I
LI
(1)
I
LI
(2)
I
LO
0.7V
DD
0.7V
DD
0.7V
DD
0.7V
DD
V
SS
V
SS
V
DD
0.4
0
V
DD
0.4
0
V
DD
0.2
0
0
V
DD
0.5
0
10
20
5
0.2V
DD
0.2V
DD
0.2V
DD
0.2V
DD
V
DD
V
DD
V
DD
0.4
V
DD
0.4
V
DD
0.4
0.4
V
DD
0.4
10
20
5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A
A
A
Conditions
Min.
Typ.
Max.
Unit
Applicable
pins
Applicable pins
1
DTS0, TES2, TES3, TEST, PSSL
2
ASYE, VCKI
3
ATSK, DATA, MD2, PWMI, SSTP, XLAT, XTSL, PCMDI, XWO
4
CLOK, EXCK, MUTE, SCLK, SCSY, SQCK, XRST, BCKI, LRCKI
5
ASYI, BIAS, CLTV, FILI, IGEN, BSSD, RFAC, VCTL
6
CE, FE, SE, TE, VC, RFDC
7
ASYO, C16M, C4M, DA01 to DA16, DOUT, LRCK, MON, SBSO, SCOR, SQSO, WDCK, WFCK, PWMLP,
PWMLN, PWMRP, PWMRN, RMUTO, LMUTO
8
FSW
9
MCKO
10
MDP, MDS, PCO, PDO, SENS, V16M, VPCO1, VPCO2
11
FILO
12
COUT, DFCT, FOK, LOCK, MIRR, FSTIO
Schmitt input
V
I
5.5V
V
I
5.5V
Schmitt input
Analog input
Analog input
I
OH
= 8mA
I
OL
= 8mA
I
OH
= 4mA
I
OL
= 4mA
I
OH
= 2mA
I
OL
= 4mA
I
OL
= 4mA
I
OH
= 0.28mA
I
OH
= 0.36mA
V
I
= 0 to 5.5V
V
I
= 0.25V
DD
to 0.75V
DD
V
O
= 0 to 3.6V
1
,
12
2
3
4
5
6
9
7
,
10
12
7
,
10
12
8
11
3
,
4
,
5
6
10
10
CXD3021R
2. AC Characteristics
(1) XTLI pin, VCOI pin
(a) When using self-excited oscillation
(Topr = 20 to +75C, V
DD
= AV
DD
= 3.3V 10%)
(b) When inputting pulses to XTLI and VCOI pins
(Topr = 20 to +75C, V
DD
= AV
DD
= 3.3V 10%)
(c) When inputting sine waves to XTLI and VCOI pins via a capacitor
(Topr = 20 to +75C, V
DD
= AV
DD
= 3.3V 10%)
Oscillation
frequency
f
MAX
7
34
MHz
Item
Symbol
Min.
Typ.
Max.
Unit
High level pulse
width
t
WHX
13
500
ns
Low level pulse
width
t
WLX
13
500
ns
Pulse cycle
t
CX
26
1000
ns
Input high level
V
IHX
V
DD
1.0
V
Input low level
V
ILX
0.8
V
Rise time,
fall time
t
R
, t
F
10
ns
Item
Symbol
Min.
Typ.
Max.
Unit
Input amplitude
V
I
2.0
V
DD
+ 0.3 Vp-p
Item
Symbol
Min.
Typ.
Max.
Unit
t
R
t
F
t
WHX
t
WLX
t
CX
V
ILX
V
IHX
0.1
V
IHX
0.9
V
IHX
XTLI
V
DD
/2
11
CXD3021R
(2) CLOK, DATA, XLAT, SQCK and EXCK pins
(V
DD
= AV
DD
= 3.3V 10%, V
SS
= AV
SS
= 0V, Topr = 20 to +75C)
Clock frequency
Clock pulse width
Setup time
Hold time
Delay time
Latch pulse width
EXCK SQCK frequency
EXCK SQCK pulse width
CNIN frequency
CNIN pulse width
f
CK
t
WCK
t
SU
t
H
t
D
t
WL
f
T
t
WT
f
T
t
WT
30
30
30
30
750
750
7.5
16
0.65
65
MHz
ns
ns
ns
ns
ns
MHz
ns
kHz
s
Item
Symbol
Min.
Typ.
Max.
Unit
t
WCK
t
WCK
1/f
CK
t
H
t
SU
t
WL
t
D
1/f
T
t
WT
t
WT
t
H
t
SU
CLOK
DATA
XLAT
EXCK
SQCK
CNIN
SBSO
SQSO
Only when $44 and $45 are executed.
12
CXD3021R
(4) COUT, MIRR and DFCT pins
Operating frequency
(V
DD
= AV
DD
= 3.3V 10%, V
SS
= AV
SS
= 0V, Topr = 20 to +75C)
COUT maximum operating frequency
MIRR maximum operating frequency
DFCT maximum operating frequency
f
COUT
f
MIRR
f
DFCTH
40
40
5
kHz
kHz
kHz
1
2
3
Signal
Symbol
Min.
Typ.
Max.
Unit
Conditions
1
When using a high-speed traverse TZC.
2
When the RF signal continuously satisfies the following conditions during the above traverse.
A = 0.11V
DD
to 0.23V
DD
25%
3
During complete RF signal omission.
When settings related to DFCT signal generation are Typ.
(3) SCLK pin
SCLK frequency
SCLK pulse width
Delay time
f
SCLK
t
SPW
t
DLS
31.3
15
16
MHz
ns
s
Item
Symbol
Min.
Typ.
Max.
Unit
t
SPW
t
DLS
1/f
SCLK
MSB
LSB
...
...
XLAT
SCLK
Serial Readout Data
(SENS)
A
B
B
A + B
13
CXD3021R
(5) BCKI, LRCKI and PCMDI pins
(V
DD
= 3.3V 10%, Topr = 20 to +75C)
Input BCKI frequency
Input BCKI pulse width
Input data setup time
Input data hold time
Input LRCK setup time
Input LRCK hold time
t
BCK
t
WIB
t
IDS
t
IDH
t
ILRH
t
ILRS
100
10
15
10
15
4.5
MHz
ns
Item
Symbol
Min.
Typ.
Max.
Unit
t
ILRH
t
WIB
t
WIB
t
IDH
t
IDS
t
ILRS
50%
BCKI
PCMDI
LRCKI
14
CXD3021R
DAC Analog Characteristics
Measurement conditions
(Ta = 25C, V
DD
= 3.3V, Fs = 44.1kHz, signal frequency = 1kHz, measurement band = 4Hz to 20kHz, master clock = 384fs)
S/N ratio
THD + N
Dynamic range
Channel separation
Output level
Difference in gain between channels
93
0.007
91
91
0.81
0.1
dB
%
dB
dB
V (rms)
dB
Item
Typ.
Unit
(EIAJ)
1
(EIAJ)
(EIAJ)
1,
2
(EIAJ)
Remarks
PWMLP
(PWMRP)
100k
100 10
1000p
220p
8.2k
8.2k
0.1
33k
33k
33k
33k
100p
100p
39k
100p
47k
8.2k
PWMLN
(PWMRN)
15k
15k
15k
15k
1
Using "A" weighting filter
2
60dB, 1kHz input
The analog characteristics measurement circuit is shown below.
PWMLN
PWMRP
PWMRN
PWMLP
TEST DISC
DATA
Audio Circuit
Analog
1ch
2ch
Audio Analyzer
SHIBASOKU (AM51A)
768fs
CXD3021R
Block diagram of analog characteristics measurement
15
CXD3021R
Servo Drive Analog Characteristics
(V
DD
= AV
DD
= 3.0 to 4.0V, V
SS
= AV
SS
= 0V, Topr = 20 to +75C,
BSSD pin is connected to AV
DD
via a 33k
resistor.)
When the load resistance is 200k
or more
When the load resistance is 60k
Maximum output voltage
Minimum output voltage
0.9V
DD
V
SS
0.97V
DD
0.03V
DD
V
DD
0.1V
DD
V
V
Item
Min.
Typ.
Max.
Unit
FAO, TAO, SAO
FAO, TAO, SAO
Applicable pins
Maximum output voltage
Minimum output voltage
V
SS
0.90V
DD
0.03V
DD
0.1V
DD
V
V
Item
Min.
Typ.
Max.
Unit
FAO, TAO, SAO
FAO, TAO, SAO
Applicable pins
16
CXD3021R
Contents
[1] CPU Interface
1-1. CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1-2. CPU Interface Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1-3. CPU Command Presets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1-4. Description of SENS Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
[2] Subcode Interface
2-1. P to W Subcode Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2-2. 80-bit Sub-Q Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
[3] Description of Modes
3-1. CLV-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3-2. CLV-W Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3-3. CAV-W Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3-4. VCO-C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
[4] Description of Other Functions
4-1. Channel Clock Recovery by Digital PLL Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4-2. Frame Sync Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4-3. Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4-4. DA Interface Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4-5. Digital Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4-6. Servo Auto Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4-7. Digital CLV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4-8. Playback Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4-9. DAC Block Playback Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4-10. DAC Block Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4-11. Asymmetry Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4-12. Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
[5] Description of Servo Signal Processing System Functions and Commands
5-1. General Description of Servo Signal Processing System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5-2. Digital Servo Block Master Clock (MCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5-3. DC Offset Cancel [AVRG Measurement and Compensation] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5-4. E:F Balance Adjustment Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5-5. FCS Bias Adjustment Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5-6. AGCNTL Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5-7. FCS Servo and FCS Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5-8. TRK and SLD Servo Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5-9. MIRR and DFCT Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5-10. DFCT Countermeasure Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5-11. Anti-Shock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5-12. Brake Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5-13. COUT Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5-14. Serial Readout Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5-15. Writing to Coefficient RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5-16. DAC Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5-17. Servo Status Changes Produced by LOCK Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5-18. Description of Commands and Data Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5-19. List of Servo Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5-20. Filter Composition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5-21. TRACKING and FOCUS Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
[6] Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Explanation of abbreviations AVRG:
Average
AGCNTL:
Auto gain control
FCS:
Focus
TRK:
Tracking
SLD:
Sled
DFCT:
Defect
17
CXD3021R
[1] CPU Interface
1-1. CPU Interface Timing
CPU interface
This interface uses DATA, CLOK and XLAT to set the modes.
The interface timing chart is shown below.
The internal registers are initialized by a reset when XRST = 0.
1-2. CPU Interface Command Table
Total bit length for each register
Register
0 to 2
3
4 to 6
7
8
9
A
B
C
D
E
8 bits
8 to 24 bits
16 bits
20 bits
32 bits
32 bits
28 bits
20 bits
28 bits
20 bits
20 bits
Total bit length
30ns or more
D18
D19
D20
D21
D22
D23
750ns or more
Valid
CLOK
DATA
XLAT
Registers
D0
D1
18
CXD3021R
Command Table ($0X to 1X)
FOCUS SERVO ON
(FOCUS GAIN
NORMAL)
FOCUS SERVO ON
(FOCUS GAIN
DOWN)
FOCUS SERVO OFF,
0V OUT
FOCUS SERVO OFF,
FOCUS SEARCH
VOLTAGE OUT
FOCUS SEARCH
VOLTAGE DOWN
FOCUS SEACH
VOLTAGE UP
ANTI SHOCK ON
ANTI SHOCK OFF
BRAKE ON
BRAKE OFF
TRACKING GAIN
NORMAL
TRACKING GAIN UP
TRACKING GAIN UP
FILTER SELECT 1
TRACKING GAIN UP
FILTER SELECT 2
1
1
0
0
0
0
1
0
--
--
--
--
--
--
0
1
--
--
--
--
0
--
1
0
--
--
--
--
--
--
0
1
1
1
--
--
--
--
0
1
--
--
--
--
--
--
0
1
--
--
--
--
--
--
1
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0
1
0 0 0 0
0 0 0 1
FOCUS
CONTROL
TRACKING
CONTROL
Reg-
ister
Command
Address
D23 to D20
Data 1
D19
D18
D17
D16
Data 2
D15
D14
D13
D12
Data 3
D11
D10
D9
D8
Data 4
D7
D6
D5
D4
Data 5
D3
D2
D1
D0
--: Don't care
19
CXD3021R
Command Table ($2X to 3X)
TRACKING SERVO OFF
TRACKING SERVO ON
FORWARD TRACK JUMP
REVERSE TRACK JUMP
SLED SERVO OFF
SLED SERVO ON
FORWARD SLED MOVE
REVERSE SLED MOVE
SLED KICK LEVEL
(
1
basic value) (Default)
SLED KICK LEVEL
(
2
basic value)
SLED KICK LEVEL
(
3
basic value)
SLED KICK LEVEL
(
4
basic value)
0
0
1
1
--
--
--
--
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0
1
0
1
--
--
--
--
--
--
--
--
0
0
1
1
--
--
--
--
0
1
0
1
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
2
3
0 0 1 0
0 0 1 1
TRACKING
MODE
SELECT
Reg-
ister
Command
Address
D23 to D20
Reg-
ister
Command
Address
D23 to D20
Data 1
D19
D18
D17
D16
Data 1
D19
D18
D17
D16
Data 2
D15
D14
D13
D12
Data 2
D15
D14
D13
D12
Data 3
D11
D10
D9
D8
Data 4
D7
D6
D5
D4
Data 5
D3
D2
D1
D0
Data 3
D11
D10
D9
D8
Data 4
D7
D6
D5
D4
Data 5
D3
D2
D1
D0
--: Don't care
20
CXD3021R
Command Table ($340X)
KRAM DATA (K00)
SLED INPUT GAIN
KRAM DATA (K01)
SLED LOW BOOST FILTER A-H
KRAM DATA (K02)
SLED LOW BOOST FILTER A-L
KRAM DATA (K03)
SLED LOW BOOST FILTER B-H
KRAM DATA (K04)
SLED LOW BOOST FILTER B-L
KRAM DATA (K05)
SLED OUTPUT GAIN
KRAM DATA (K06)
FOCUS INPUT GAIN
KRAM DATA (K07)
SLED AUTO GAIN
KRAM DATA (K08)
FOCUS HIGH CUT FILTER A
KRAM DATA (K09)
FOCUS HIGH CUT FILTER B
KRAM DATA (K0A)
FOCUS LOW BOOST FILTER A-H
KRAM DATA (K0B)
FOCUS LOW BOOST FILTER A-L
KRAM DATA (K0C)
FOCUS LOW BOOST FILTER B-H
KRAM DATA (K0D)
FOCUS LOW BOOST FILTER B-L
KRAM DATA (K0E)
FOCUS PHASE COMPENSATE FILTER A
KRAM DATA (K0F)
FOCUS DEFECT HOLD GAIN
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3
0 0 1 1
0 1 0 0
0 0 0 0
SELECT
Reg-
ister
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11
D10
D9
D8
Data 1
D7
D6
D5
D4
Data 2
D3
D2
D1
D0
21
CXD3021R
Command Table ($341X)
KRAM DATA (K10)
FOCUS PHASE COMPENSATE FILTER B
KRAM DATA (K11)
FOCUS OUTPUT GAIN
KRAM DATA (K12)
ANTI SHOCK INPUT GAIN
KRAM DATA (K13)
FOCUS AUTO GAIN
KRAM DATA (K14)
HPTZC / AUTO GAIN HIGH PASS FILTER A
KRAM DATA (K15)
HPTZC / AUTO GAIN HIGH PASS FILTER B
KRAM DATA (K16)
ANTI SHOCK HIGH PASS FILTER A
KRAM DATA (K17)
HPTZC / AUTO GAIN LOW PASS FILTER B
KRAM DATA (K18)
FIX
KRAM DATA (K19)
TRACKING INPUT GAIN
KRAM DATA (K1A)
TRACKING HIGH CUT FILTER A
KRAM DATA (K1B)
TRACKING HIGH CUT FILTER B
KRAM DATA (K1C)
TRACKING LOW BOOST FILTER A-H
KRAM DATA (K1D)
TRACKING LOW BOOST FILTER A-L
KRAM DATA (K1E)
TRACKING LOW BOOST FILTER B-H
KRAM DATA (K1F)
TRACKING LOW BOOST FILTER B-L
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3
0 0 1 1
0 1 0 0
0 0 0 1
SELECT
Reg-
ister
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11
D10
D9
D8
Data 1
D7
D6
D5
D4
Data 2
D3
D2
D1
D0
22
CXD3021R
Command Table ($342X)
KRAM DATA (K20)
TRACKING PHASE COMPENSATE FILTER A
KRAM DATA (K21)
TRACKING PHASE COMPENSATE FILTER B
KRAM DATA (K22)
TRACKING OUTPUT GAIN
KRAM DATA (K23)
TRACKING AUTO GAIN
KRAM DATA (K24)
FOCUS GAIN DOWN HIGH CUT FILTER A
KRAM DATA (K25)
FOCUS GAIN DOWN HIGH CUT FILTER B
KRAM DATA (K26)
FOCUS GAIN DOWN LOW BOOST FILTER A-H
KRAM DATA (K27)
FOCUS GAIN DOWN LOW BOOST FILTER A-L
KRAM DATA (K28)
FOCUS GAIN DOWN LOW BOOST FILTER B-H
KRAM DATA (K29)
FOCUS GAIN DOWN LOW BOOST FILTER B-L
KRAM DATA (K2A)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
KRAM DATA (K2B)
FOCUS GAIN DOWN DEFECT HOLD GAIN
KRAM DATA (K2C)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
KRAM DATA (K2D)
FOCUS GAIN DOWN OUTPUT GAIN
KRAM DATA (K2E)
NOT USED
KRAM DATA (K2F)
NOT USED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3
0 0 1 1
0 1 0 0
0 0 1 0
SELECT
Reg-
ister
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11
D10
D9
D8
Data 1
D7
D6
D5
D4
Data 2
D3
D2
D1
D0
23
CXD3021R
Command Table ($343X)
KRAM DATA (K30)
SLED INPUT GAIN
(when TGup2 is accessed with SFSK = 1)
KRAM DATA (K31)
ANTI SHOCK LOW PASS FILTER B
KRAM DATA (K32)
NOT USED
KRAM DATA (K33)
ANTI SHOCK HIGH PASS FILTER B-H
KRAM DATA (K34)
ANTI SHOCK HIGH PASS FILTER B-L
KRAM DATA (K35)
ANTI SHOCK FILTER COMPARATE GAIN
KRAM DATA (K36)
TRACKING GAIN UP2 HIGH CUT FILTER A
KRAM DATA (K37)
TRACKING GAIN UP2 HIGH CUT FILTER B
KRAM DATA (K38)
TRACKING GAIN UP2 LOW BOOST FILTER A-H
KRAM DATA (K39)
TRACKING GAIN UP2 LOW BOOST FILTER A-L
KRAM DATA (K3A)
TRACKING GAIN UP2 LOW BOOST FILTER B-H
KRAM DATA (K3B)
TRACKING GAIN UP2 LOW BOOST FILTER B-L
KRAM DATA (K3C)
TRACKING GAIN UP PHASE COMPENSATE FILTER A
KRAM DATA (K3D)
TRACKING GAIN UP PHASE COMPENSATE FILTER B
KRAM DATA (K3E)
TRACKING GAIN UP OUTPUT GAIN
KRAM DATA (K3F)
NOT USED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3
0 0 1 1
0 1 0 0
0 0 1 1
SELECT
Reg-
ister
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11
D10
D9
D8
Data 1
D7
D6
D5
D4
Data 2
D3
D2
D1
D0
24
CXD3021R
Command Table ($344X)
KRAM DATA (K40)
TRACKING HOLD FILTER INPUT GAIN
KRAM DATA (K41)
TRACKING HOLD FILTER A-H
KRAM DATA (K42)
TRACKING HOLD FILTER A-L
KRAM DATA (K43)
TRACKING HOLD FILTER B-H
KRAM DATA (K44)
TRACKING HOLD FILTER B-L
KRAM DATA (K45)
TRACKING HOLD FILTER OUTPUT GAIN
KRAM DATA (K46)
TRACKING HOLD INPUT GAIN
(when TGup2 is accessed with THSK = 1)
KRAM DATA (K47)
NOT USED
KRAM DATA (K48)
FOCUS HOLD FILTER INPUT GAIN
KRAM DATA (K49)
FOCUS HOLD FILTER A-H
KRAM DATA (K4A)
FOCUS HOLD FILTER A-L
KRAM DATA (K4B)
FOCUS HOLD FILTER B-H
KRAM DATA (K4C)
FOCUS HOLD FILTER B-L
KRAM DATA (K4D)
FOCUS HOLD FILTER OUTPUT GAIN
KRAM DATA (K4E)
NOT USED
KRAM DATA (K4F)
NOT USED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3
0 0 1 1
0 1 0 0
0 1 0 0
SELECT
Reg-
ister
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11
D10
D9
D8
Data 1
D7
D6
D5
D4
Data 2
D3
D2
D1
D0
25
CXD3021R
Command Table ($348X to 34FX)
FCS Bias Limit
FCS Bias Data
Traverse Center Data
3
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
0
1
0
FBL9
FB9
TV9
FBL8
FB8
TV8
FBL7
FB7
TV7
FBL6
FB6
TV6
FBL5
FB5
TV5
FBL4
FB4
TV4
FBL3
FB3
TV3
FBL2
FB2
TV2
FBL1
FB1
TV1
--
--
TV0
SELECT
Reg-
ister
Command
Address 1
Address 2
D23 to D20
Address 3
D15
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D1
D0
D3
D2
Data 3
Data 2
Data 1
Address 3
D14
D13
D12
Data 1
D11
D10
D9
D8
Data 2
D7
D6
D5
D4
Data 3
D3
D2
D1
D0
--: Don't care
0 0 1 1
D19 to D16
0 1 0 0
PGFS1
0
A/D
SEL
SFBK1
THBON
FAON
PGFS0
0
COPY
EN
SFBK2
FHBON
TAON
PFOK1
0
EMPH
D
0
TLB1ON
SAON
PFOK0
0
CAT
b8
0
FLB1ON
0
PGFS, PFOK, MIRR
DOUT
Booster Surf Brake
Booster
Servo DAC output
0
0
DOUT
EN
0
TLB2ON
FAOZ
0
0
DOUT
DMUT
0
0
TAOZ
0
0
DOUT
WOD
0
HBST1
SAOZ
0
0
WIN
EN
0
HBST0
0
MRT1
0
DOUT
EN2
0
LB1S1
0
MRT0
0
0
0
LB1S0
0
0
0
0
0
LB2S1
0
0
0
0
0
LB2S0
0
26
CXD3021R
Command Table ($35X to 3FX)
FCS search, AGF
TRK jump, AGT
FZC, AGC, SLD move
DC measure, cancel
Serial data read out
FCS Bias, Gain,
Surf jump/brake
Mirr, DFCT, FOK
TZC, Cout, Bottom, Mirr
SLD filter
Filter
Clock, others
3
FT1
TDZC
FZSH
VCLM
DAC
0
SFO2
COSS
SFID
F1NM
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
FT0
DTZC
FZSL
VCLC
SD6
FBON
SFO1
COTS
SFSK
F1DM
AGC4
FS5
TJ5
SM5
FLM
SD5
FBSS
SDF2
CETZ
THID
F3NM
XT4D
FS4
TJ4
SM4
FLC0
SD4
FBUP
SDF1
CETF
THSK
F3DM
XT2D
FS3
TJ3
SM3
RFLM
SD3
FBV1
MAX2
COT2
0
TINM
0
FS2
TJ2
SM2
RFLC
SD2
FBV0
MAX1
COT1
TLD2
TIUM
DRR2
FS1
TJ1
SM1
AGF
SD1
0
SFOX
MOT2
TLD1
T3NM
DRR1
FS0
TJ0
SM0
AGT
SD0
TJD0
BTF
0
TLD0
T3UM
DRR0
FTZ
SFJP
AGS
DFSW
0
FPS1
D2V2
BTS1
0
DF1S
0
FG6
TG6
AGJ
LKSW
0
FPS0
D2V1
BTS0
0
TLCD
ASFG
FG5
TG5
AGGF
TBLM
0
TPS1
D1V2
MRC1
0
0
FTQ
FG4
TG4
AGGT
TCLM
0
TPS0
D1V1
MRC0
0
LKIN
LPAS
FG3
TG3
AGV1
FLC1
0
0
RINT
0
0
COIN
SRO1
FG2
TG2
AGV2
TLC2
0
SJHD
0
0
0
MDFI
SRO0
FG1
TG1
AGHS
TLC1
0
INBK
0
0
0
MIRI
AGHF
FG0
TG0
AGHT
TLC0
0
MTI0
0
0
0
XT1D
0
SELECT
Reg-
ister
Command
Address 1
Address 2
D23 to D20
D19
D18
D17
D16
Data 1
D15
D14
D13
D12
Data 2
D11
D10
D9
D8
Data 3
D7
D6
D5
D4
Data 4
D3
D2
D1
D0
0 0 1 1
27
CXD3021R
Command Table ($4X to EX)
Auto sequence
Blind (A, E),
Brake (B),
Overflow (C, G)
Sled KICK,
BRAKE (D),
KICK (F)
Auto sequence (N)
track jump count
setting
MODE
specification
Function
specification
Audio CTRL
Traverse monitor
counter setting
Spindle servo
coefficient setting
CLV CTRL
SPD mode
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
AS3
TR3
SD3
32768
CD-
ROM
DCLV
ON/OFF
0
32768
Gain
MDP1
DCLV
PWM MD
CM3
AS2
TR2
SD2
16384
DOUT
Mute
DSPB
ON/OFF
0
16384
Gain
MDP0
TB
CM2
AS1
TR1
SD1
8192
DOUT
Mute-F
ASEQ
ON/OFF
Mute
8192
Gain
MDS1
TP
CM1
AS0
TR0
SD0
4096
WSEL
DPLL
ON/OFF
ATT
4096
Gain
MDS0
CLVS
Gain
CM0
MT3
0
KF3
2048
VCO
SEL1
BiliGL
MAIN
PCT1
2048
Gain
DCLV1
VP7
EPWM
MT2
0
KF2
1024
ASHS
BiliGL
SUB
PCT2
1024
Gain
DCLV0
VP6
SPDC
MT1
0
KF1
512
SOCT0
FLFC
MCSL
512
PCC1
VP5
ICAP
MT0
0
KF0
256
VCO
SEL2
XWOC
SOC2
256
PCC0
VP4
SFSL
LSSL
0
0
128
KSL3
DAC
EMP
DCOF
128
SFP3
VP3
VC2C
0
0
0
64
KSL2
DAC
ATT
FMUT
64
SFP2
VP2
HIFC
0
0
0
32
KSL1
SYCOF
BSBST
32
SFP1
VP1
LPWR
0
0
0
16
KSL0
0
BBSL
16
SFP0
VP0
VPON
--
--
--
8
VC01
CS1
PLM3
ATTCH
SEL
8
SRP3
VP
CTL1
Gain
CAV1
--
--
--
4
VCO1
CS0
PLM2
ATD10
4
SRP2
VP
CTL0
Gain
CAV0
--
--
--
2
XVCO2
THRU
PLM1
ATD9
2
SRP1
0
FCSW
--
--
--
1
VCO2
CS
PLM0
ATD8
1
SRP0
0
INV
VPCO
4
5
6
7
8
9
A
B
C
D
E
Reg-
ister
Command
Address
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
Data 1
Data 2
Data 3
Data 4
--: Don't care
28
CXD3021R
FOCUS SERVO OFF,
0V OUT
TRACKING GAIN UP
FILTER SELECT 1
TRACKING SERVO OFF
SLED SERVO OFF
SLED KICK LEVEL
(
1
basic value) (Default)
KRAM DATA
($3400XX to $344fXX)
0
0
0
0
0
0
0
0
0
0
1
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0
1
2
0 0 0 0
0 0 0 1
0 0 1 0
FOCUS
CONTROL
TRACKING
CONTROL
TRACKING
MODE
Reg-
ister
Command
Address
D23 to D20
Data 1
D19
D18
D17
D16
Data 2
D15
D14
D13
D12
Data 3
D11
D10
D9
D8
Data 4
D7
D6
D5
D4
Data 5
D3
D2
D1
D0
Reg-
ister
Command
3
SELECT
Address
D23 to D20
0 0 1 1
0 0 1 1
0
1
0
0
0
See "Coefficient ROM Preset Values Table".
0
0
0
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Data 1
D19
D18
D17
D16
Data 2
D15
D14
D13
D12
Data 3
D11
D10
D9
D8
Data 4
D7
D6
D5
D4
Data 5
D3
D2
D0
D0
Address 1
D23 to D20
D19
D18
D17
D16
Address 2
D15
D14
D13
D12
Address 3
D11
D10
D9
D8
Data 1
D7
D6
D5
D4
Data 2
D3
D2
D0
D0
1-3. CPU Command Presets
Command Preset Table ($0X to 344X)
--: Don't care
Command Table ($4X to EX) cont.
--: Don't care
MODE
specification
1 0 0 0
ERC4
SCOR
SEL
SCSY
SOCT1
0
0
OUTL
0
8
Function
specification
Audio CTRL
Spindle servo
coefficient setting
1 0 0 1
1 0 1 0
1 1 0 0
DAC
SMUTL
ATD7
EDC7
DAC
SMUTR
ATD6
EDC6
ZMUT
ATD5
EDC5
ZDPL
ATD4
EDC4
0
ATD3
EDC3
0
ATD2
EDC2
0
ATD1
EDC1
SLBS
ATD0
EDC0
9
A
C
Reg-
ister
Command
Address
Data 1
Data 2
Data 3
Data 4
D3
D2
D1
D0
D3
D2
D1
D0
Data 5
Data 6
FSTIN
0
0
0
DIV4
--
--
DSP
SLEEP
--
--
DSSP
SLEEP
--
--
DAC
SLEEP
--
--
D3
D2
D1
D0
Data 7
29
CXD3021R
Command Preset Table ($348X to 34FX)
PGFS, PFOK, MIRR
CAV control
DOUT
Booster Surf Brake
Booster
Servo DAC output
FCS Bias Limit
FCS Bias Data
Traverse Center Data
3
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SELECT
Reg-
ister
Command
Address 1
Address 2
D23 to D20
Address 3
D15
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D1
D0
D3
D2
Data 3
Data 2
Data 1
Address 3
D14
D13
D12
Data 1
D11
D10
D9
D8
Data 2
D7
D6
D5
D4
Data 3
D3
D2
D1
D0
0 0 1 1
D19 to D16
0 1 0 0
30
CXD3021R
Command Preset Table ($35X to 3FX)
FCS search, AGF
TRK jump, AGT
FZC, AGC, SLD move
DC measure, cancel
Serial data read out
FCS Bias, Gain,
Surf jump/brake
Mirr, DFCT, FOK
TZC, Cout, Bottom, Mirr
SLD filter
Filter
Clock, others
3
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
SELECT
Reg-
ister
Command
Address 1
Address 2
D23 to D20
D19
D18
D17
D16
Data 1
D15
D14
D13
D12
Data 2
D11
D10
D9
D8
Data 3
D7
D6
D5
D4
Data 4
D3
D2
D1
D0
0 0 1 1
31
CXD3021R
Command Preset Table ($4X to EX)
Auto sequence
Blind (A, E),
Brake (B),
Overflow (C, G)
Sled KICK,
BRAKE (D),
KICK (F)
Auto sequence
(N) track jump
count setting
MODE
specification
Function
specification
Audio CTRL
Traverse monitor
counter setting
Spindle servo
coefficient setting
CLV CTRL
SPD mode
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
--
--
--
0
0
1
0
0
0
0
0
--
--
--
0
0
0
1
0
0
0
0
--
--
--
0
0
0
0
0
1
0
0
--
--
--
0
0
1
0
0
1
0
0
4
5
6
7
8
9
A
B
C
D
E
Reg-
ister
Command
Address
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
Data 1
Data 2
Data 3
Data 4
--: Don't care
MODE
specification
Function
specification
Audio CTRL
Spindle servo
coefficient setting
1 0 0 0
1 0 0 1
1 0 1 0
1 1 0 0
8
9
A
C
Reg-
ister
Command
Address
Data 1
Data 2
Data 3
Data 4
D3
D2
D1
D0
D3
D2
D1
D0
Data 5
Data 6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D3
D2
D1
D0
Data 7
0
0
--
--
0
0
--
--
0
0
--
--
0
0
--
--
32
CXD3021R
Fix indicates that normal preset values should be used.
<Coefficient ROM Preset Values Table (1)>
ADDRESS
K00
K01
K02
K03
K04
K05
K06
K07
K08
K09
K0A
K0B
K0C
K0D
K0E
K0F
E0
81
23
7F
6A
10
14
30
7F
46
81
1C
7F
58
82
7F
SLED INPUT GAIN
SLED LOW BOOST FILTER A-H
SLED LOW BOOST FILTER A-L
SLED LOW BOOST FILTER B-H
SLED LOW BOOST FILTER B-L
SLED OUTPUT GAIN
FOCUS INPUT GAIN
SLED AUTO GAIN
FOCUS HIGH CUT FILTER A
FOCUS HIGH CUT FILTER B
FOCUS LOW BOOST FILTER A-H
FOCUS LOW BOOST FILTER A-L
FOCUS LOW BOOST FILTER B-H
FOCUS LOW BOOST FILTER B-L
FOCUS PHASE COMPENSATE FILTER A
FOCUS DEFECT HOLD GAIN
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K1A
K1B
K1C
K1D
K1E
K1F
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K2A
K2B
K2C
K2D
K2E
K2F
4E
32
20
30
80
77
80
77
00
F1
7F
3B
81
44
7F
5E
FOCUS PHASE COMPENSATE FILTER B
FOCUS OUTPUT GAIN
ANTI SHOCK INPUT GAIN
FOCUS AUTO GAIN
HPTZC / Auto Gain HIGH PASS FILTER A
HPTZC / Auto Gain HIGH PASS FILTER B
ANTI SHOCK HIGH PASS FILTER A
HPTZC / Auto Gain LOW PASS FILTER B
Fix
TRACKING INPUT GAIN
TRACKING HIGH CUT FILTER A
TRACKING HIGH CUT FILTER B
TRACKING LOW BOOST FILTER A-H
TRACKING LOW BOOST FILTER A-L
TRACKING LOW BOOST FILTER B-H
TRACKING LOW BOOST FILTER B-L
82
44
18
30
7F
46
81
3A
7F
66
82
44
4E
1B
00
00
TRACKING PHASE COMPENSATE FILTER A
TRACKING PHASE COMPENSATE FILTER B
TRACKING OUTPUT GAIN
TRACKING AUTO GAIN
FOCUS GAIN DOWN HIGH CUT FILTER A
FOCUS GAIN DOWN HIGH CUT FILTER B
FOCUS GAIN DOWN LOW BOOST FILTER A-H
FOCUS GAIN DOWN LOW BOOST FILTER A-L
FOCUS GAIN DOWN LOW BOOST FILTER B-H
FOCUS GAIN DOWN LOW BOOST FILTER B-L
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
FOCUS GAIN DOWN DEFECT HOLD GAIN
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
FOCUS GAIN DOWN OUTPUT GAIN
NOT USED
NOT USED
DATA
CONTENTS
33
CXD3021R
<Coefficient ROM Preset Values Table (2)>
ADDRESS
K30
K31
K32
K33
K34
K35
K36
K37
K38
K39
K3A
K3B
K3C
K3D
K3E
K3F
80
66
00
7F
6E
20
7F
3B
80
44
7F
77
86
0D
57
00
SLED INPUT GAIN (Only when TRK Gain Up2 is accessed with SFSK = 1.)
ANTI SHOCK LOW PASS FILTER B
NOT USED
ANTI SHOCK HIGH PASS FILTER B-H
ANTI SHOCK HIGH PASS FILTER B-L
ANTI SHOCK FILTER COMPARATE GAIN
TRACKING GAIN UP2 HIGH CUT FILTER A
TRACKING GAIN UP2 HIGH CUT FILTER B
TRACKING GAIN UP2 LOW BOOST FILTER A-H
TRACKING GAIN UP2 LOW BOOST FILTER A-L
TRACKING GAIN UP2 LOW BOOST FILTER B-H
TRACKING GAIN UP2 LOW BOOST FILTER B-L
TRACKING GAIN UP PHASE COMPENSATE FILTER A
TRACKING GAIN UP PHASE COMPENSATE FILTER B
TRACKING GAIN UP OUTPUT GAIN
NOT USED
K40
K41
K42
K43
K44
K45
K46
K47
K48
K49
K4A
K4B
K4C
K4D
K4E
K4F
04
7F
7F
79
17
6D
00
00
02
7F
7F
79
17
54
00
00
TRACKING HOLD FILTER INPUT GAIN
TRACKING HOLD FILTER A-H
TRACKING HOLD FILTER A-L
TRACKING HOLD FILTER B-H
TRACKING HOLD FILTER B-L
TRACKING HOLD FILTER OUTPUT GAIN
TRACKING HOLD FILTER INPUT GAIN
(Only when TRK Gain Up2 is accessed with THSK = 1.)
NOT USED
FOCUS HOLD FILTER INPUT GAIN
FOCUS HOLD FILTER A-H
FOCUS HOLD FILTER A-L
FOCUS HOLD FILTER B-H
FOCUS HOLD FILTER B-L
FOCUS HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED
DATA
CONTENTS
34
CXD3021R
1-4. Description of SENS Signals
SENS output
Microcomputer
serial register
(latching not required)
$0X
$1X
$2X
$38
$38
$30 to 37
$3A
$3B to 3F
$3904
$3908
$390C
$391C
$391D
$391F
$4X
$5X
$6X
$AX
$BX
$CX
$EX
$7X, 8X, 9X,
DX, FX
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
GFS
COMP
COUT
OV64
Z
FZC
AS
TZC
AGOK
XAVEBSY
SSTP
FBIAS Count STOP
SSTP
TE Avrg Reg.
FE Avrg Reg.
VC Avrg Reg.
TRVSC Reg.
FB Reg.
RFDC Avrg Reg.
XBUSY
FOK
0
GFS
COMP
COUT
OV64
0
--
--
--
--
--
--
--
--
9 bits
9 bits
9 bits
9 bits
9 bits
8 bits
--
--
--
--
--
--
--
--
ASEQ = 0
ASEQ = 1
Output data length
$38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement.
SSTP is output in all other cases.
35
CXD3021R
Description of SENS Signals
The SENS pin is high impedance.
Low while the auto sequencer is in operation, high when operation terminates.
Outputs the same signal as the FOK pin.
High for "focus OK".
High when the regenerated frame sync is obtained with the correct timing.
Counts the number of tracks set with Reg.B.
High when Reg.B is latched, low when the initial Reg.B number is input by CNIN.
Counts the number of tracks set with Reg.B.
High when Reg.B is latched, toggles each time the Reg.B number is input by CNIN. While $44
and $45 are being executed, toggles with each CNIN 8-count instead of the Reg.B number.
Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing
through the sync detection filter.
Z
XBUSY
FOK
GFS
COMP
COUT
OV64
SENS output
36
CXD3021R
The meaning of the data for each address is explained below.
$4X commands
Register name
4
Data 1
Command
Data 2
MAX timer value
Data 3
Timer range
AS3
AS2
AS1
AS0
MT3
MT2
MT1
MT0
LSSL
0
0
0
Command
Cancel
Fine Search
Focus-On
1 Track Jump
10 Track Jump
2N Track Jump
M Track Move
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
RXF
1
RXF
RXF
RXF
RXF
AS3
AS2
AS1
AS0
RXF = 0 Forward
RXF = 1 Reverse
When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted.
When the Track jump commands ($44 to $45, $48 to $4D) are canceled, $25 is sent and the auto sequence
is interrupted.
To disable the MAX timer, set the MAX timer value to 0.
$5X commands
MAX timer value
MT3
23.2ms
1.49s
11.6ms
0.74s
5.8ms
0.37s
2.9ms
0.18s
0
1
0
0
0
0
0
0
MT2
MT1
MT0
LSSL
0
0
0
Timer range
Timer
TR3
TR2
TR1
TR0
Blind (A, E), Overflow (C, G)
Brake (B)
0.18ms
0.36ms
0.09ms
0.18ms
0.045ms
0.09ms
0.022ms
0.045ms
37
CXD3021R
Command
Data 1
Data 2
Data 3
Data 4
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
Auto sequence track
jump count setting
This command is used to set N when a 2N-track jump is executed, to set M when an M-track move is
executed and to set the jump count when fine search is executed for auto sequencer.
The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count
depends on the mechanical limitations of the optical system.
When the track jump count is from 0 to 15, the COUT signal is counted for 2N-track jumps and M-track
moves; when the count is 16 or over, the MIRR signal is counted. For fine search, the COUT signal is
counted.
$7X commands
Auto sequence track jump count setting
$6X commands
Register name
6
Data 1
KICK (D)
Data 2
KICK (F)
SD3
SD2
SD1
SD0
KF3
KF2
KF1
KF0
Timer
SD3
SD2
SD1
SD0
When executing KICK (D) $44 or $45
When executing KICK (D) $4C or $4D
23.2ms
11.6ms
11.6ms
5.8ms
5.8ms
2.9ms
2.9ms
1.45ms
Timer
KF3
KF2
KF1
KF0
KICK (F)
0.72ms
0.36ms
0.18ms
0.09ms
38
CXD3021R
See "Mute conditions" (1), (2), and (4) to (6) under $AX commands for other mute conditions.
MD2
Other mute conditions
DOUT Mute D.out Mute F DOUT output
OFF
0dB
dB
DA output for
48-bit slot
DA output for
64-bit slot
0dB
0dB
dB
0dB
dB
dB
0dB
dB
0dB
dB
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Command
Data 1
MODE
specification
CD-
ROM
DOUT
Mute
DOUT
Mute-F
WSEL
D3
D2
D1
D0
Data 2
VCO
SEL1
ASHS SOCT0
VCO
SEL2
D3
D2
D1
D0
$8X commands
Command bit
DOUT Mute = 1
DOUT Mute = 0
When Digital Out is on (MD2 pin = 1), DOUT output is muted.
When Digital Out is on, DOUT output is not muted.
Processing
Command bit
D. out Mute F = 1
D. out Mute F = 0
When Digital Out is on (MD2 pin = 1), DA output is muted.
DA output mute is not affected when Digital Out is either on or off.
Processing
Command bit
CDROM = 1
CDROM = 0
C2PO timing
1-3
1-3
CDROM mode; average value interpolation and pre-value hold are not performed.
Audio mode; average value interpolation and pre-value hold are performed.
Processing
39
CXD3021R
Command bit
Sync protection window width
WSEL = 1
WSEL = 0
26 channel clock
6 channel clock
Anti-rolling is enhanced.
Sync window protection is enhanced.
Application
In normal-speed playback, channel clock = 4.3218MHz.
Command bit
Function
ASHS = 0
ASHS = 1
The command transfer rate to SSP is set to normal speed.
The command transfer rate to SSP is set to half speed.
See " 4-8. Playback Speed" for settings.
Command bit
SOCT0
SOCT1
Processing
Sub-Q is output from the SQSO pin.
Each output signal is output from the SQSO pin. Input the readout clock to SQCK.
(See Timing Chart 2-4.)
The error rate is output from the SQSO pin. Input the readout clock to SQCK.
(See Timing Chart 2-6.)
0
1
1
--
0
1
--: Don't care
$8X commands contin.
40
CXD3021R
Command bit
Processing
VCOSEL1 = 0
VCOSEL1 = 1
Multiplier PLL VCO1 is set to normal speed.
Multiplier PLL VCO1 is set to approximately twice the normal speed.
Command bit
KSL3
KSL2
Processing
Output of multiplier PLL VCO1 selected by VCO1, CS1 and CS0 is 1/1 frequency-divided.
Output of multiplier PLL VCO1 selected by VCO1, CS1 and CS0 is 1/2 frequency-divided.
Output of multiplier PLL VCO1 selected by VCO1, CS1 and CS0 is 1/4 frequency-divided.
Output of multiplier PLL VCO1 selected by VCO1, CS1 and CS0 is 1/8 frequency-divided.
0
0
1
1
0
1
0
1
This setting is valid only when the low-speed VCO is selected by VCO1 CS1 and CS0.
See the previous page.
Command
Data 2
MODE
specification
VCO
SEL1
ASHS SOCT0
VCO
SEL2
D3
D2
D1
D0
Data 3
KSL3
KSL2
KSL1
KSL0
D3
D2
D1
D0
Command bit
Processing
VCOSEL2 = 0
VCOSEL2 = 1
Wide-band PLL VCO2 is set to normal speed.
Wide-band PLL VCO2 is set to approximately twice the normal speed.
Command bit
KSL1
KSL0
Processing
Output of wide-band PLL VCO2 selected by VCO2CS is 1/1 frequency-divided.
Output of wide-band PLL VCO2 selected by VCO2CS is 1/2 frequency-divided.
Output of wide-band PLL VCO2 selected by VCO2CS is 1/4 frequency-divided.
Output of wide-band PLL VCO2 selected by VCO2CS is 1/8 frequency-divided.
0
0
1
1
0
1
0
1
This setting is valid only when the low-speed VCO is selected by VCO2CS.
$8X commands contin.
41
CXD3021R
$8X commands contin.
Block Diagram of VCO Internal Path
S
e
l
e
c
t
o
r
1/2
1/1
1/8
1/4
S
e
l
e
c
t
o
r
To DSP interior
KSL3, 2
VCO1CS1, 0
No.2 VCO1
No.3 VCO1
No.4 VCO1
VCO1SEL
No.1 VCO1
Low-speed
VCO2
High-speed
VCO2
S
e
l
e
c
t
o
r
1/2
1/1
1/8
1/4
S
e
l
e
c
t
o
r
To DSP interior
KSL1, 0
VCO2CS
VCO2SEL
VCO1 internal path
VCO2 internal path
42
CXD3021R
Command bit
Processing
VCO2 THRU = 0
VCO2 THRU = 1
V16M output is connected internally to VCKI.
V16M output is not connected internally. Input the clock from VCKI.
This command sets internal or external connection for the VCO2 used in CAV-W mode.
Command bit
Processing
VCO2 CS = 0
VCO2 CS = 1
Low-speed wide-band PLL VCO2 is selected.
High-speed wide-band PLL VCO2 is selected.
The CXD3021R has two wide-band PLL VCO2s, and this command selects one of these VCO2s.
The block diagram for VCO1 and VCO2 including VCOSEL1, VCOSEL2, KSL0 to KSL3, VCO1CS0,
VCO1CS1 and VCO2 CS is shown on the previous page.
The CXD3021R has four multiplier PLL VCO1s, and this command selects one of these VCO1s.
Four VCOs are No.3, No.4, No.2 and No.1 in order of the maximum frequency.
Command bit
VCO1CS1
VCO1CS0
Processing
No.1 (Low-speed VCO for CXD3005R)
No.2 (Middle-speed VCO for CXD3005R)
No.3 (High-speed VCO for CXD3005R)
No.4
0
0
1
1
0
1
0
1
Command
Data 4
MODE
specification
VCO1
CS1
VCO1
CS0
XVCO2
THRU
D3
D2
D1
D0
VCO
CS
$8X commands contin.
43
CXD3021R
Command bit
Processing
ERC4 = 0
ERC4 = 1
C2 error double correction is performed when DSPB = 1.
C2 error quadruple correction is performed even when DSPB = 1.
Command bit
Processing
SCOR SEL = 0
SCOR SEL = 1
FSW signal is output.
GRSCOR (protected SCOR) is output.
Used when outputting GRSCOR from the FSW pin
Command bit
Processing
SCSY = 0
SCSY = 1
No processing.
GRSCOR (protected SCOR) synchronization is applied again.
Used to resynchronize GRSCOR.
The rising edge signal of this command bit is used internally. Therefore, when resynchronizing GRSCOR, first
return the setting to 0 and then set to 1.
GRSCOR achieves the crystal accuracy by removing the jitter components included in the SCOR signal. This
signal is synchronized with PCMDATA.
The resynchronization conditions are when GTOP = high or when the SCSY pin = high.
(Same as when SCSY = 1 is sent by the $8X command.)
Command
Data 5
MODE
specification
ERC4
SCOR
SEL
SCSY SOCT1
D3
D2
D1
D0
Data 6
0
0
OUTL
0
D3
D2
D1
D0
Data 7
FSTIN
0
0
0
D3
D2
D1
D0
$8X commands contin.
Command bit
Processing
No processing.
Outputs of C16M, FSTIO, GTOP, XUGF and XPLCK pins are low.
The PDO pin output is high impedance.
The power consumption can be reduced.
Command bit
Processing
FSTIN = 0
FSTIN = 1
Clock switching for servo block; internally connected. (Preset)
The clock with 2/3 frequency of XTLO pin is input to the servo block.
The FSTIO pin serves as the output pin which monitors the clock for the servo block.
Clock switching for servo block; externally input.
The FSTIO pin serves as the input pin.
The clock for the servo block is input from the FSTIO pin.
44
CXD3021R
Command
Data 1
Function
specification
DCLV
ON-OFF
DSPB
ON-OFF
A.SEQ
ON-OFF
D.PLL
ON-OFF
D3
D2
D1
D0
Data 2
BiliGL
MAIN
BiliGL
SUB
FLFC
D3
D2
D1
XWOC
D0
$9X commands
Command bit
DCLV on/off = 0
CLVS mode
FSW = low, MON = high, MDS = Z; MDP = servo control signal,
carrier frequency of 230Hz at T
B
= 0 and 460Hz at T
B
= 1.
FSW = Z, MON = high; MDS = speed control signal,
carrier frequency of 7.35kHz; MDP = phase control signal,
carrier frequency of 1.8kHz.
When DCLV
PWM and MD = 1
(Prohibited in CLV-W
and CAV-W modes)
MDS = PWM polarity signal, carrier
frequency of 132kHz
MDP = PWM absolute value output (binary),
carrier frequency of 132kHz
When DCLV
PWM and MD = 0
MDS = Z
MDP = ternary PWM output, carrier
frequency of 132kHz
CLVP mode
CLVS and
CLVP modes
DCLV on/off = 1
(FSW, MON not
required)
CLV mode
Contents
When DCLV on/off = 1 for the Digital CLV servo, the sampling frequency of the internal digital filter switches
simultaneously with the CLVP/CLVS switching.
Therefore, the cut-off frequency for CLVS is fc = 70Hz when T
B
= 0, and fc = 140Hz when T
B
= 1.
Command bit
DSPB = 0
DSPB = 1
Normal-speed playback, C2 error quadruple correction.
Double-speed playback, C2 error double correction. (quadruple correction when ERC4 = 1)
Processing
FLFC is normally 0.
FLFC is 1 in CAV-W mode for any playback speed.
Command bit
DPLL = 0
DPLL = 1
RFPLL is analog. PDO, VCOI and VCOO are used.
RFPLL is digital. PDO is impedance.
Meaning
Command bit
BiliGL SUB = 0
BiliGL SUB = 1
STEREO
SUB
MAIN
Mute
BiliGL MAIN = 0
BiliGL MAIN = 1
Definition of bilingual capable MAIN, SUB and STEREO
The left channel input is output to the left and right channels for MAIN.
The right channel input is output to the left and right channels for SUB.
The left and right channel inputs are output to the left and right channels for STEREO.
External parts for the FILI, FILO and PCO pins are required even when analog PLL is selected.
45
CXD3021R
Command
Data 3
Function
specification
DAC
EMPH
DAC
ATT
SYCOF
0
D3
D2
D1
D0
Command bit
DAC EMPH = 1
DAC EMPH = 0
Applies digital de-emphasis. The emphasis constants are
1 = 50s and
2 = 15s when
Fs = 44.1kHz.
Turns digital de-emphasis off.
Processing
Command bit
DAC ATT = 1
DAC ATT = 0
Identical digital attenuation control is used for both the left and right channels. When
common attenuation data is specified, the attenuation values for the left channel are
used.
Independent digital attenuation control is used for both the left and right channels.
Processing
This is used to perform resynchronization to DAC.
This command has the same function as the external pin XWO.
Set to high or 1 for the unused external pin or unused command register, respectively.
Command bit
External pin
XWOC
XWO
Processing
DAC sync window is open.
DAC sync window is not open.
0
0
1
1
L
H
L
H
Command bit
SYCOF = 1
SYCOF = 0
LRCK asynchronous mode.
Normal operation.
Processing
Set SYCOF = 0 in advance in order to resynchronize the DAC using $9 command XWOC or the external pin
XWO.
$9X commands contin.
46
CXD3021R
PLM3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Mute
L
R
L + R
Mute
L
R
L + R
Mute
L
R
L + R
Mute
L
R
L + R
Mute
Mute
Mute
Mute
L
L
L
L
R
R
R
R
L + R
L + R
L + R
L + R
Mute
Reverse
Stereo
Mono
PLM2
PLM1
PLM0
Left channel output Right channel output
Remarks
Note) The output data of L + R is (L + R)/2 to prevent overflow.
Command
Data 4
Function
specification
PLM3
PLM2
PLM1
PLM0
D3
D2
D1
D0
DAC play mode
By controlling these command bits, the DAC output left channel and right channel can be output in 16
different combinations of left channel, right channel, left + right channel, and mute.
The relationship between the commands and the outputs is shown in the table below.
$9X commands contin.
47
CXD3021R
Command
Data 5
Function
specification
DAC
SMUTL
DAC
SMUTR
ZMUT
ZDPL
D3
D2
D1
D0
Command bit
DAC SMUTL = 1
DAC SMUTL = 0
Left channel soft mute is on.
Left channel soft mute is off.
Processing
Command bit
DAC SMUTR = 1
DAC SMUTR = 0
Right channel soft mute is on.
Right channel soft mute is off.
Processing
Command bit
ZMUT = 1
ZMUT = 0
Zero detection mute is on.
Zero detection mute is off.
Processing
Command bit
ZDPL = 1
ZDPL = 0
LMUTO and RMUTO are high during mute.
LMUTO and RMUTO are low during mute.
Processing
See the description of "Mute flag output" for the mute flag output conditions.
$9X commands contin.
48
CXD3021R
Command
Data 6
Function
specification
0
0
0
SLBS
D3
D2
D1
D0
Data 7
DIV4
DSP
SLEEP
DSSP
SLEEP
DAC
SLEEP
D3
D2
D1
D0
Command bit
DIV4 = 0
DIV4 = 1
Digital PLL master clock; conventional mode. (Preset)
Digital PLL master clock; 2/3 mode.
Processing
Command bit
DSP SLEEP = 0
DSP SLEEP = 1
Normal operation
Multiplier PLL VCO1, wide-band PLL VCO2 oscillation and the DSP block clock are halted.
Power consumption can be reduced.
Processing
Command bit
DSSP SLEEP = 0
DSSP SLEEP = 1
Normal operation
Servo block clock is halted and the MDP pin is high impedance.
Power consumption can be reduced
Processing
The master clock of the digital PLL is switched.
The conventional mode or 2/3 mode of the conventional one can be selected.
Command bit
SLBS = 0
SLBS = 1
32-bit/64-bit slot outputs switching; 64-bit slot output. (Preset)
32-bit/64-bit slot outputs switching; 32-bit slot output. (Preset)
Processing
This command bit switches the audio serial output format from the DA12, 13 and 14 pins.
32-bit slot or 64-bit slot can be selected.
Note) Do not set DIV4 to 1 when DSPB=0.
Command writing related to the servo is invalid when DSSP SLEEP=1.
Command bit
DAC SLEEP = 0
DAC SLEEP = 1
Normal operation
DAC block clock is halted.
Power consumption can be reduced.
Processing
Command writing related to the audio DAC is invalid when DAC SLEEP=1.
49
CXD3021R
Command
Data 1
Audio CTRL
0
0
Mute
ATT
D3
D2
D1
D0
Data 2
PCT1
PCT2
D3
D2
MCSL
SOC2
D1
D0
$AX commands
Command bit
Mute = 0
Mute = 1
Mute off if other mute
conditions are not set.
Mute on. Peak register reset.
Meaning
Command bit
ATT = 0
ATT = 1
Attenuation off.
12dB
Meaning
Mute conditions
(1) When register A mute = 1.
(2) When Mute pin = 1.
(3) When register 8 D.out Mute F = 1 and the Digital Out is on (MD2 pin = 1).
(4) When GFS stays low for over 35 ms (during normal speed).
(5) When register 9 BiliGL MAIN = Sub = 1.
(6) When register A PCT1 = 1 and PCT2 = 0.
(1) to (4) perform zero-cross muting with a 1ms time limit.
Command bit
PCT1
0
0
1
1
PCT2
0
1
0
1
Normal mode
Level meter mode
Peak meter mode
Normal mode
0dB
0dB
Mute
0dB
C1: double; C2: quadruple
C1: double; C2: quadruple
C1: double; C2: double
C1: double; C2: double
Meaning
PCM Gain
ECC error correction ability
Description of level meter mode (see Timing Chart 1-4.)
When the LSI is set to this mode, it performs digital level meter functions.
When the 96-bit clock is input to SQCK, 96 bits of data are output to SQSO.
The initial 80 bits are Sub-Q data (see "[2] Subcode Interface"). The last 16 bits are LSB first, which are 15-
bit PCM data (absolute values) and an L/R flag.
The L/R flag is high when the 15-bit PCM data is from the left channel and low when the data is from the right
channel.
The PCM data is reset and the L/R flag is reverted after one readout.
Then maximum value measuring continues until the next readout.
50
CXD3021R
$AX commands contin.
Description of peak meter mode (see Timing Chart 1-5.)
When the LSI is set to this mode, the maximum PCM data value is detected regardless of if it comes from the
left or right channel.
The 96-bit clock must be input to SQCK to read out this data.
When the 96-bit clock is input, 96 bits of data are output to SQSO and the value is set in the LSI internal
register again.
In other words, the PCM maximum value detection register is not reset by the readout.
To reset the PCM maximum value register to zero, set PCT1 = PCT2 = 0 or set the $AX mute.
The Sub-Q absolute time is automatically controlled in this mode.
In other words, after the maximum value is generated, the absolute time for CRC to become OK is retained in
the memory. Normal operation is conducted for the relative time.
The final bit (L/R flag) of the 96-bit data is normally 0.
The pre-value hold and average value interpolation data are fixed to level (
) for this mode.
SENS output switching
This command enables the SQSO pin signal to be output from the SENS pin.
When SOC2 = 0, SENS output is performed as usual. See " 1-4. Description of SENS Signals".
When SOC2 = 1, the SQSO pin signal is output from the SENS pin.
At this time, the readout clock is input to the SCLK pin.
Note) SOC2 should be switched when SQCK = SCLK = high.
Command bit
SOC2 = 0
SOC2 = 1
The SENS signal is output from the SENS pin as usual.
The SQSO pin signal is output from the SENS pin.
Processing
Command bit
MCSL = 1
MCSL = 0
DF/DAC block master clock is selected. Crystal = 768Fs (33.8688MHz)
DF/DAC block master clock is selected. Crystal = 384Fs (16.9344MHz)
Processing
Note) See " 4-9. DAC Block Playback Speed".
51
CXD3021R
Command
Data 3
Audio CTRL
DCOF
FMUT
BSBST
BBSL
D3
D2
D1
D0
Command bit
DCOF = 1
DCOF = 0
DC offset is off.
DC offset is on.
Processing
Command bit
FMUT = 1
FMUT = 0
Forced mute is on.
Forced mute is off.
Processing
Command bit
BSBST = 1
BSBST = 0
Bass boost on.
Bass boost off.
Processing
Command bit
BBSL = 1
BBSL = 0
Bass boost MAX.
Bass boost MID.
Processing
Set DC offset to off when zero detection mute is on.
$AX commands contin.
52
CXD3021R
$BX commands
This command sets the traverse monitor count.
Command
Data 1
Data 2
Data 3
Data 4
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
Traverse monitor count
setting
When the set number of tracks are counted during fine search, the sled control for the traverse cycle control
goes off.
The traverse monitor count is set to monitor the traverse status from the SENS output as COMP and COUT.
Data 4
D3
ATTCH
SEL
ATD10 ATD9 ATD8 ATD7 ATD6 ATD5 ATD4 ATD3 ATD2 ATD1 ATD0
Audio CTRL
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
Data 5
Data 6
Attenuation data
400H
3FFH
3FEH
:
001H
000H
0dB
0.0085dB
0.017dB
:
60.206dB
Audio output
The attenuation data consists of 11 bits each for the left and right channels; the DAC ATT bit can be used to
control the left and right channels with common attenuation data. When common attenuation data is specified,
the attenuation values for the left channel are used.
The audio output, from 001H to 400H, is determined
according to the following equation:
Audio output = 20log
[dB]
Command bit
ATTCH SEL = 1
ATTCH SEL = 0
Right channel attenuation data can be set.
Left channel attenuation data can be set.
Processing
Command bit
ATD10 to 0
Attenuation data
Meaning
Attenuation data
1024
Command
$AX commands contin.
53
CXD3021R
Spindle servo
coefficient setting
CLV CTRL ($DX)
Gain
MDP1
Gain
MDP0
Gain
MDS1
Gain
MDS0
Gain
CLVS
Gain
MDS1
0
0
0
0
1
1
Gain
MDS0
0
0
1
1
0
0
Gain
CLVS
0
1
0
1
0
1
GCLVS
12dB
6dB
6dB
0dB
0dB
+6dB
Command
D3
Data 1
D2
D1
D0
Gain
DCLV0
Gain
DCLV1
PCC1 PCC0
D3
Data 2
Description
Valid only when DCLV = 1.
Valid when DCLV = 1 or 0.
D2
D1
D0
$CX commands
The spindle servo gain is externally set when DCLV = 1
CLVS mode gain setting: GCLVS
Note) When DCLV = 0, the CLVS gain is as follows.
When Gain CLVS = 0, GCLVS = 12dB.
When Gain CLVS = 1, GCLVS = 0dB.
Gain
MDP1
0
0
1
Gain
MDP0
0
1
0
GMDP
6dB
0dB
+6dB
Gain
DCLV1
0
0
1
Gain
DCLV0
0
1
0
GDCLV
0dB
+6dB
+12dB
Gain
MDS1
0
0
1
Gain
MDS0
0
1
0
GMDS
6dB
0dB
+6dB
CLVP mode gain setting: GMDP : GMDS
DCLV overall gain setting: GDCLV
Command bit
PCC1
PCC0
Processing
The VPCO1 and 2 signals are output.
The VPCO1 and 2 pin outputs are high impedance.
The VPCO1 and 2 pin outputs are low.
The VPCO1 and 2 pin outputs are high.
0
0
1
1
0
1
0
1
These command bits controls the VPCO1 and VPCO2 pin signals.
Identical control can be performed for both VPCO1 and VPCO2 outputs with this setting. However, VPCO2 can
also be set to high impedance with the $E command FCSW separately from this setting.
54
CXD3021R
Command bit
FCSW
PCC1
PCC0
Processing
The VPCO1 pin signal is output and the VPCO2 pin is high impedance.
The VPCO1 and 2 pin outputs are high impedance.
The VPCO1 pin output is low and the VPCO2 pin is high impedance.
The VPCO1 pin output is high and the VPCO2 pin is high impedance.
The VPCO1 and 2 signals are output.
The VPCO1 and 2 pin outputs are high impedance.
The VPCO1 and 2 pin outputs are low.
The VPCO1 and 2 pin outputs are high.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
$CX commands contin.
Processing for the $CX commands PCC1 and PCC0 and the $EX command FCSW is shown below.
Command
Data 3
D3
SFP3 SFP2 SFP1 SFP0 SRP3 SRP2 SRP1 SRP0
Spindle servo
coefficient setting
D2
D1
D0
D3
D2
D1
D0
Data 4
See " 4-2. Frame Sync Protection" regarding frame sync protection.
Command bit
SRP3 to 0
Sets the frame sync backward protection times. The setting range is 1 to F (Hex).
Processing
Command bit
SFP3 to 0
Sets the frame sync forward protection times. The setting range is 1 to F (Hex).
Processing
55
CXD3021R
$CX commands contin.
The CXD3021R can serially output the 40 bits (10 BCD codes) of error rate data selected by EDC0 to 7 from
the SQSO pin and monitor this data using a microcomputer.
In order to output error rate data, set $C commands for C1 and C2 individually, and set SOCT0 and SOCT1
= 0 of $8 command. Then, the data can be read out from the SQSO pin by sending 40 SQCK pulses.
See Timing Chart 2-6.
Command bit
EDC7 = 0 EDC6
EDC5
EDC4
EDC3
EDC2
EDC1
EDC0
EDC7 = 1 EDC6
EDC5
EDC4
EDC3
EDC2
EDC1
EDC0
The [No C1 errors, pointer set] count is output when 1.
The [One C1 error corrected, pointer reset] count is output when 1.
The [No C1 errors, pointer set] count is output when 1.
The [One C1 error corrected, pointer set] count is output when 1.
The [Two C1 errors corrected, pointer set] count is output when 1.
The [C1 correction impossible, pointer set] count is output when 1.
7350-frame count cycle mode
1
when 0.
73500-frame count cycle mode
2
when 1.
The [No C2 errors, pointer reset] count is output when 1.
The [One C2 error corrected, pointer reset] count is output when 1.
The [Two C2 errors corrected, pointer reset] count is output when 1.
The [Three C2 errors corrected, pointer reset] count is output when 1.
The [Four C2 errors corrected, pointer reset] count is output when 1.
The [C2 correction impossible, pointer copy] count is output when 1.
The [C2 correction impossible, pointer set] count is output when 1.
Processing
Error rate monitor commands
1
The number selected by C1 (EDC1 to 6) and C2 (EDC0 to 6) is added to C1 and C2 and output every 7350
frames.
2
The number selected by C1 (EDC1 to 6) and C2 (EDC0 to 6) is added to C1 and C2 and output every
73500 frames.
Command
Data 5
D3
EDC7 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0
Spindle servo
coefficient setting
D2
D1
D0
D3
D2
D1
D0
Data 6
56
CXD3021R
$DX commands
See "$CX commands".
Command bit
DCLV PWM MD = 1
DCLV PWM MD = 0
Digital CLV PWM mode specified. Both MDS and MDP are used.
CLV-W and CAV-W modes cannot be used.
Digital CLV PWM mode specified. Ternary MDP values are output.
CLV-W and CAV-W modes can be used.
Description
Command bit
TB = 0
TB = 1
TP = 0
TP = 1
Bottom hold at a cycle of RFCK/32 in CLVS and CLVH modes.
Bottom hold at a cycle of RFCK/16 in CLVS and CLVH modes.
Peak hold at a cycle of RFCK/4 in CLVS mode.
Peak hold at a cycle of RFCK/2 in CLVS mode.
Description
Command
Data 1
CLV CTRL
DCLV
PWM MD
TB
TP
Gain
CLVS
D3
D2
D1
D0
57
CXD3021R
The rotational velocity R of the spindle can be expressed with the following equation.
R =
l
R: Relative velocity at normal speed = 1
n: VP0 to 7 setting value
1: Multiple set by VPCTL0, 1
256 n
32
The above setting should be 0, 0 except for the CAV-W operating mode.
Command bit
VPCTL1
VPCTL0
Processing
The setting of VP0 to 7 is multiplied by 1.
The setting of VP0 to 7 is multiplied by 2.
The setting of VP0 to 7 is multiplied by 3.
The setting of VP0 to 7 is multiplied by 4.
0
0
1
1
0
1
0
1
Command
Data 2
CLV CTRL
VP7
VP6
VP5
VP4
D3
D2
D1
D0
Data 3
VP3
VP2
VP1
VP0
D3
D2
D1
D0
Data 4
VP
CTL1
VP
CTL0
0
0
D3
D2
D1
D0
Command bit
Processing
VP0 to 7
The spindle rotational velocity is set.
$DX commands contin.
58
CXD3021R
Command bit
VP0 to 7 = F0 (Hex)
VP0 to 7 = E0 (Hex)
VP0 to 7 = C0 (Hex)
VP0 to 7 = A0 (Hex)
VP0 to 7 = 80 (Hex)
VP0 to 7 = 60 (Hex)
VP0 to 7 = 40 (Hex)
VP0 to 7 = 20
(
Hex)
VP0 to 7 = 00 (Hex)
Playback at 1/2 (1, 2)
speed
Playback at 1 (2, 4)
speed
Playback at 2 (4, 8)
speed
Playback at 3 (6, 12)
speed
Playback at 4 (8, 16)
speed
Playback at 5 (10, 20)
speed
Playback at 6 (12, 24)
speed
Playback at 7 (14, 28)
speed
Playback at 8 (16, 32)
speed
Description
Notes) 1. Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTSL is high.
2. Regarding the values in parentheses, the former ones are for when DSPB is 1 and VPCTL0, 1 = 0,
and the latter ones are for when DSPB is 1, VPCTL0 = 1 and VPCTL1 = 0.
........................
........................
$DX commands contin.
59
CXD3021R
E0
C0
A0
80
2
4
6
8
R
R
e
l
a
t
i
v
e
v
e
l
o
c
i
t
y
[
M
u
l
t
i
p
l
e
]
VP0 to 7 setting value [H]
60
40
10
12
20
00
14
16
DSPB = 1
DSPB0 = 0
When VPCTL0 = VPCTL1 = 0
E0
C0
A0
80
4
8
12
16
R
R
e
l
a
t
i
v
e
v
e
l
o
c
i
t
y
[
M
u
l
t
i
p
l
e
]
VP0 to 7 setting value [H]
60
40
20
24
20
00
28
32
DSPB = 1
DSPB = 0
When VPCTL0 = 1, VPCTL1 = 0
$DX commands contin.
60
CXD3021R
$EX commands
Command
Data 1
SPD mode
CM3
CM2
CM1
CM0
D3
D2
D1
D0
Data 2
EPWM SPDC
ICAP
SFSL
D3
D2
D1
D0
Data 3
VC2C
HIFC
LPWR VPON
D3
D2
D1
D0
Command bit
CM3
CM2
CM1
Description
Spindle stop mode.
1
Spindle forward rotation mode.
1
Spindle reverse rotation mode. Valid only when LPWR = 0
in any mode.
1
Rough servo mode. When the RF-PLL circuit isn't locked,
this mode is used to pull the disc rotations within the RF-
PLL capture range.
PLL servo mode.
Automatic CLVS/CLVP switching mode.
Used for normal playback.
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
1
1
CM0
0
0
0
0
1
0
Mode
STOP
KICK
BRAKE
CLVS
CLVP
CLVA
1
See Timing Charts 1-6 to 1-12.
Command bit
EPWM SPDC ICAP
Description
Crystal reference CLV servo.
Used for playback in CLV-W
mode.
2
Spindle control with VP0 to 7.
Spindle control with the external
PWM.
VCO control
3
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
SFSL
0
0
0
0
0
VC2C
0
1
0
0
0
HIFC
0
1
1
1
1
LPWR
0
0
0
0
0
VPON
0
0
1
1
1
INV
VPCO
0
0
0
0
1
Mode
CLV-N
CLV-W
CAV-W
CAV-W
VCO-C
2
Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode.
3
Fig. 3-3 shows the control flow with the microcomputer software in VCO-C mode.
61
CXD3021R
Mode
DCLV
DCLV PWM MD
LPWR
Command
Timing chart
CLV-N
CLV-W
CAV-W
0
1
1
1
0
0
1
0
0
0
0
0
0
1
0
1
KICK
BRAKE
STOP
KICK
BRAKE
STOP
KICK
BRAKE
STOP
KICK
BRAKE
STOP
KICK
BRAKE
STOP
KICK
BRAKE
STOP
KICK
BRAKE
STOP
1-6 (a)
1-6 (b)
1-6 (c)
1-7 (a)
1-7 (b)
1-7 (c)
1-8 (a)
1-8 (b)
1-8 (c)
1-9 (a)
1-9 (b)
1-9 (c)
1-10 (a)
1-10 (b)
1-10 (c)
1-11 (a)
1-11 (b)
1-11 (c)
1-12 (a)
1-12 (b)
1-12 (c)
Mode
DCLV
DCLV PWM MD
LPWR
Timing chart
CLV-N
CLV-W
CAV-W
1
1
1
0
1
0
0
0
0
0
1
0
1
0
1
1-13
1-14
1-15
1-16
1-17 (EPWM = 0)
1-18 (EPWM = 0)
1-19 (EPWM = 1)
1-20 (EPWM = 1)
Note) CLV-W and CAV-W modes support control only by the ternary output of the MDP pin.
Therefore, set DCLV to 1 and DCLV PWM MD to 0 in CLV-W and CAV-W modes.
$EX commands contin.
62
CXD3021R
Command bit
FCSW = 0
FCSW = 1
The VPCO2 pin is not used and it is high impedance.
The VPCO2 pin is used and the pin signal is the same as VPCO1.
Processing
Command
SPD mode
Data 4
This sets the gain when controlling the spindle with VP7 to 0 in
CAV-W mode.
Note) Gain CAV1, 0 commands are invalid for spindle control
with the external PWM.
D3
D2
D1
D0
Gain
CAV1
Gain
CAV0
FCSW
INV
VPCO
Gain
CAV1
0
0
1
1
Gain
CAV0
0
1
0
1
Gain
0dB
6dB
12dB
18dB
$EX commands contin.
63
CXD3021R
Timing Chart 1-3
R
c
h
1
6
-
b
i
t
C
2
P
o
i
n
t
e
r
L
c
h
1
6
-
b
i
t
C
2
P
o
i
n
t
e
r
I
f
C
2
P
o
i
n
t
e
r
=
1
,
d
a
t
a
i
s
N
G
C
2
P
o
i
n
t
e
r
f
o
r
u
p
p
e
r
8
b
i
t
s
C
2
P
o
i
n
t
e
r
f
o
r
l
o
w
e
r
8
b
i
t
s
R
c
h
C
2
P
o
i
n
t
e
r
C
2
P
o
i
n
t
e
r
f
o
r
u
p
p
e
r
8
b
i
t
s
C
2
P
o
i
n
t
e
r
f
o
r
l
o
w
e
r
8
b
i
t
s
L
c
h
C
2
P
o
i
n
t
e
r
L
R
C
K
W
D
C
K
C
D
R
O
M
=
0
C
2
P
O
C
D
R
O
M
=
1
C
2
P
O
4
8
b
i
t
s
l
o
t
64
CXD3021R
Timing Chart 1-4
L
e
v
e
l
M
e
t
e
r
T
i
m
i
n
g
9
6
c
l
o
c
k
p
u
l
s
e
s
W
F
C
K
1
2
3
9
6
c
l
o
c
k
p
u
l
s
e
s
C
R
C
F
C
R
C
F
1
2
3
P
e
a
k
d
a
t
a
o
f
t
h
i
s
s
e
c
t
i
o
n
1
6
b
i
t
s
R
/
L
L
/
R
9
6
-
b
i
t
d
a
t
a
H
o
l
d
s
e
c
t
i
o
n
1
2
3
8
0
8
1
9
6
C
R
C
F
S
Q
C
K
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
1
3
D
1
4
L
/
R
P
e
a
k
d
a
t
a
L
/
R
f
l
a
g
S
u
b
Q
D
a
t
a
S
e
e
"
S
u
b
C
o
d
e
I
n
t
e
r
f
a
c
e
"
1
5
-
b
i
t
p
e
a
k
-
d
a
t
a
A
b
s
o
l
u
t
e
v
a
l
u
e
d
i
s
p
l
a
y
,
L
S
B
f
i
r
s
t
7
5
0
n
s
t
o
1
2
0
s
S
Q
C
K
S
Q
S
O
S
Q
S
O
65
CXD3021R
Timing Chart 1-5
M
e
a
s
u
r
e
m
e
n
t
P
e
a
k
M
e
t
e
r
T
i
m
i
n
g
9
6
c
l
o
c
k
p
u
l
s
e
s
C
R
C
F
W
F
C
K
1
2
3
M
e
a
s
u
r
e
m
e
n
t
M
e
a
s
u
r
e
m
e
n
t
9
6
c
l
o
c
k
p
u
l
s
e
s
C
R
C
F
C
R
C
F
1
2
3
S
Q
C
K
66
CXD3021R
Timing Chart 1-6
CLV-N mode DCLV = DCLV PWM MD = LPWR = 0
Z
KICK
MDS
MDP
H
FSW
L
MON
H
(a) KICK
Z
BRAKE
MDS
MDP
FSW
L
MON
H
(b) BRAKE
Z
STOP
MDS
MDP
FSW
L
MON
(c) STOP
L
L
L
Timing Chart 1-7
CLV-N mode DCLV = 1, DCLV PWM MD = LPWR = 0
Z
KICK
MDS
MDP
H
FSW
L
MON
H
(a) KICK
Z
BRAKE
MDS
MDP
FSW
L
MON
H
(b) BRAKE
Z
STOP
MDS
MDP
FSW
L
MON
(c) STOP
Z
L
Z
L
Z
67
CXD3021R
Timing Chart 1-8
CLV-N mode DCLV = DCLV PWM MD = 1, LPWR = 0
KICK
MDS
MDP
H
FSW
L
MON
H
(a) KICK
BRAKE
MDS
MDP
FSW
L
MON
H
(b) BRAKE
STOP
MDS
MDP
FSW
L
MON
(c) STOP
L
L
H
L
L
L
H
Timing Chart 1-9
CLV-W mode (when following the spindle rotational velocity) DCLV = 1, DCLV PWM MD = LPWR = 0
Z
KICK
MDS
MDP
H
FSW
L
MON
H
(a) KICK
Z
BRAKE
MDS
MDP
FSW
L
MON
H
(b) BRAKE
Z
STOP
MDS
MDP
FSW
L
MON
(c) STOP
Z
L
Z
Other than when following the velocity,
the timing is the same as Timing Chart 1-6 (a).
L
Z
Other than when following the velocity,
the timing is the same as Timing Chart 1-6 (b).
68
CXD3021R
Timing Chart 1-10
CLV-W mode (when following the spindle rotational velocity) DCLV = 1, DCLV PWM MD = 0, LPWR = 1
Z
KICK
MDS
MDP
H
FSW
L
MON
H
(a) KICK
Z
BRAKE
MDS
MDP
FSW
L
MON
H
(b) BRAKE
Z
Z
STOP
MDS
MDP
FSW
L
MON
(c) STOP
Z
L
Z
Other than when following the velocity,
the timing is the same as Timing Chart 1-6 (a).
Timing Chart 1-11
CAV-W mode DCLV = 1, DCLV PWM MD = LPWR = 0
Z
KICK
MDS
MDP
H
FSW
L
MON
H
(a) KICK
Z
BRAKE
MDS
MDP
FSW
L
MON
H
(b) BRAKE
Z
STOP
MDS
MDP
FSW
L
MON
(c) STOP
Z
L
H
69
CXD3021R
Timing Chart 1-12
CAV-W mode DCLV = 1, DCLV PWM MD = 0, LPWR = 1
Z
KICK
MDS
MDP
H
FSW
L
MON
H
(a) KICK
Z
BRAKE
MDS
MDP
FSW
L
MON
H
(b) BRAKE
Z
Z
STOP
MDS
MDP
FSW
L
MON
(c) STOP
Z
H
Timing Chart 1-13
CLV-N mode DCLV PWM MD = LPWR = 0
Z
MDS
MDP
Acceleration
Z
Deceleration
132kHz
7.6s
n
236 (ns) n = 0 to 31
Timing Chart 1-14
CLV-N mode DCLV PWM MD = 1, LPWR = 0
MDS
MDP
Acceleration
Deceleration
132kHz
7.6s
n
236 (ns) n = 0 to 31
Output Waveforms with DCLV = 1
70
CXD3021R
Timing Chart 1-15
CLV-W mode DCLV PWM MD = LPWR = 0
Z
MDS
MDP
Acceleration
Z
Deceleration
264kHz
3.8s
Output Waveforms with DCLV = 1
Timing Chart 1-16
CLV-W mode DCLV PWM MD = 0, LPWR = 1
Z
MDS
MDP
Acceleration
Z
264kHz
3.8s
Output Waveforms with DCLV = 1
The BRAKE pulse is maked when LPWR = 1.
Timing Chart 1-17
CAV-W mode EPWM = DCLV PWM MD = LPWR = 0
MDP
Acceleration
Z
Deceleration
264kHz
3.8s
Timing Chart 1-18
CAV-W mode EPWM = DCLV PWM MD = 0, LPWR=1
MDP
Acceleration
Z
264kHz
3.8s
The BRAKE pulse is maked when LPWR = 1.
71
CXD3021R
Timing Chart 1-19
CAV-W mode EPWM = 1, DCLV PWM MD = LPWR = 0
PWMI
MDP
H
L
H
L
Acceleration
Deceleration
Timing Chart 1-20
CAV-W mode EPWM = 1, DCLV PWM MD = 0, LPWR = 1
PWMI
MDP
H
L
H
Z
Acceleration
The BRAKE pulse is masked when LPWR = 1.
Note)
CLV-W and CAV-W modes support control only by the ternary output of the MDP pin.
Therefore, set DCLV PWM MD to 0 in CLV-W and CAV-W modes.
72
CXD3021R
[2] Subcode Interface
There are two methods for reading out a subcode externally.
The 8-bit subcodes P to W can be read out from SBSO by inputting EXCK.
Sub-Q can be read out after checking CRC of the 80 bits in the subcode frame.
Sub-Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes
correctly and CRCF is high.
2-1. P to W Subcode Readout
Data can be read out by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.)
2-2. 80-bit Sub-Q Readout
Fig. 2-2 shows the peripheral block of the 80-bit Sub-Q register.
First, Sub-Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check
circuit.
96-bit Sub-Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are
loaded into the parallel/serial register.
When SQSO goes high after SCOR is output, the CPU determines that new data (which passed the CRC
check) has been loaded.
When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result,
although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.
Once the 80-bit data load is confirmed, SQCK is input so that the data can be read.
The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low.
The retriggerable monostable multivibrator has a time constant from 270 to 400s. When the duration when
SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval,
the serial/parallel register is not loaded into the parallel/serial register.
While the monostable multivibrator is being reset, data cannot be loaded in the peak detection parallel/serial
register or the 80-bit parallel/serial register.
In other words, while reading out with a clock cycle shorter than this time constant, the register will not be
rewritten by CRCOK and others.
The previously mentioned peak detection register can be connected to the shift-in of the 80-bit parallel/serial
register.
For ring control 1, input and output are shorted during peak meter and level meter modes.
For ring control 2, input and output are shorted during peak meter mode.
This is because the register is reset with each readout in level meter mode, and to prevent readout
destruction in peak meter mode.
As a result, the 96-bit clock must be input in peak meter mode.
The absolute time after peak is stored in the memory in peak meter mode. (See Timing Chart 2-3.)
The high and low intervals for SQCK should be between 750ns and 120s.
73
CXD3021R
Timing Chart 2-1
Internal
PLL clock
4.3218
MHz
WFCK
SCOR
EXCK
SBSO
750ns max
S0 S1
Q
R
WFCK
SCOR
EXCK
SBSO
S0
S1 Q
R S T U
V W S0
S1
P1
Q R S T
U V W
P1
P2
P3
Same
Same
Subcode P.Q.R.S.T.U.V.W Read Timing
74
CXD3021R
Block Diagram 2-2
8
8
8
8
8
8
8
8
8
O
r
d
e
r
I
n
v
e
r
s
i
o
n
1
6
P
e
a
k
d
e
t
e
c
t
i
o
n
L
O
A
D
C
O
N
T
R
O
L
R
i
n
g
c
o
n
t
r
o
l
2
C
R
C
F
M
i
x
M
o
n
o
s
t
a
b
l
e
m
u
l
t
i
v
i
b
r
a
t
o
r
C
R
C
C
A
B
S
t
i
m
e
l
o
a
d
c
o
n
t
r
o
l
f
o
r
p
e
a
k
v
a
l
u
e
1
6
-
b
i
t
P
/
S
r
e
g
i
s
t
e
r
R
i
n
g
c
o
n
t
r
o
l
1
S
O
S
I
S
Q
S
O
S
Q
C
K
S
H
I
F
T
S
H
I
F
T
SUBQ
LD
LD
LD
LD
LD
LD
LD
LD
S
O
H
G
F
E
D
C
B
A
A
B
C
D
E
F
G
H
S
I
8
0
-
b
i
t
P
/
S
R
e
g
i
s
t
e
r
8
0
-
b
i
t
S
/
P
R
e
g
i
s
t
e
r
(
A
F
R
A
M
)
(
A
S
E
C
)
(
A
M
I
N
)
A
D
D
R
S
C
T
R
L
S
I
N
S
U
B
Q
75
CXD3021R
Timing Chart 2-3
1
2
3
9
1
9
2
9
3
9
4
9
5
9
6
9
7
9
8
W
F
C
K
S
C
O
R
S
Q
S
O
S
Q
C
K
C
R
C
F
1
D
e
t
e
r
m
i
n
e
d
b
y
m
o
d
e
C
R
C
F
2
8
0
o
r
9
6
C
l
o
c
k
s
R
e
g
i
s
t
e
r
l
o
a
d
f
o
r
b
i
d
d
e
r
2
7
0
t
o
4
0
0
s
w
h
e
n
S
Q
C
K
=
h
i
g
h
.
7
5
0
n
s
t
o
1
2
0
s
3
0
0
n
s
m
a
x
C
R
C
F
A
D
R
0
A
D
R
1
A
D
R
2
A
D
R
3
C
T
L
0
C
T
L
1
C
T
L
2
C
T
L
3
S
Q
C
K
S
Q
S
O
1
2
3
C
R
C
F
1
M
o
n
o
s
t
a
b
l
e
M
u
l
t
i
v
i
b
r
a
t
o
r
(
I
n
t
e
r
n
a
l
)
76
CXD3021R
Timing Chart 2-4
E
x
a
m
p
l
e
:
$
8
0
2
0
0
0
l
a
t
c
h
S
e
t
S
Q
C
K
h
i
g
h
d
u
r
i
n
g
t
h
i
s
i
n
t
e
r
v
a
l
.
I
n
t
e
r
n
a
l
s
i
g
n
a
l
l
a
t
c
h
P
E
R
0
P
E
R
1
P
E
R
2
P
E
R
3
P
E
R
4
P
E
R
5
P
E
R
6
P
E
R
7
C
1
F
0
C
1
F
1
C
1
F
2
C
2
F
0
C
2
F
1
C
2
F
2
F
O
K
G
F
S
L
O
C
K
E
M
P
H
7
5
0
n
s
o
r
m
o
r
e
X
L
A
T
S
Q
C
K
S
Q
S
O
A
L
O
C
K
V
F
0
V
F
1
V
F
2
V
F
3
V
F
4
V
F
5
V
F
6
V
F
9
V
F
7
V
F
8
Signal
PER0 to 7
FOK
GFS
LOCK
EMPH
ALOCK
VF0 to 9
RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB.
Focus OK.
High when the frame sync and the insertion protection timing match.
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin ou
tputs low.
High when the playback disc has emphasis.
GFS is sampled at 460Hz; when GFS is high eight consecutive samples, this pin outputs a high signal. If GFS is low eight consec
utive
samples, this pin outputs low.
Used in CAV-W mode. The result obtained by measuring the rotational velocity of the disc. (See Timing Chart 2-5.) VF0 = LSB, VF
9 = MSB.
Description
C1F2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No C1 errors; C1 pointer reset
One C1 error corrected; C1 pointer reset
--
--
No C1 errors; C1 pointer set
One C1 error corrected; C1 pointer set
Two C1 errors corrected; C1 pointer set
C1 correction impossible; C1 pointer set
C1F1
C1F0
Description
C2F2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No C2 errors; C2 pointer reset
One C2 error corrected; C2 pointer reset
Two C2 errors corrected; C2 pointer reset
Three C2 errors corrected; C2 pointer reset
Four C2 errors corrected; C2 pointer reset
--
C2 correction impossible; C1 pointer copy
C2 correction impossible; C2 pointer set
C2F1
C2F0
Description
77
CXD3021R
Timing Chart 2-5
Measurement interval (approximately 3.8s)
Reference window
(132.2kHz)
Measurement pulse
(V16M/2)
Measurement counter
VF0 to 9
Load
m
The relative velocity of the disc can be obtained with the following equation.
R =
(R: Relative velocity, m: Measurement results)
VF0 to 9 is the result obtained by counting VCKI/2 pulses while the reference signal (132.2kHz) generated
from XTAL (XTLI, XTLO) (384Fs) is high. This value is 31 when the disc is rotating at normal speed and 63
when it is rotating at double speed (when DSPB is low).
(m + 1)
32
78
CXD3021R
Timing Chart 2-6
1
8
1
7
C
1
M
S
B
1
9
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
0
5
3
7
0
0
5
3
7
0
C
1
e
r
r
o
r
r
a
t
e
C
2
e
r
r
o
r
r
a
t
e
X
L
A
T
S
Q
C
K
S
Q
S
O
79
CXD3021R
[3] Description of Modes
This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations
for each mode are described below.
3-1. CLV-N Mode
This mode is compatible with the CXD2510Q, and operation is the same as for conventional control (however,
variable pitch cannot be used). The PLL capture range is 150kHz.
3-2. CLV-W Mode
This is the wide capture range mode. This mode allows the PLL to follow the rotational velocity of the disc. This
rotational following control has two types: using the built-in VCO2 or providing an external VCO. The spindle is
the same CLV servo as for the conventional series. Operation using the built-in VCO2 is described below.
(When using an external VCO, input the signal from the VPCO pin to the low-pass filter, use the output from
the low-pass filter as the control voltage for the external VCO, and input the oscillation output from the VCO to
the VCKI pin.)
When starting to rotate the disc and/or speeding up to the lock range from the condition where the disc is
stopped, CAV-W mode should be used. Specifically, first send $E665X to set CAV-W mode and kick the disc,
then send $E60CX to set CLV-W mode if ALOCK is high, which can be read out serially from the SQSO pin.
CLV-W mode can be used while ALOCK is high. The microcomputer monitors the serial data output, and must
return the operation to the speed adjusting state (CAV-W mode) when ALOCK becomes low. The control flow
according to the microcomputer software in CLV-W mode is shown in Fig. 3-2.
In CLV-W mode (normal), low power consumption is achieved by setting LPWR to high. Control was formerly
performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is set
high, deceleration pulses are not output, thereby achieving low power consumption mode.
CLV-W mode supports control only by the ternary output of the MDP pin. Therefore, when using CLV-W mode,
set DCLV PWM MD to low.
Note) The capture range for this mode is theoretically up to the signal processing limit.
3-3. CAV-W Mode
This is CAV mode. In this mode, the external clock is fixed and it is possible to control the spindle to the
desired rotational velocity. The rotational velocity is determined by the VP0 to VP7 setting values or the
external PWM. When controlling the spindle with VP0 to VP7, setting CAV-W mode with the $E665X command
and controlling VP0 to VP7 with the $DX commands allows the rotational velocity to be varied from low speed
to 32
speed. (See "$DX commands".) When controlling the spindle with the external PWM, CAV-W mode is
set with the $E6A5X command. Then, the PWMI pin is binary input which becomes KICK during high intervals
and BRAKE during low intervals.
The microcomputer can know the rotational velocity using V16M. The reference for the velocity measurement
is a signal of 132.3kHz obtained by 1/128-frequency dividing the crystal (XTLI, XTLO) (384Fs). The velocity is
obtained by counting the half of V16M pulses while the reference is high, and the result is output from the new
CPU interface as 10 bits (VF0 to 9). These measurement results are 31 when the disc is rotating at normal
speed or 127 when it is rotating at quadruple speed. These values match those of the 256 - n for control with
VP0 to VP7. (See Table 2-5 and Fig. 2-6.)
In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire
system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and all other
output signals from this LSI change according to the rotational velocity of the disc.
Note) The capture range for this mode is theoretically up to the signal processing limit.
Note) Set FLFC to 1 for this mode.
80
CXD3021R
3-4. VCO-C Mode
This is VCO control mode. In this mode, the V16M oscillation frequency can be controlled by setting $D
commands VP0 to VP7 and VPCTL0, 1. The V16M oscillation frequency can be expressed by the following
equation.
n: VP0 to VP7 setting value
1: VPCTL0, 1 setting value
The VCO1 oscillation frequency is determined by V16M. The VCO1 frequency can be expressed by the
following equation.
When DSPB = 0
When DSPB = 1
1 (256 n)
V16M =
32
49
VCO1 = V16M
24
49
VCO1 = V16M
16
81
CXD3021R
CAV-W
CLVS
CLV-W
CLVP
Rotational velocity
Target speed
Operation mode
Spindle mode
Time
KICK
LOCK
ALOCK
Fig. 3-1. Disc Stop to Regular Playback in CLV-W Mode
CLV-W Mode
NO
YES
KICK $E8000
Mute OFF $A00XXXX
ALOCK = H ?
NO
YES
ALOCK = L ?
CLV-W MODE
START
CAV-W $E665X
(CLVA)
CLV-W $E6C00
(CLVA)
(WFCK PLL)
Fig. 3-2. CLV-W Mode Flow Chart
82
CXD3021R
VCO-C Mode
R?
(How many minutes
of absolute time?)
Access START
Transfer
$E00510
n?
(Calculate n)
Transfer
$DX
XX
Track Jump
Subroutine
Transfer
$E66500
Access END
What is the playback speed when access ends?
Calculate VP0 to VP7.
Switch to VCO control mode.
EPWM = SPDC = ICAP = SFSL = VC2C = LPWR = 0
HIFC = VPON = 1
Transfer VP0 to VP7. (
corresponds to VP0 to VP7.)
Switch to normal-speed playback mode.
EPWM = SFSL = VC2C = LPWR = 0
SPDC = ICAP = HIFC = VPON = 1
Fig. 3-3. Access Flow Chart Using VCO Control
83
CXD3021R
[4] Description of Other Functions
4-1. Channel Clock Recovery by Digital PLL Circuit
The channel clock is necessary for demodulating the EFM signal regenerated by the optical system.
Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T.
In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that
is the channel clock, is necessary.
In an actual player, a PLL is necessary to recover the channel clock because the fluctuation in the spindle
rotation alters the width of the EFM signal pulses.
The block diagram of this PLL is shown in Fig. 4-1.
The CXD3021R has a built-in three-stage PLL.
The first-stage PLL is a wide-band PLL. When using the internal VCO2, an external LPF is necessary; when
not using the internal VCO2, external LPF and VCO are necessary.
The output of first-stage PLL is used as a reference for all clocks within the LSI.
The second-stage PLL generates the high-frequency clock needed by the third-stage digital PLL.
The third-stage PLL is a digital PLL that recovers the actual channel clock.
The digital PLL in CLV-N mode has a secondary loop, and is controlled by the primary loop (phase) and the
secondary loop (frequency). When FLFC = 1, the secondary loop can be turned off. High frequency
components such as 3T and 4T may contain deviations. In such cases, turning the secondary loop off yields
better playability. However, in this case the capture range becomes
50kHz.
A new digital PLL has been provided for CLV-W mode to follow the rotational velocity of the disc in addition
to the conventional secondary loop.
84
CXD3021R
Block Diagram 4-1
XTSL
1/2
1/32
1/n
1/2
Microcomputer
control
n = 1 to 256
(VP7 to VP0)
1/K
(KSL1, 0)
CLV-W
CAV-W
Spindle rotation information
CLV-N
CLV-W
CAV-W
/CLV-N
P
h
a
s
e
c
o
m
p
a
r
a
t
o
r
S
e
l
e
c
t
o
r
LPF
2/1 MUX
VPON
1/M
1/N
VCOSEL2
VCO2
P
h
a
s
e
c
o
m
p
a
r
a
t
o
r
VCO1
VCOSEL1
1/K
(KSL3, 2)
Digital PLL
RFPLL
VPCO1, 2
VCTL
V16M
VCKI
PCO
FILI
FILO
CLTV
XTLI
Clock input
1/l
l = 1, 2, 3, 4
(VPCTL0, 1)
85
CXD3021R
4-2. Frame sync protection
In normal-speed playback, a frame sync is recorded approximately every 136s (7.35kHz). This signal is
used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be
recognized, the data is processed as error data because the data cannot be recognized. As a result,
recognizing the frame sync properly is extremely important for improving playability.
In the CXD3021R, window protection and forward protection/backward protection have been adopted for
frame sync protection. These functions achieve very powerful frame sync protection. There are two window
widths; one for cases where a rotational disturbance affects the player and the other for cases where there is
no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is set to 12
, and the
backward protection counter to 3
. Concretely, when the frame sync is being played back normally and then
cannot be detected due to scratches, a maximum of 12 frames are inserted. If the frame sync cannot be
detected for 13 frames or more, the window opens to resynchronize the frame sync.
In addition, immediately after the window opens and the resynchronization is executed, if a proper frame
sync cannot be detected within 3 frames, the window opens immediately.
Default values. These values can be set as desired by $C commands SFP0 to 3 and SRP0 to 3.
4-3. Error Correction
In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code
is created with 28-byte information and 4-byte C1 parity.
For C2 correction, the code is created with 24-byte information and 4-byte parity.
Both C1 and C2 are Reed Solomon codes with a minimum distance of 5.
The CXD3021R uses refined super strategy to achieve double correction for C1 and quadruple correction for C2.
In addition, to prevent C2 miscorrection, a C1 pointer is attached to data after C1 correction according to the
C1 error status, the playback status of the EFM signal, and the operating status of the player.
The correction status can be monitored externally.
See Table 4-2.
When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an
average value interpolation was made for the data.
MNT3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
No C1 errors;
C1 pointer reset
One C1 error corrected;
C1 pointer reset
--
--
No C1 errors;
C1 pointer set
One C1 error corrected;
C1 pointer set
Two C1 errors corrected;
C1 pointer set
C1 correction impossible;
C1 pointer set
No C2 errors;
C2 pointer reset
One C2 error corrected;
C2 pointer reset
Two C2 errors corrected;
C2 pointer reset
Three C2 errors corrected;
C2 pointer reset
Four C2 errors corrected;
C2 pointer reset
--
C2 correction impossible;
C1 pointer copy
C2 correction impossible;
C2 pointer set
MNT2
MNT1
MNT0
Description
Table 4-2.
86
CXD3021R
Timing Chart 4-3
Normal-speed PB
400 to 500ns
RFCK
MNT3
MNT1
MNT0
t = Dependent on error
condition
C1 correction
C2 correction
Strobe
Strobe
MNT2
4-4. DA Interface Output
The CXD3021R has two DA interface output modes.
1)
48-bit slot interface
This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first.
When LRCK is high, the data is for the left channel.
2-a) 64-bit slot interface
This interface includes 64 cycles of the bit clock within one LRCK cycle, and is LSB first.
When LRCK is low, the data is for the left channel.
2-b) 32-bit slot interface
This interface includes 32 cycles of the bit clock within one LRCK cycle, and is LSB first.
When LRCK is low, the data is for the left channel.
Note) The 32-bit and 64-bit slot outputs can not be output simultaneously because the common pin is used by
switching with the command. (SLSB of $9X command)
87
CXD3021R
Timing Chart 4-4
L
R
C
K
(
4
4
.
1
K
)
D
A
1
5
(
2
.
1
2
M
)
W
D
C
K
D
A
1
6
L
R
C
K
(
8
8
.
2
K
)
D
A
1
5
(
4
.
2
3
M
)
W
D
C
K
D
A
1
6
4
8
-
b
i
t
S
l
o
t
N
o
r
m
a
l
-
S
p
e
e
d
P
l
a
y
b
a
c
k
P
S
S
L
=
L
1
2
4
R
0
L
c
h
M
S
B
(
1
5
)
L
1
4
L
1
3
L
1
2
L
1
1
L
1
0
L
9
L
8
L
7
L
6
L
5
L
4
L
3
L
2
L
1
L
0
R
c
h
M
S
B
L
c
h
M
S
B
(
1
5
)
2
4
R
c
h
M
S
B
2
3
4
5
6
7
8
9
1
0
1
1
1
2
4
8
-
b
i
t
S
l
o
t
D
o
u
b
l
e
-
S
p
e
e
d
P
l
a
y
b
a
c
k
1
2
L
0
R
0
88
CXD3021R
Timing Chart 4-5
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
R
1
5
L
c
h
L
S
B
(
0
)
R
c
h
L
S
B
(
0
)
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
2
0
3
0
3
2
3
1
D
A
1
2
(
4
4
.
1
K
)
D
A
1
3
(
2
.
8
2
M
)
D
A
1
4
1
L
c
h
L
S
B
1
2
3
4
5
1
0
1
5
2
5
D
A
1
2
(
8
8
.
2
K
)
D
A
1
3
(
5
.
6
4
M
)
D
A
1
4
2
0
3
0
3
1
3
2
R
c
h
L
S
B
(
0
)
2
3
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
4
L
1
5
6
4
-
b
i
t
S
l
o
t
D
o
u
b
l
e
-
S
p
e
e
d
P
l
a
y
b
a
c
k
6
4
-
b
i
t
S
l
o
t
N
o
r
m
a
l
-
S
p
e
e
d
P
l
a
y
b
a
c
k
P
S
S
L
=
L
89
CXD3021R
Timing Chart 4-6
1
L
R
C
K
(
4
4
.
1
K
)
D
A
1
3
(
2
.
1
2
M
)
D
A
1
4
3
2
-
b
i
t
S
l
o
t
N
o
r
m
a
l
-
S
p
e
e
d
P
l
a
y
b
a
c
k
L
R
C
K
(
8
8
.
2
K
)
D
A
1
3
(
4
.
2
3
M
)
D
A
1
4
3
2
-
b
i
t
S
l
o
t
D
o
u
b
l
e
-
S
p
e
e
d
P
l
a
y
b
a
c
k
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
R
0
L
1
5
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
1
0
R
1
1
R
1
2
R
1
3
R
1
4
R
1
5
L
0
1
5
1
0
1
5
1
6
R
0
L
1
5
R
2
R
1
R
4
R
3
R
6
R
5
R
8
R
7
R
1
0
R
9
R
1
2
R
1
1
R
1
4
R
1
3
L
0
R
1
5
L
2
L
1
L
3
90
CXD3021R
4-5. Digital Out
There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use,
and the type 2 form 2 format for the manufacture of software.
The CXD3021R supports type 2 form 1.
This LSI supports 2 kinds of Digital Out generation methods; one is to generate the Digital Out using the PCM
data read out from the disc and the other is to generate it using the DA interface input (PCMDI, LRCKI and
BCKI).
4-5-1. Digital Out From PCM Data
The Digital Out is generated from the PCM data which is read out from the disc.
The clock accuracy of the channel status is automatically set to level II when the crystal clock is used and to
level III in CAV-W mode. In addition, the Sub-Q data matched twice continuously with CRC check are input to
the initial 4 bits (bits 0 to 3).
DOUT is output when the crystal is 34MHz and XTSL is high in CLV-N or CLV-W mode with DSPB = 1.
Therefore, DOUT is set to off by making the MD2 pin to 0.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1
0
0
0
ID0
ID1 COPY Emph
0
0
0
0
1
0
0
0
0
0
0
0
From sub Q
0
16
32
48
176
Sub-Q control bits that matched twice with CRCOK
Digital Out C bit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VPON: 1 X'tal: 0
bits 0 to 3
bit 29
Table 4-6-1.
91
CXD3021R
4-5-2. Digital Out From DA Interface Input
The Digital Out is generated from the DA interface.
Validity Flag and User Data
The Validity Flag and User Data are fixed to 0.
Channel Status Data
For the Channel Status Data, bits 0, 6 and 7 are fixed to 0. The following items can be set by bits 1, 2, 3 and 8.
a) Digital data/audio data
b) Digital copy enabled/ prohibited
c) With/without pre-emphasis
d) Category code (two types possible)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A/D
SEL
COPY
En
EMPH
D
0
0
0
0
CAT
b8
0
0
0
0
0
0
0
0
16
32
48
176
Digital Out C bit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Table 4-6-2.
Note) In this method, DOUT can be set to off by making the MD pin to 0 and $34A command DOUT EN to 0.
92
CXD3021R
Digital Audio Data Input
The input signal of the digital audio data is input from the DAC input pins PCMDI, LRCKI and BCKI. The input
format supports 48-bit slot/MSB first.
Mute Function
By setting the command bit DOUT_DMUT to 1, all the audio data portions in the Digital Out output can be
made to 0 with the Channel Status Data as it is.
Input/Output Synchronization Circuit
In the normal operation, the DAC automatically synchronizes with the input LRCK. However, when the input
data has much jitter or the power is turned on the synchronization may not be achieved. In such a case, the
internal operation should be forcibly synchronized by setting $34A DOUT WOD to 1. Also, the forcible
synchronization is required when the operating frequency is changed such as switching between CLV and
CAV, etc. Be sure to set DOUT WOD to 0 before performing forcible synchronization again.
When the synchronization is performed, the internal counter which counts the frames is cleared so that the
frame is started from 0 after the synchronization processed. In case where the automatic processing of the
synchronization is not desirable or the user wants to do it manually, set the command $34A WIN EN to 0 to
invalidate the automatic synchronization circuit.
Clock System of DOUT Circuit
For the DOUT block, the master clock is set using the clock control command MCSL ($A) employed by the
DAC block. Set MCSL to 1 for 768fs and to 0 for 384fs.
93
CXD3021R
L
0
L
1
L
2
L
3
L
4
L
5
L
6
L
7
L
8
L
9
L
1
0
L
1
1
L
1
2
L
1
3
L
1
4
L
1
5
R
0
1
2
3
4
5
6
7
8
9
1
0
1
7
1
8
L
1
L
2
L
3
L
4
L
5
L
6
L
7
L
8
L
9
L
1
0
L
1
1
L
1
2
L
1
3
L
1
4
L
1
5
R
c
h
L
S
B
(
0
)
L
c
h
L
S
B
(
0
)
1
2
3
4
5
6
7
8
9
1
0
R
c
h
M
S
B
(
1
5
)
L
c
h
M
S
B
(
1
5
)
L
1
3
L
1
2
L
1
1
L
1
0
L
9
L
8
L
7
L
6
L
5
L
4
L
3
L
2
L
1
L
0
L
1
4
P
C
M
D
I
B
C
K
I
(
3
)
4
8
-
b
i
t
S
l
o
t
M
S
B
f
i
r
s
t
P
C
M
D
I
B
C
K
I
(
2
)
6
4
-
b
i
t
S
l
o
t
L
S
B
f
i
r
s
t
P
C
M
D
I
B
C
K
I
(
1
)
3
2
-
b
i
t
S
l
o
t
L
S
B
f
i
r
s
t
L
R
C
K
I
(
4
4
.
1
k
)
DOUT Block Input Timing Chart
94
CXD3021R
4-6. Servo Auto Sequence
This function performs a series of controls, including auto focus and track jumps. When the auto sequence
command is received from the CPU, auto focus, 1-track jump, 2N-track jump, fine search and M-track move
are executed automatically.
The servo block operates according to the built-in program during the auto sequence execution (when
XBUSY = low), so that does not accept commands from the CPU, that is $0, 1 and 2 commands. ($3 to E
commands are accepted.)
In addition, when using the auto sequence, turn the A.SEQ of register 9 on.
When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of
100s after that point. This is to prevent the transfer of erroneous data to the servo when XBUSY changes
from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low).
In addition, a MAX timer is built into this LSI as a countermeasure against abnormal operation due to
external disturbances, etc. When the auto sequence command is sent from the CPU, this command
assumes a $4XY format, in which X specifies the command and Y sets the MAX timer value and timer
range. If the executed auto sequence command does not terminate within the set timer value, the auto
sequence is interrupted (like $40). See [1] "$4X commands" concerning the timer value and range. Also, the
MAX timer is invalidated by inputting $4X0.
Although this command is explained in the format of $4X in the following command descriptions, the timer
value and timer range are actually sent together from the CPU.
(a) Auto focus ($47)
Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on.
If $47 is received from the CPU, the focus servo is turned on according to Fig. 4-8. The auto focus starts
with focus search-up, and note that the pickup should be lowered beforehand (focus search-down). In
addition, blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on
at the falling edge of FZC after FZC has been continuously high for a longer time than E.
(b) Track jump
1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled
servos are on. Note that tracking gain-up and braking-on ($17) should be sent beforehand because they
are not involved in this sequence.
1-track jump
When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in
accordance with Fig. 4-9. Set blind A and brake B with register 5.
10-track jump
When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in
accordance with Fig. 4-10. The principal difference from the 1-track jump is to kick the sled. In addition,
after kicking the actuator, when 5 tracks have been counted through COUT, the brake is applied to the
actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT
cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on.
95
CXD3021R
2N-track jump
When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in
accordance with Fig. 4-11. The track jump count N is set with register 7. Although N can be set to 2
16
tracks, note that the setting is actually limited by the actuator. COUT is used for counting the number of
jumps when N is less than 16, and MIRR is used when N is 16 or more.
Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is
that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6.
Fine search
When $44 ($45 for REV) is received from the CPU, a FWD (REV) fine search (N-track jump) is performed
in accordance with Fig. 4-12. The differences from a 2N-track jump are that a higher precision is achieved
by controlling the traverse speed, and a longer distance jump is achieved by controlling the sled. The track
jump count is set with register 7. N can be set to 2
16
tracks. After kicking the actuator and sled, the traverse
speed is controlled based on the overflow G. Set kick D and F with register 6 and overflow G with register 5.
Also, sled speed control during traverse can be turned off by causing COMP to fall. Set the number of
tracks during which COMP falls with register B. After N tracks have been counted through COUT, the brake
is applied to the actuator and sled. (This is performed by turning on the tracking servo for the actuator, and
by kicking the sled in the opposite direction during the time for kick D set with register 6.) Then, the tracking
and sled servos are turned on.
Set overflow G to the speed required to slow up just before the track jump terminates. (The speed should
be such that it will come on-track when the tracking servo turns on at the termination of the track jump.) For
example, set the target track count N
for the traverse monitor counter which is set with register B, and
COMP will be monitored. When the falling edge of this COMP is detected, overflow G can be set again.
M-track move
When $4E ($4F for REV) is received from the CPU, a FWD (REV) M-track move is performed in
accordance with Fig. 4-13. M can be set to 2
16
tracks. Like the 2N-track jump, COUT is used for counting
the number of moves when M is less than 16, and MIRR is used when M is 16 or more. The M-track move
is executed by moving only the sled, and is therefore suited for moving across several thousand to several
ten-thousand tracks. In addition, the track and sled servos are turned off after M tracks have been counted
through COUT or MIRR unlike for the other jumps. Transfer $25 from the microcomputer after the actuator
has stabilized.
96
CXD3021R
Auto focus
Focus search up
FOK = H
NO
YES
FZC = H
NO
YES
FZC = L
NO
YES
END
Focus servo ON
Check whether FZC is
continuously high for
the period of time E set
with register 5.
Fig. 4-8-(a). Auto Focus Flow Chart
XLAT
$47 Latch
$03
Blind E
$08
FOK
FZC
BUSY
Command for
SSP
Fig. 4-8-(b). Auto Focus Timing Chart
97
CXD3021R
1 Track
NO
YES
END
Track FWD kick
sled servo OFF
WAIT
(Blind A)
COUT =
Track REV
kick
WAIT
(Brake B)
Track, sled
servo ON
(FWD kick for REV jump)
(REV kick for REV jump)
Fig. 4-9-(a). 1-Track Jump Flow Chart
$48 (REV = $49) Latch
$28 ($2C)
Blind A
Brake B
$2C ($28)
$25
XLAT
COUT
BUSY
Command for
SSP
Fig. 4-9-(b). 1-Track Jump Timing Chart
98
CXD3021R
10 Track
NO
YES
END
Track, sled
FWD kick
WAIT
(Blind A)
COUT = 5 ?
Track, REV
kick
Track, sled
servo ON
Checks whether the
COUT cycle is longer
than overflow C.
(Counts COUT
5)
NO
YES
C = Overflow ?
Fig. 4-10-(a). 10-Track Jump Flow Chart
COUT
$4A (REV = $4B) Latch
Blind A
$2A ($2F)
COUT 5 count
$2E ($2B)
Overflow C
$25
XLAT
BUSY
Command for
SSP
Fig. 4-10-(b). 10-Track Jump Timing Chart
99
CXD3021R
2N Track
NO
YES
END
Track, sled
FWD kick
WAIT
(Blind A)
COUT (MIRR) = N
Track REV
kick
Track servo
ON
NO
YES
C = Overflow
WAIT
(Kick D)
Sled servo
ON
Counts COUT for the first 16 times
and MIRR for more times.
Fig. 4-11-(a). 2N-Track Jump Flow Chart
XLAT
Blind A
$2A ($2F)
COUT (MIRR)
N count
$2E ($2B)
Overflow C
Kick D
$26 ($27)
$25
$4C (REV = $4D) Latch
COUT
(MIRR)
BUSY
Command
for SSP
Fig. 4-11-(b). 2N-Track Jump Timing Chart
100
CXD3021R
Track Servo ON
Sled FWD Kick
Fine Search
WAIT
(Kick D)
Track Sled
FWD Kick
WAIT
(Kick F)
Traverse
Speed Ctrl
(Overflow G)
COUT = N?
Track Servo ON
Sled REV Kick
WAIT
(Kick D)
Track Sled
Servo ON
END
YES
NO
Fig. 4-12-(a). Fine Search Flow Chart
Traverse Speed Control (Overflow G)
&
COUT N count
Kick F
Kick D
$26 ($27)
$2A ($2F)
$27 ($26)
$25
$44 (REV = $45) latch
XLAT
COUT
Kick D
BUSY
Fig. 4-12-(b). Fine Search Timing Chart
101
CXD3021R
M Track Move
NO
YES
END
Track Servo OFF
Sled FWD Kick
WAIT
(Blind A)
COUT (MIRR) = M
Track, Sled
Servo OFF
Counts COUT for M
<
16.
Counts MIRR for M
16.
Fig. 4-13-(a). M-Track Move Flow Chart
XLAT
Blind A
$22 ($23)
COUT (MIRR)
M count
$20
$4E (REV = $4F) Latch
COUT
(MIRR)
BUSY
Command for
servo
Fig. 4-13-(b). M-Track Move Timing Chart
102
CXD3021R
4-7. Digital CLV
Fig. 4-14 shows the block diagram. Digital CLV outputs MDS error and MDP error signals with PWM, with the
sampling frequency increased up to 130kHz during normal-speed playback in CLVS, CLVP and other modes.
In addition, the digital spindle servo gain is variable.
MDP
Digital CLV
CLVS U/D
MDS Error
MDP Error
CLV P/S
Measure
Measure
2/1 MUX
Oversampling
Filter-1
Gain
MDS
1/2
Mux
CLV P/S
Oversampling
Filter-2
Noise Shape
Modulation
KICK, BRAKE, STOP
MDS
Mode Select
Gain
DCLV
Gain
MDP
DCLVMD, LPWR
PWMI
Fig. 4-14. Block Diagram
CLVS U/D:
Up/down signal from CLVS servo
MDS error:
Frequency error for CLVP servo
MDP error:
Phase error for CLVP servo
PWMI:
Spindle drive signal from the microcomputer for CAV servo
103
CXD3021R
4-8. Playback Speed
In the CXD3021R, the following playback modes can be selected through different combinations of XTLI,
XTSL pin, double-speed command (DSPB), VCO1 selection command (VCOSEL1), VCO1 frequency
division commands (KSL3, KSL2) and command transfer rate selector (ASHS) in CLV-N or CLV-W mode.
Mode
1
2
3
4
5
6
7
XTLI
768Fs
768Fs
768Fs
768Fs
384Fs
384Fs
384Fs
XTSL
1
1
0
0
0
0
1
DSPB
0
1
0
1
0
1
1
VCOSEL1
1
0/1
0/1
1
1
0/1
0/1
0/1
ASHS
0
0
1
1
0
0
0
Playback
speed
1
2
2
4
1
2
1
Error correction
C1: double; C2: quadruple
C1: double; C2: double
C1: double; C2: quadruple
C1: double; C2: double
C1: double; C2: quadruple
C1: double; C2: double
C1: double; C2: double
1
Actually, the optimal value should be used together with KSL3 and KSL2.
The playback speed can be varied by setting VP0 to VP7 in CAV-W mode. See "[3] Description of Modes" for
details.
104
CXD3021R
4-9. DAC Block Playback Speed
The operating speed of the DAC block is determined by the crystal and the $AX command MCSL regardless of
the operating conditions of the CD-DSP block. This allows the DAC block and DSP block playback modes to
be set independently.
Crystal
768Fs
768Fs
384Fs
1
2
1
1
0
0
DAC block playback speed
1-bit DAC block playback speed
MCSL
4-10. DAC Block Input Timing
The DAC input timing chart is shown below.
Audio data is not transferred from the CD signal processor block to the DAC block inside the CXD3021R. This
enables to send data to the DAC block via the external audio DSP, etc.
When the data is input to the DAC block without using the audio DSP, the data must be connected outside the
LSI. In this case, LRCK, BCK and PCMD can be connected directly with LRCKI, BCKI and PCMDI. (See the
Application Circuit.)
L15
Invalid
L14 L13 L12
L11 L10
L9
L8
L7
L6
L5
L4
L3
L2
L1
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
L0
LRCKI
(44.1k)
BCKI
(2.12M)
PCMDI
Fs = 44.1kHz
Nomal-speed Playback
105
CXD3021R
Description of DAC Block Functions
Zero data detection
When the condition where the lower 4 bits of the input data are DC and the remaining upper bits are all "0" or
all "1" has continued for about 300ms (16384/44.1kHz), zero data is detected. Zero data detection is
performed independently for the left and right channels.
Mute flag output
The LMUTO and RMUTO pins go active when any one of the following conditions is met.
The polarity can be selected by the $9X command ZDPL.
When zero data is detected
When the $9X commands DAC SMUTL and DAC SMUTR are set (The flags change independently for the
left and right channels.)
The mute flag output at initializing is as shown below. (This is in the case the zero data is input from LRCKI,
BCKI, PCMDI and the time address $9X command ZDPL and address $AX command MCSL stay in the
initial values.)
A
Y1
B
Y3
C
Y2
23.2 [ms]
000(H)
0dB
400(H)
XRST
LMUTO
RMUTO
Approx. 370ms when crystal = 16.9344MHz
Approx. 185ms when crystal = 33.8688MHz
Attenuation operation
Assuming the attenuation commands X1, X2 and X3, the corresponding audio outputs are Y1, Y2 and Y3 (Y1
> Y3 > Y2). First, the command X1 is sent and then the audio output approaches Y1. When the command
X2 is sent before the audio output reaches Y1 (A in the figure), the audio output passes Y1 and approaches
Y2. And, when the command X3 is sent before the audio output rteaches Y2 (B or C in the figure), the audio
output approaches Y3 from the value (B or C in the figure) at that point.
106
CXD3021R
DAC block mute operation
Soft mute
Soft mute results and the input data is attenuated to zero when any one of the following conditions is met.
When attenuation data of 000 (Hex) is set
When the $9X commands DAC SMUTL and DAC SMUTR are set to 1
Forced mute
Forced mute results when the $AX command FMUT is set to 1.
Forced mute fixes the PWM output. (Low for left channel, high for right channel)
Zero detection mute
Setting $9X command ZMUT to 1 enables forced mute when zero data is detected for both the left and right
channels. (See "Zero data detection".)
LRCK Synchronization
Synchronization is performed at the first rising edge of the LRCK input when reset.
After that, synchronization is lost when the LRCK input frequency changes, etc., so resynchronization must
be performed.
The LRCK input frequency changes when the master clock of the LSI is switched and the playback speed
changes such as the following cases.
When the XTSL pin switches between high and low
When the $9X command DSPB setting changes
When the $9X command MCSL setting changes
When operation switches between CLV mode and CAV mode
LRCK switching may also be performed if there are other ICs between the CD-DSP block and the DAC
block. Resynchronization must be performed in these cases as well.
For resynchronization, set the $9X command XWOC to 0 or the external pin XWO to low, wait for one
LRCK cycle or more, and then set XWOC to 1 and XWO to high.
When setting XWOC to 0 or the external pin XWO to low, be sure to set the $9X command SYCOF to 0
beforehand.
Soft mute on
Soft mute off
Soft mute off
23.2 [ms]
23.2 [ms]
0dB
dB
107
CXD3021R
Graph 4-15.
SYCOF
When LRCK, PCMD and BCK are connected directly with LRCKI, PCMDI and BCKI, respectively, playback
can be performed easily in CAV-W mode by setting SYCOF of address 9 to 1.
Normally, the memory proof, etc., is used for playback in CAV-W mode.
In CAV-W mode, the LRCK output conforms not to the crystal but to the VCO. Therefore, synchronization is
frequently lost.
Setting SYCOF of address 9 to 1 ignores the LRCKI's asynchronization, facilitating playback. However, the
playback is not perfect because pre-value hold or data skip occurs due to the wow and flutter in the LRCKI
input.
Set SYCOF to 0 other than when connecting LRCK, PCMD and BCK directly with LRCKI, PCMDI and
BCKI, respectively, and performing playback in CAV-W mode.
Digital Bass Boost
Bass boost without external parts is possible using the built-in digital filter. The boost strength has two levels:
MID and MAX.
The bass boost is set using BSBST and BBSL of address A.
See Graph 4-15 for the digital bass boost frequency response.
Normal
DBB MID
DBB MAX
10.00
4.00
6.00
4.00
2.00
0.00
2.00
8.00
6.00
8.00
10.00
12.00
14.00
10
30
100
300
1k
3k
10k
30k
Digital bass boost frequency response [Hz]
[
d
B
]
108
CXD3021R
4-11. Asymmetry Correction
Fig. 4-16 shows the block diagram and circuit example.
ASYE
RFAC
R1
R1
ASYO
ASYI
+
R1 2
R2 5
=
BIAS
R1
R1
R2
CXD3021R
+
Fig. 4-16. Asymmetry Correction Application Circuit
109
CXD3021R
4-12. Clock System
The DAC, digital signal processor and digital servo blocks can be switched to each playback mode according
to how the crystal and clock circuit are connected. Each circuit is as shown in the diagram below. During
normal use, the servo block clock is internally connected and the FSTIO pin is the monitor output pin. The
command ($8 FSTIN) is used to input the clock externally. In this time, the FSTIO pin serves as the input pin.
384fs or
768fs
XTLI
XTLO
OSC
To DAC block
To CD signal processor block
XTSL
MCKO
To exterior
FSTIO
FSTIN = 0: Output pin
(Preset)
FSTIN = 1: Input pin
To digital servo block
XT2D
XT4D
(Commands $3E, $3F)
1/2
1/2
1/4
XT1D
Selector
FSTIN (Command $8X.
"0" for preset;
internally connected)
2/3
110
CXD3021R
[5] Description of Servo Signal Processing System Functions and Commands
5-1. General Description of Servo Signal Processing System (V
DD
: Supply voltage)
Focus servo
Sampling rate:
88.2kHz (when MCK = 128Fs)
Input range:
1/4V
DD
to 3/4V
DD
Output format:
8-bit DAC
Other:
Offset cancel
Focus bias adjustment
Focus search
Gain-down
Defect countermeasure
Auto gain control
Tracking servo
Sampling rate:
88.2kHz (when MCK = 128Fs)
Input range:
1/4V
DD
to 3/4V
DD
Output format:
8-bit DAC
Other:
Offset cancel
E:F balance adjustment
Track jump
Gain-up
Defect countermeasure
Drive cancel
Auto gain control
Vibration countermeasure
Sled servo
Sampling rate:
345Hz (when MCK = 128Fs)
Input range:
1/4V
DD
to 3/4V
DD
Output format:
8-bit DAC
Other:
Sled move
FOK, MIRR, DFCT signal generation
RF signal sampling rate: 1.4MHz (when MCK = 128Fs)
Input range:
1/4V
DD
to 3/4V
DD
Other:
RF zero level automatic measurement
111
CXD3021R
5-2. Digital Servo Block Master Clock (MCK)
The FSTIO pin is the clock input/output pin for the servo block. At preset, the clock with 2/3 frequency of the
crystal is internally supplied to the servo block and the FSTIO pin serves as the monitor output pin for it. To
make this pin act as the input pin, set the command $8X command FSTIN to 1.
The master clock (MCK) is generated by dividing the frequency of the FSTIO pin. The frequency division ratio
is 1, 1/2 or 1/4.
Table 5-1 below assumes the preset status (where the clock with 2/3 frequency of the crystal is internally
supplied to the servo).
XT4D and XT2D are for the $3F command and XT1D is for the $3E command. (Default = 0)
The digital servo block is designed with an MCK frequency of 5.6448MHz (128Fs) as typical.
Mode
1
2
3
4
5
6
7
384Fs
384Fs
384Fs
768Fs
768Fs
768Fs
768Fs
256Fs
256Fs
256Fs
512Fs
512Fs
512Fs
512Fs
0
1
0
1
0
1
0
1
0
0
1
0
0
1
0
0
0
1
1/2
1/2
1
1/2
1/4
1/4
256Fs
128Fs
128Fs
512Fs
256Fs
128Fs
128Fs
XTLI
FSTO
XTSL
XT4D
XT2D
XT1D
Frequency division ratio
MCK
Fs = 44.1kHz,
: Don't care
Table 5-1.
112
CXD3021R
5-3. DC Offset Cancel [AVRG (Average) Measurement and Compensation] (See Fig. 5-3.)
The CXD3021R can measure the averages of RFDC, VC, FE and TE and compensate these signals using the
measurement results to control the servo effectively. This AVRG measurement and compensation is
necessary to initialize the CXD3021R, and is able to cancel the DC offset.
AVRG measurement takes the levels applied to the VC, FE, RFDC and TE pins as the digital average values
of 256 samples, and then loads these values into each AVRG register.
The AVRG measurement commands are VCLM, FLM, RFLM and TLM of $38.
Measurement is on when the respective command is set to 1.
AVRG measurement requires approximately 2.9ms to 5.8ms (when MCK = 128Fs) after the command is received.
The completion of AVRG measurement operation can be monitored by the SENS pin. (See Timing Chart 5-2.)
Monitoring requires that the upper 8 bits of the command register are 38 (H).
XLAT
SENS
(= XAVEBSY)
Max. 1s
AVRG measurement completed
2.9 to 5.8ms
Timing Chart 5-2.
<Measurement>
VC AVRG: The VC DC offset (VC AVRG) which is the center voltage for the system is measured and used to
compensate the FE, TE and SE signals.
FE AVRG: The FE DC offset (FE AVRG) is measured and used to compensate the FE and FZC signals.
TE AVRG: The TE DC offset (TE AVRG) is measured and used to compensate the TE and SE signals.
RF AVRG: The RF DC offset (RF AVRG) is measured and used to compensate the RFDC signal.
<Compensation>
RFLC:
(RF signal RF AVRG) is input to the RF In register.
"00" is input when the RF signal is lower than RF AVRG.
TLC0:
(TE signal VC AVRG) is input to the TRK In register.
TLC1:
(TE signal TE AVRG) is input to the TRK In register.
VCLC:
(FE signal VC AVRG) is input to the FCS In register.
FLC1:
(FE signal FE AVRG) is input to the FCS In register.
FLC0:
(FE signal FE AVRG) is input to the FZC register.
Two methods of canceling the DC offset are assumed for the CXD3021R. These methods are shown in Figs.
5-3a and 5-3b.
An example of AVRG measurement and compensation commands is shown below.
$38 08 00
(RF AVRG measurement)
$38 20 00
(FE AVRG measurement)
$38 00 10
(TE AVRG measurement)
$38 14 0A
(Compensation on [RFLC, FLC0, FLC1, TLC1], corresponds to Fig. 5-3a.)
See the description of $38 for these commands.
113
CXD3021R
5-4. E:F Balance Adjustment Function (See Fig. 5-3.)
When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search),
the traverse waveform appears in the TE signal due to disc eccentricity.
In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold
filter by setting D5 (TBLM) of $38 to 1.
The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC
register value is established when TBLM returns to 0.
Next, setting D2 (TLC2) of $38 to 1 compensates the values obtained from the TE and SE input pins with the
TRVSC register value (subtraction), allowing the E:F balance offset to be adjusted. (See Fig. 5-3.)
5-5. FCS Bias (Focus Bias) Adjustment Function
The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See
Fig. 5-3.)
When D11 = 0 and D10 = 1 is set by $34F, the FBIAS register value can be written using the 9-bit value of D9
to D1 (D9: MSB).
In addition, the RF jitter can be monitored by setting the $8 commands SOCT1, SOCT0. (See "DSP Block
Timing Chart".)
The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to 1. The FBIAS register functions
as an up counter when D12 (FBUP) of $3A = 1, and as a down counter when D12 (FBUP) of $3A = 0.
The number of up and down steps can be changed by setting D11 and D10 (FBV1 and FBV0) of $3A.
When using the FBIAS register as a counter, the counter stops when the value set beforehand in FBL9 to
FBL1 of $34 matches the FCSBIAS value. Also, if the upper 8 bits of the command register are $3A at this
time, SENS goes high and the counter stop can be monitored.
A
B
C
FBIAS setting value (FB9 to FB1)
LIMIT value (FBL9 to FBL1)
SENS pin
A: Register mode
B: Counter mode
C: Counter mode (when stopped)
Here, assume the FBIAS setting value FB9 to FB1
and the FBIAS LIMIT value FBL9 to FBL1 are set
in status A. For example, if command registers
FBUP = 0, FBV1 = 0, FBV0 = 0 and FBSS = 1 are
set from this status, down count starts from status
A and approaches the set LIMIT value. When the
LIMIT value is reached and the FCSBIAS value
matches FBL9 to FBL1, the counter stops and the
SENS pin goes high. Note that the up/down
counter counts at each sampling cycle of the focus
servo filter. The number of steps by which the
count value changes can be selected from 1, 2, 4
or 8 steps by FBV1 and FBV0. When converted to
FE input, 1 step corresponds to 1/512
V
DD
/2.
114
CXD3021R
Fig. 5-3a.
Fig. 5-3b.
TE AVRG
register
TLC1
TRVSC
register
TLC2
to TRK In register
TE from A/D
FE AVRG
register
FLC1
FBIAS
register
FBON
to FCS In register
FLC0
to FZC register
FE from A/D
RFLC
to RF In register
RFDC from A/D
RF AVRG
register
to SLD In register
SE from A/D
TLC1 TLD1
TLC2 TLD2
+
VC AVRG
register
TLC0
TRVSC
register
TLC2
to TRK In register
TE from A/D
FBIAS
register
FBON
to FCS In register
VCLC
to FZC register
FE from A/D
RFLC
to RF In register
RFDC from A/D
RF AVRG
register
to SLD In register
SE from A/D
TLC2 TLD2
+
FE AVRG
register
FLC0
TLC0 TLD0
115
CXD3021R
5-6. AGCNTL (Automatic Gain Control) Function
The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate servo loop
gain. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but also
obtains the optimal gain for each disc.
The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of
the command register are 38 (Hex), the completion of AGCNTL operation can be confirmed by monitoring the
SENS pin. (See Timing Chart 5-4 and "Description of SENS Signals".)
Setting D9 and D8 of $38 to 1 sets FCS (focus) and TRK (tracking) respectively to AGCNTL operation.
Note) During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described
hereafter) must be disabled.
XLAT
SENS
(= AGOK)
Max. 11.4s
AGCNTL completion
Timing Chart 5-4
Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 change for AGT (tracking
AGCNTL) due to AGCNTL.
These coefficients change from 01 to 7F (Hex), and they must also be set within this range when written
externally.
After AGCNTL operation has completed, these coefficient values can be confirmed by reading them out from
the SENS pin with the serial readout function (described hereafter).
AGCNTL related settings
The following settings can be changed with $35, $36 and $37.
FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (Hex)
TG6 to TG0; AGT convergence gain setting, effective setting range: 00 to 57 (Hex)
AGS;
Self-stop on/off
AGJ;
Convergence completion judgment time
AGGF;
Internally generated sine wave amplitude (AGF)
AGGT;
Internally generated sine wave amplitude (AGT)
AGV1;
AGCNTL sensitivity 1 (during rough adjustment)
AGV2;
AGCNTL sensitivity 2 (during fine adjustment)
AGHS;
Rough adjustment on/off
AGHT;
Fine adjustment time
Note) Converging servo loop gain values can be changed with the FG6 to FG0 and TG6 to TG0 setting values. In
addition, these setting values must be within the effective setting range. The default settings aim for 0dB at
1kHz. However, since convergence values vary according to the characteristics of each constituent
element of the servo loop, FG and TG values should be set as necessary.
116
CXD3021R
AGCNTL and default operation have two stages.
In the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select
256/128ms with AGHT, when MCK = 128Fs), and the AGCNTL coefficient approaches the appropriate value.
The sensitivity at this time can be selected from two types with AGV1.
In the second stage, the AGCNTL coefficient is finely adjusted with relatively low sensitivity to further approach
the appropriate value. The sensitivity for the second stage can be selected from two types with AGV2. In the
second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops
changing, the CXD3021R confirms that the AGCNTL coefficient has not changed for a certain period of time
(select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self-stop mode)
This self-stop mode can be canceled by setting AGS to 0.
In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0.
An example of AGCNTL coefficient transitions during AGCNTL operation with various settings is shown in Fig. 5-5.
Initial value
SENS
AGCNTL
start
AGCNTL
completion
Convergence value
AGCNTL coefficient value
Slope
AGV1
AGHT
AGJ
Slope
AGV2
Fig. 5-5.
Note) Fig. 5-5 shows the case where the AGCNTL coefficient converges from the initial value to a smaller
value.
117
CXD3021R
5-7. FCS Servo and FCS Search (Focus Search)
The FCS servo is controlled by the 8-bit serial command $0X. (See Table 5-6.)
Register
name
Command
D23 to D20
D19 to D16
1 0
1 1
0
0
0
1
0
1 0
0
1 1
FOCUS SERVO ON (FOCUS GAIN NORMAL)
FOCUS SERVO ON (FOCUS GAIN DOWN)
FOCUS SERVO OFF, 0V OUT
FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT
FOCUS SEARCH VOLTAGE DOWN
FOCUS SEARCH VOLTAGE UP
0 0 0 0
FOCUS
CONTROL
0
Table 5-6.
FCS Search
FCS search is required in the course of turning on the FCS servo.
Fig. 5-7 shows the signals for sending commands $00
$02
$03 and performing only FCS search operation.
Fig. 5-8 shows the signals for sending $08 (FCS on) after that.
FCSDRV
RF
FOK
FE
FZC
FZC comparator level
$00 $02
$03
0
0
FCSDRV
RF
FOK
FE
FZC
$00 $02
$03
0
$08
Fig. 5-7.
Fig. 5-8.
: Don't care
118
CXD3021R
5-8. TRK (Tracking) and SLD (Sled) Servo Control
The TRK and SLD servos are controlled by the 8-bit command $2X. (See Table 5-9.)
When the upper 4 bits of the serial data are 2 (Hex), TZC is output to the SENS pin.
Register
name
Command
D23 to D20
D19 to D16
TRACKING SERVO OFF
TRACKING SERVO ON
FORWARD TRACK JUMP
REVERSE TRACK JUMP
SLED SERVO OFF
SLED SERVO ON
FORWARD SLED MOVE
REVERSE SLED MOVE
0 0 1 0
TRACKING
MODE
2
Table 5-9.
TRK Servo
The TRK JUMP (track jump) level can be set with 6 bits (D13 to D8) of $36.
In addition, when the TRK servo is on and D17 of $1 is set to 1, the TRK servo filter switches to gain-up mode.
The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected with the
anti-shock circuit (described hereafter) enabled.
The CXD3021R has 2 types of gain-up filter structures in TRK gain-up mode which can be selected by setting
D16 of $1. (See Table 5-17.)
SLD Servo
The SLD MOV (sled move) output, composed of a basic value from 6 bits (D13 to D8) of $37, is determined by
multiplying this value by 1
, 2
, 3
, or 4
magnification set using D17 and D16 when D18 = D19 = 0 is set with
$3. (See Table 5-10.)
SLD MOV must be performed continuously for 50s or more. In addition, if the LOCK input signal goes low
when the SLD servo is on, the SLD servo turns off.
Note) When the LOCK signal is low, the TRK servo switches to gain-up mode and the SLD servo is turned off.
These operations are disabled by setting D6 (LKSW) of $38 to 1.
Register
name
Command
D23 to D20
D19 to D16
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
SLED KICK LEVEL (basic value
1)
SLED KICK LEVEL (basic value
2)
SLED KICK LEVEL (basic value
3)
SLED KICK LEVEL (basic value
4)
0 0 1 1
SELECT
3
Table 5-10.
: Don't care
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
119
CXD3021R
5-9. MIRR and DFCT Signal Generation
The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz (when MCK = 128Fs) and
loaded. The MIRR and DFCT signals are generated from this RF signal.
MIRR Signal Generation
The loaded RF signal is applied to peak hold and bottom hold circuits.
An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is
generated from the average of this envelope waveform.
The MIRR signal is generated by comparing the waveform generated by subtracting the bottom hold value
from the peak hold value with this MIRR comparator level. (See Fig. 5-11.)
The bottom hold speed and mirror sensitivity can be selected from 4 values using D7 and D6, and D5 and D4,
respectively, of $3C.
RF
Peak Hold
Bottom Hold
Peak Hold
Bottom Hold
MIRR
MIRR Comp
(Mirror comparator level)
H
L
RF
Peak Hold1
Peak Hold2
Peak Hold1
DFCT
(Defect comparator level)
H
L
SDF
Peak Hold2
Fig. 5-11.
DFCT Signal Generation
The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is
generated by comparing the difference between these two peak hold waveforms with the DFCT comparator
level. (See Fig. 5-12.)
The DFCT comparator level can be selected from four values using D13 and D12 of $3B.
Fig. 5-12.
120
CXD3021R
5-10. DFCT Countermeasure Circuit
The DFCT countermeasure circuit maintains the directionality of the servo so that the servo does not
become easily dislocated due to scratches or defects on discs.
Specifically, these operations are achieved by detecting scratches and defects with the DFCT signal
generation circuit, and when DFCT goes high, applying the low-frequency component of the error signal
before DFCT went high to the FCS and TRK servo filter inputs. (See Fig. 5-13.)
In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of
$38 to 1.
Input register
Hold register EN
Hold Filter
Servo Filter
Error signal
DFCT
Fig. 5-13.
5-11. Anti-Shock Circuit
When vibrations occur in the CD player, this circuit forces the TRK filter to switch to gain-up mode so that the
servo does not become easily dislocated. This circuit is for systems which require vibration countermeasures.
Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is
increased. (See Fig. 5-14.)
The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator
level is practically variable by adjusting the value of the anti-shock filter output coefficient K35.
This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See
Table 5-17.)
This circuit can also support an external vibration detection circuit, and can set the TRK servo filter to gain-up
mode by inputting high level to the ATSK pin.
When the upper 8 bits of the command register are $1, vibration detection can be monitored from the SENS pin.
TE
Anti Shock
Filter
TRK Gain Up
Filter
TRK Gain Normal
Filter
TRK DAC
ATSK
SENS
Comparator
Fig. 5-14.
121
CXD3021R
5-12. Brake Circuit
Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to
turn on.
The brake circuit prevents these phenomenon.
In principle, the brake circuit uses the tracking drive as a brake by cutting the unnecessary portions utilizing the
180 offset in the RF envelope and tracking error phase relationship which occurs when the actuator traverses
the track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 5-15 and 5-16.)
Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by
loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal.
The brake circuit can be turned on and off by D18 of $1. (See Fig. 5-17.)
In addition, the low frequency for the tracking drive after masking can be boosted. (SFBK1, 2 of $34B)
Inner track
Outer track
TRK
DRV
FWD
JMP
REV
JMP
Servo ON
RF
Trace
MIRR
TE
0
TZC
Edge
TRKCNCL
0
TRK DRV
(SFBK OFF)
SENS
TZC out
0
TRK DRV
(SFBK ON)
Outer track
Inner track
TRK
DRV
REV
JMP
FWD
JMP
Servo ON
RF
Trace
MIRR
TE
0
TZC
Edge
TRKCNCL
0
TRK DRV
(SFBK OFF)
SENS
TZC out
0
TRK DRV
(SFBK ON)
Fig. 5-15.
Fig. 5-16.
Register
name
Command
D23 to D20
D19 to D16
1 0
0
1
0
0
1
1
0
ANTI SHOCK ON
ANTI SHOCK OFF
BRAKE ON
BRAKE OFF
TRACKING GAIN NORMAL
TRACKING GAIN UP
TRACKING GAIN UP FILTER SELECT 1
TRACKING GAIN UP FILTER SELECT 2
0 0 0 1
TRACKING
CONTROL
1
Table 5-17.
: Don't care
122
CXD3021R
5-13. COUT Signal
The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by
loading the MIRR signal at both edges of the TZC signal. The used TZC signal can be selected from among
three different phases according to the COUT signal application.
HPTZC: For 1-track jumps
Fast phase COUT signal generation with a fast phase TZC signal. (The TZC phase is advanced
by a cut-off 1kHz digital HPF; when MCK = 128Fs.)
STZC:
For COUT generation when MIRR is externally input and for applications other than COUT generation.
This is generated by sampling the TE signal at 700kHz. (when MCK = 128Fs)
DTZC:
For high-speed traverse
Reliable COUT signal generation with a delayed phase STZC signal.
Since it takes some time to generate the MIRR signal, it is necessary to delay the TZC signal in accordance
with the MIRR signal delay during high-speed traverse.
The COUT signal output method is switched with D15 and D14 of $3C.
When D15 = 1:
STZC
When D15 = 0 and D14 = 0: HPTZC
When D15 = 0 and D14 = 1: DTZC
When DTZC is selected, the delay can be selected from two values with D14 of $36.
5-14. Serial Readout Circuit
The following measurement and adjustment results can be read out from the SENS pin by inputting the
readout clock to the SCLK pin by the serial command $39. (See Fig. 5-18, Table 5-19 and "Description of
SENS Signals".)
Specified commands
$390C: VC AVRG measurement result
$3953: FCS AGCNTL coefficient result
$3908: FE AVRG measurement result
$3963: TRK AGCNTL coefficient result
$3904: TE AVRG measurement result
$391C: TRVSC adjustment result
...
...
t
DLS
t
SPW
1/f
SCLK
MSB
LSB
XLAT
SCLK
Serial Readout Data
(SENS pin)
Item
Symbol
Min.
Typ.
Max.
Unit
SCLK frequency
SCLK pulse width
Delay time
f
SCLK
t
SPW
t
DLS
31.3
15
16
MHz
ns
s
Table 5-19.
During readout, the upper 8 bits of the command register must be 39 (H).
Fig. 5-18.
123
CXD3021R
5-15. Writing to Coefficient RAM
The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and
transfer from the ROM to the RAM is completed approximately 40s (when MCK = 128Fs) after the XRST pin
rises. (The coefficient RAM cannot be rewritten during this period.)
After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address
of the coefficient RAM.
The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and
D7 to D0 as the data. Coefficient rewriting is completed 11.3s (when MCK = 128Fs) after the command is
received. When rewriting multiple coefficients, be sure to wait 11.3s (when MCK = 128Fs) before sending the
next rewrite command.
124
CXD3021R
5-16. DAC Output
FCS, TRK and SLD DAC format outputs are described below.
See the "Servo Drive Analog Characteristics" of Electrical Characteristics for the output range.
In particular, FSC and TRK use a double oversampling noise shaper.
Timing Chart 5-22 and Fig. 5-23 show examples of output waveforms and drive circuits.
V
DD
64MCK
64MCK
64MCK
Output value +B
Output value B
Output value 0
B
256
V
DD
B
128
V
DD
32MCK
32MCK
32MCK
32MCK
32MCK
32MCK
B
256
V
DD
B
256
V
DD
B
256
V
DD
B
256
V
DD
0.9V
DD
0.5V
DD
0.1V
DD
0
0.9V
DD
V
DD
0.5V
DD
0.1V
DD
0
SAO
FAO/TAO
SLD
FCS/TRK
R
R
R
R
DRV
V
CC
V
DD
/2
AO
Timing Chart 5-22.
Fig. 5-23. Drive Circuit
125
CXD3021R
5-17. Servo Status Changes Produced by LOCK Signal
When the LOCK signal becomes low, the TRK servo switches to the gain-up mode and the SLD servo turns off
in order to prevent SLD free-running.
Setting D6 (LKSW) of $38 to 1 deactivates this function.
In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low.
This enables microcomputer control.
126
CXD3021R
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
KA6
KA5
KA4
KA3
KA2
KA1
KA0
KD7
KD6
KD5
KD4
KD3
KD2
KD1
KD0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
PGFS1 PGFS0 PFOK1 PFOK0
0
0
0
0
MRT2 MRT1
0
0
When D15 = 0.
KA6 to KA0: Coefficient address
KD7 to KD0: Coefficient data
5-18. Description of Commands and Data Sets
$34
$348 (preset: $348 000)
PGFS1
0
0
1
1
0
1
0
1
High when the frame sync is of the correct timing,
low when not the correct timing.
High when the frame sync is of the correct timing,
low when continuously not the correct timing for 2ms or longer.
High when the frame sync is of the correct timing,
low when continuously not the correct timing for 4ms or longer.
High when the frame sync is the correct timing,
low when continuously not the correct timing for 8ms or longer.
PGFS0
Processing
These commands set the GFS pin hold time. The hold time is inversely proportional to the playback speed.
PFOK1
0
0
1
1
0
1
0
1
High when the RFDC value is higher than the FOK slice level,
low when lower than the FOK slice level.
High when the RFDC value is higher than the FOK slice level,
low when continuously lower than the FOK slice level for 4.35ms or more.
High when the RFDC value is higher than the FOK slice level,
low when continuously lower than the FOK slice level for 10.16ms or more.
High when the RFDC value is higher than the FOK slice level,
low when continuously lower than the FOK slice level for 21.77ms or more.
PFOK0
Processing
These commands set the FOK hold time. See $3B for the FOK slice level.
These are the values when MCK = 128Fs, and the hold time is inversely proportional to the MCK setting.
MRT2
0
0
1
1
0
1
0
1
No time limit
1.1ms
2.2ms
4.0ms
MRT1
Time limit
These commands limit the time while Mirr = high. These are the values when MCK = 128Fs, and the time limit
is inversely proportional to the MCK setting.
127
CXD3021R
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
A/D
SEL
COPY
EN
EMPH
D
CAT
b8
DOUT
EN
DOUT
DMUT
DOUT
WOD
WIN
EN
DOUT
EN2
0
0
0
$34A (preset: $34A 150)
Command bit
A/DSEL = 0
A/DSEL = 1
Channel status data. Bit 1 is output as the audio data.
Channel status data. Bit 1 is output as the data other than the audio data.
Processing
Command bit
COPY EN = 0
COPY EN = 1
Channel status data. Bit 2 is output as the digital copy prohibited.
Channel status data. Bit 2 is output as the digital copy enabled.
Processing
Command bit
EMPH D = 0
EMPH D = 1
Channel status data. Bit 3 is output without pre-emphasis.
Channel status data. Bit 3 is output with pre-emphasis.
Processing
Command bit
CAT b8 = 0
CAT b8 = 1
Channel status data. Bit 8 is output as 0.
Channel status data. Bit 8 is output as 1.
Processing
: Preset
Command bit
DOUT EN = 0
DOUT EN = 1
DOUT signal, which is generated from PCM data read out from the disc, is output.
DOUT signal, which is generated from the DA interface input, is output.
Processing
Command bit
DOUT DMUT = 0
DOUT DMUT = 1
Digital Out output is normally output.
All the audio data portions are output in 0, with Digital Out output as it is.
Processing
Command bit
DOUT WOD = 0
DOUT WOD = 1
DOUT sync window is not open.
DOUT sync window is open.
Processing
128
CXD3021R
Command bit
WIN EN = 0
WIN EN = 1
The operation is invalidated, where the input LRCK is automatically synchronized
with the internal processing to match the phase.
The operation is validated, where the input LRCK is automatically synchronized with
the internal processing to match the phase.
Processing
Command bit
DOUT EN2 = 0
DOUT EN2 = 1
Digital Out is not generated from the DA interface input.
Digital Out is generated from the DA interface input.
Processing
Note) In order to generate Digital Out from the DA interface input, set DOUT EN to 1 and DOUT EN2 to 1.
: Preset
See the "Mute conditions" (1), (2) and (4) to (6) of $AX commands for the other mute conditions.
See $8X commands for DOUT Mute and D. out Mute F.
DOUT
EN
0
0
0
0
0
0
0
0
0
1
1
DOUT
DMUT
MD2 pin
Other mute
condition
DOUT
Mute
D. out
Mute F
DOUT output
OFF
0dB
The output from the PCM
data readout from a disc
dB
The output from the PCM
data readout from a disc
0dB
The output from the
DA interface input
dB
The output from the
DA interface input
--
--
--
--
--
--
--
--
--
0
1
0
1
1
1
1
1
1
1
1
--
--
--
0
0
0
0
1
1
1
1
--
--
--
0
0
1
1
0
0
1
1
--
--
--
0
1
0
1
0
1
0
1
--
--
--: don't care
$34A commands contin.
129
CXD3021R
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
1
SFBK1 SFBK2
0
0
0
0
0
0
0
0
0
0
$34B (preset: $34B 000)
The low frequency can be boosted for brake operation.
See 5-12 for brake operation.
SFBK1: When 1, brake operation is performed by setting the LowBooster-1 input to 0.
This is valid only when TLB1ON = 1. The preset is 0.
SFBK2: When 1, brake operation is performed by setting the LowBooster-2 input to 0.
This is valid only when TLB2ON = 1. The preset is 0.
130
CXD3021R
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
0
THB
ON
FHB
ON
TLB1
ON
FLB1
ON
TLB2
ON
0
HBST1 HBST0 LB1S1 LB1S0 LB2S1 LB2S0
$34C (preset: $34C 000)
These commands turn on the boost function. (See " 5-20. Filter Composition".)
There are five boosters (three for the TRK filter and two for the FCS filter) which can be turned on and off
independently.
THBON: When 1, the high frequency is boosted for the TRK filter. Preset is 0.
FHBON: When 1, the high frequency is boosted for the FCS filter. Preset is 0.
TLB1ON: When 1, the low frequency is boosted for the TRK filter. Preset is 0.
FLB1ON: When 1, the low frequency is boosted for the FCS filter. Preset is 0.
TLB2ON: When 1, the low frequency is boosted for the TRK filter. Preset is 0.
The difference between TLB1ON and TLB2ON is the position where the low frequency is boosted.
For TLB1ON, the low frequency is boosted before the TRK jump, and for TLB2ON, after the TRK jump.
Set SFJP ($36) to 1 or TAOZ ($34D) to 0 in order to boost the low frequency for the TRK jump operation.
The following commands set the boosters. (See " 5-20. Filter Composition".)
HBST1, HBST0: TRK and FCS HighBooster setting.
HighBooster has the configuration shown in Fig. 5-24a, and can select three different
combinations of coefficients BK1, BK2 and BK3. (See Table 5-25a.)
An example of characteristics is shown in Fig. 5-26a.
These characteristics are the same for both the TRK and FCS filters.
The sampling frequency is 88.2kHz (when MCK = 128Fs).
LB1S1, LB1S0: TRK and FCS LowBooster-1 setting.
LowBooster-1 has the configuration shown in Fig. 5-24b, and can select three different
combinations of coefficients BK4, BK5 and BK6. (See Table 5-25b.)
An example of characteristics is shown in Fig. 5-26b.
These characteristics are the same for both the TRK and FCS filters.
The sampling frequency is 88.2kHz (when MCK = 128Fs).
LB2S1, LB2S0: TRK LowBooster-2 setting.
LowBooster-2 has the configuration shown in Fig. 5-24c, and can select three different
combinations of coefficients BK7, BK8 and BK9. (See Table 5-25c.)
An example of characteristics is shown in Fig. 5-26c.
This booster is used exclusively for the TRK filter.
The sampling frequency is 88.2kHz (when MCK = 128Fs).
Set SFJP ($36) to 1 or TAOZ ($34D) to 0 in order to boost the low frequency for the TRK
jump operation.
Note) Fs = 44.1kHz
131
CXD3021R
BK2
Z
1
Z
1
BK1
BK3
HBST1
HBST0
0
1
1
--
0
1
HighBooster setting
120/128
124/128
126/128
96/128
112/128
120/128
BK1
BK2
2
2
2
BK3
Table 5-25a.
Fig. 5-24a.
BK5
Z
1
Z
1
BK4
BK6
Fig. 5-24b.
BK8
Z
1
Z
1
BK7
BK9
Fig. 5-24c.
LB1S1
LB1S0
0
1
1
--
0
1
LowBooster-1 setting
255/256
511/512
1023/1024
1023/1024
2047/2048
4095/4096
BK4
BK5
1/4
1/4
1/4
BK6
Table 5-25b.
LB2S1
LB2S0
0
1
1
--
0
1
LowBooster-2 setting
255/256
511/512
1023/1024
1023/1024
2047/2048
4095/4096
BK7
BK8
1/4
1/4
1/4
BK9
Table 5-25c.
132
CXD3021R
Fig. 5-26a. Servo HighBooster characteristics [FCS, TRK] (MCK = 128Fs)
HBST1 = 0
HBST1 = 1, HBST0 = 0
HBST1 = 1, HBST0 = 1
1
2
3
15
9
3
3
9
15
G
a
i
n
[
d
B
]
12
6
0
6
12
100
10
1
Frequency [Hz]
1k
10k
2
3
1
90
+90
P
h
a
s
e
[
d
e
g
r
e
e
]
72
36
0
+36
+72
100
10
1
Frequency [Hz]
1k
10k
2
3
1
133
CXD3021R
Fig. 5-26b. Servo LowBooster-1 characteristics [FCS, TRK] (MCK = 128Fs)
LB1S1 = 0
LB1S1 = 1, LB1S0 = 0
LB1S1 = 1, LB1S0 = 1
1
2
3
15
9
3
3
9
15
G
a
i
n
[
d
B
]
12
6
0
6
12
100
10
1
Frequency [Hz]
1k
10k
90
+90
P
h
a
s
e
[
d
e
g
r
e
e
]
72
36
0
+36
+72
100
10
1
Frequency [Hz]
1k
10k
2
2
3
1
1
3
134
CXD3021R
Fig. 5-26c. Servo LowBooster-2 characteristics [FCS, TRK] (MCK = 128Fs)
LB2S1 = 0
LB2S1 = 1, LB2S0 = 0
LB2S1 = 1, LB2S0 = 1
1
2
3
15
9
3
3
9
15
G
a
i
n
[
d
B
]
12
6
0
6
12
100
10
1
Frequency [Hz]
1k
10k
90
+90
P
h
a
s
e
[
d
e
g
r
e
e
]
72
36
0
+36
+72
100
10
1
Frequency [Hz]
1k
10k
2
1
3
2
3
1
135
CXD3021R
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
1
FAON TAON SAON
0
FAOZ TAOZ SAOZ
0
0
0
0
0
$34D (preset: $34D 000)
The servo drive is output. DAC format.
FAON: When 0, the FCS servo drive is muted. (default)
When 1, the FCS servo drive is output.
TAON: When 0, the TRK servo drive is muted. (default)
When 1, the TRK servo drive is output.
SAON: When 0, the SLD servo drive is muted. (default)
When 1, the SLD servo drive is output.
These commands select the drive DAC output when the servo is off. Center potential or high impedance can
be selected.
FAOZ:
When 0, the FCS drive DAC output is the center potential when the FCS servo is off. (default)
When 1, the FCS drive DAC output is high impedance when the FCS servo is off.
TAOZ:
When 0, the TRK drive DAC output is the center potential when the TRK servo is off. (default)
When 1, the TRK drive DAC output is high impedance when the TRK servo is off.
Set SFJP ($36) to 1 or TAOZ to 0 in order to boost the low frequency for the TRK Jump operation by
the $34C command TLB2ON.
SAOZ:
When 0, the SLD drive DAC output is the center potential when the SLD servo is off. (default)
When 1, the SLD drive DAC output is high impedance when the SLD servo is off.
136
CXD3021R
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
0
1
FB9
FB8
FB7
FB6
FB5
FB4
FB3
FB2
FB1
--
When D15 = D14 = D13 = D12 = 1 ($34F)
D11 = 0, D10 = 1
FBIAS register write
FB9 to FB1: Data;
two's complement data, FB9 = MSB.
For FE input conversion, FB9 to FB1 = 011111111 corresponds to 255/256
V
DD
/4
and FB9 to FB1 = 100000000 to 256/256
V
DD
/4 respectively. (V
DD
: supply voltage)
1
1
1
1
1
0
FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1
--
When D15 = D14 = D13 = D12 = D11 = 1 ($34F)
D10 = 0
FBIAS LIMIT register write
FBL9 to FBL1: Data; data compared with FB9 to FB1, FBL9 = MSB.
When using the FBIAS register in counter mode, counter operation stops when the
value of FB9 to FB1 matches with FBL9 to FBL1.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
0
0
TV9
TV8
TV7
TV6
TV5
TV4
TV3
TV2
TV1
TV0
When D15 = D14 = D13 = D12 = 1 ($34F)
D11 = 0, D10 = 0
TRVSC register write
TV9 to TV0: Data;
two's complement data, TV9 = MSB.
For TE input conversion, TV9 to TV0 = 0011111111 corresponds to 255/256
V
DD
/4
and TV9 to TV0 = 1100000000 to 256/256
V
DD
/4 respectively. (V
DD
: supply voltage)
Note) When the TRVSC register is read out, the data length is 9 bits. At this time, data corresponding to each
bits TV8 to TV0 during external write are read out.
When reading out internally measured values and then writing these values externally, set TV9 the
same as TV8.
$34F
137
CXD3021R
$35 (preset: $35 58 2D)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FT1
FT0
FS5
FS4
FS3
FS2
FS1
FS0
FTZ
FG6
FG5
FG4
FG3
FG2
FG1
FG0
FT1, FT0, FTZ: Focus search-up speed
Default value: 010 (0.673
V
DD
V/s)
FT1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
1.35
V
DD
0.673
V
DD
0.449
V
DD
0.336
V
DD
1.79
V
DD
1.08
V
DD
0.897
V
DD
0.769
V
DD
FT0
FTZ
Focus search speed [V/s]
FS5 to Fs0:
Focus search limit voltage
Default value: 011000 ((1 24/64)
V
DD
/2, V
DD
: supply voltage)
FG6 to FG0:
AGF convergence gain setting value
Default value: 0101101
$36 (preset: $36 0E 2E)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TDZC DTZC TJ5
TJ4
TJ3
TJ2
TJ1
TJ0
SFJP TG6
TG5
TG4
TG3
TG2
TG1
TG0
TDZC:
Selects the TZC signal for generating the TRKCNCL signal during brake circuit operation.
When TDZC = 0, the edge of the HPTZC or STZC signal, whichever has the faster phase, is used.
When TDZC = 1, the edge of the HPTZC, STZC signal or the tracking drive signal zero-cross,
whichever has the fastest phase, is used. (See 5-12.)
DTZC:
DTZC delay (8.5/4.25s, when MCK = 128Fs)
Default value: 0 (4.25s)
TJ5 to TJ0:
Track jump voltage
Default value: 001110 ((1 14/64)
V
DD
/2, V
DD
: supply voltage)
SFJP:
Surf jump mode on/off
The tracking drive output is generated by adding the tracking filter output and TJReg (TJ5 to TJ0),
by setting SFJP to 1.
Set SFJP to 1 or TAOZ ($34D) to 0 in order to boost the low frequency for the TRK Jump
operation by the $34C command TLB2ON.
TG6 to TG0:
AGT convergence gain setting value
Default value: 0101110
: preset, V
DD
: supply voltage
138
CXD3021R
$37 (preset: $37 50 BA)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS
AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT
FZSH, FZSL:
FZC (Focus Zero Cross) slice level
Default value: 01 (1/8
V
DD
/2, V
DD
: supply voltage); FE input conversion
FZSH
0
0
1
1
0
1
0
1
1/4
V
DD
/2
1/8
V
DD
/2
1/16
V
DD
/2
1/32
V
DD
/2
FZSL
Slice level
SM5 to SM0:
Sled move voltage
Default value: 010000 ((1
16/64)
V
DD
/2, V
DD
: supply voltage)
AGS:
AGCNTL self-stop on/off
Default value: 1 (on)
AGJ:
AGCNTL convergence completion judgment time during low sensitivity adjustment (31/63ms,
when MCK = 128Fs)
Default value: 0 (63ms)
AGGF:
Focus AGCNTL internally generated sine wave amplitude (small/large)
Default value: 1 (large)
AGGT:
Tracking AGCNTL internally generated sine wave amplitude (small/large)
Default value: 1 (large)
AGGF
0 (small)
1 (large)
1/32
V
DD
/2
1/16
V
DD
/2
1/16
V
DD
/2
1/8
V
DD
/2
AGGT
0 (small)
1 (large)
FE/TE input conversion
AGV1:
AGCNTL convergence sensitivity during high sensitivity adjustment; high/low
Default value: 1 (high)
AGV2:
AGCNTL convergence sensitivity during low sensitivity adjustment; high/low
Default value: 0 (low)
AGHS:
AGCNTL high sensitivity adjustment on/off
Default value: 1 (on)
AGHT:
AGCNTL high sensitivity adjustment time (128/256ms, when MCK = 128Fs)
Default value: 0 (256ms)
: preset
: preset
139
CXD3021R
$38 (preset: $38 00 00)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0
VCLM: VC level measurement (on/off)
VCLC: VC level compensation for FCS In register (on/off)
FLM:
Focus zero level measurement (on/off)
FLC0:
Focus zero level compensation for FZC register (on/off)
RFLM: RF zero level measurement (on/off)
RFLC:
RF zero level compensation (on/off)
AGF:
Focus auto gain adjustment (on/off)
AGT:
Tracking auto gain adjustment (on/off)
DFSW: Defect disable switch (on/off)
Setting this switch to 1 (on) disables the defect countermeasure circuit.
LKSW: Lock switch (on/off)
Setting this switch to 1 (on) disables the sled free-running prevention circuit.
TBLM: Traverse center measurement (on/off)
TCLM: Tracking zero level measurement (on/off)
FLC1:
Focus zero level compensation for FCS In register (on/off)
TLC2:
Traverse center compensation (on/off)
TLC1:
Tracking zero level compensation (on/off)
TLC0:
VC level compensation for TRK/SLD In register (on/off)
Note) Commands marked with
are accepted every 2.9ms. (when MCK = 128Fs)
All commands are on when 1.
140
CXD3021R
SD6
1
0
0
1
0
Data RAM data for address = SD4 to SD0
Coefficient RAM data for address = SD5 to SD0
SD4
1
0
SD3 to SD0
1 1 1 1
1 1 1 0
1 1 0 1
1 1 0 0
0 0 1 1
0 0 1 0
0 0 0 1
1 1
1 0
0 1
0 0 1 1
0 0 1 0
0 0 0 1
0 0 0 0
RF AVRG register
RFDC input signal
FBIAS register
TRVSC register
RFDC envelope (bottom)
RFDC envelope (peak)
RFDC envelope
(peak) (bottom)
VC AVRG register
FE AVRG register
TE AVRG register
FE input signal
TE input signal
SE input signal
VC input signal
8 bits
8 bits
9 bits
9 bits
8 bits
8 bits
8 bits
9 bits
9 bits
9 bits
8 bits
8 bits
8 bits
8 bits
$399F
$399E
$399D
$399C
$3993
$3992
$3991
$398C
$3988
$3984
$3983
$3982
$3981
$3980
8 bits
16 bits
SD5
Readout data
Readout data length
: Don't care
Note) Coefficients K40 to K4F cannot be read out.
See the description for SRO1 and SRO0 of $3F concerning readout methods for the above data.
D15
D14
D13
D12
D11
D10
D9
D8
DAC
SD6
SD5
SD4
SD3
SD2
SD1
SD0
DAC:
Serial data readout DAC mode (on/off)
SD6 to SD0:
Serial readout data select
$39
141
CXD3021R
$3A (preset: $3A 00 00)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
FBON FBSS FBUP FBV1 FBV0
0
TJD0 FPS1 FPS0 TPS1 TPS0
0
SJHD INBK MTI0
FBON:
FBIAS (focus bias) register addition (on/off)
The FBIAS register value is added to the signal loaded into the FCS In register by setting
FBON = 1 (on).
FBSS:
FBIAS (focus bias) register/counter switching
FBSS = 0: register, FBSS = 1: counter
FBUP:
FBIAS (focus bias) counter up/down operation switching
This performs counter up/down control when FBSS = 1.
FBUP = 0: down counter
FBUP = 1: up counter
FBV1, FBV0:
FBIAS (focus bias) counter voltage switching
The number of FCS BIAS count-up/-down steps per cycle is decided by these bits.
TJD0:
This sets the tracking servo filter to 0 when switched from track jump to servo on even if SFJP
= 1 (during surf jump operation).
FPS1, FPS0:
Gain setting for the whole focus filter.
TPS1, TPS0:
Gain setting for the whole tracking filter.
These are effective for increasing the overall gain in order to widen the servo band.
(See " 5-20. Filter Composition".)
SJHD:
This holds the tracking filter output at the value when surf jump starts during surf jump.
INBK:
The masking method for the brake circuit is selected. When INBK = 1, the tracking filter input
is masked instead of the drive output.
MTI0:
The tracking filter input is masked when the MIRR signal is high by setting MTI0 = 1.
The counter changes once for each
sampling cycle of the focus servo
filter. When MCK is 128Fs, the
sampling frequency is 88.2kHz.
When converted to FE input, 1 step
is approximately 1/2
9
V
DD
/2,
V
DD
= supply voltage.
FBV1
0
0
1
1
0
1
0
1
1
2
4
8
FBV0
Number of steps per cycle
FPS1
0
0
1
1
FPS0
0
1
0
1
0dB
+6dB
+12dB
+18dB
Relative gain
TPS1
0
0
1
1
TPS0
0
1
0
1
0dB
+6dB
+12dB
+18dB
Relative gain
: preset
: preset
142
CXD3021R
$3B (preset: $3B E0 50)
SFOX, SFO2, SFO1: FOK slice level
Default value: 011 (28/256
V
DD
/2, V
DD
: supply voltage)
RFDC input conversion
SFOX
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
16/256
V
DD
/2
20/256
V
DD
/2
24/256
V
DD
/2
28/256
V
DD
/2
32/256
V
DD
/2
40/256
V
DD
/2
48/256
V
DD
/2
56/256
V
DD
/2
SFO2
0
1
0
1
0
1
0
1
SFO1
Slice level
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT
0
0
0
: preset
SDF2, SDF1:
DFCT slice level
Default value: 10 (0.0313
V
DD
V)
RFDC input conversion
SDF2
0
0
1
1
0
1
0
1
0.0156
V
DD
0.0234
V
DD
0.0313
V
DD
0.0391
V
DD
SDF1
Slice level
MAX2, MAX1:
DFCT maximum time
Default value: 00 (no timer limit)
MAX2
0
0
1
1
0
1
0
1
No timer limit
2.00ms
2.36
2.72
MAX1
DFCT maximum time
: preset, V
DD
: supply voltage
: preset
BTF:
Bottom hold double-speed count-up mode for MIRR signal generation
On/off (default: off)
On when 1.
143
CXD3021R
D2V2, D2V1:
Peak hold 2 for DFCT signal generation
Count-down speed setting
Default value: 01 (0.086
V
DD
V/ms, 44.1kHz)
[V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the
operating frequency of the internal counter.
D1V2, D1V1:
Peak hold 1 for DFCT signal generation
Count-down speed setting
Default value: 01 (0.688
V
DD
V/ms, 352.8kHz)
[V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate
the operating frequency of the internal counter.
RINT:
This initializes the initial-stage registers of the circuits which generate MIRR, DFCT and FOK.
D2V2
0
0
1
1
0
1
0
1
22.05
44.1
88.2
176.4
0.0431
V
DD
0.0861
V
DD
0.172
V
DD
0.344
V
DD
D2V1
Count-down speed
[V/ms]
[kHz]
176.4
352.8
705.6
1411.2
0.344
V
DD
0.688
V
DD
1.38
V
DD
2.75
V
DD
D1V2
0
0
1
1
0
1
0
1
D1V1
Count-down speed
[V/ms]
[kHz]
: preset, V
DD
: supply voltage
: preset, V
DD
: supply voltage
144
CXD3021R
$3C (preset: $3C 00 80)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
COSS COTS CETZ CETF COT2 COT1 MOT2
0
BTS1 BTS0 MRC1 MRC0
0
0
0
0
COSS, COTS: These select the TZC signal used when generating the COUT signal.
Preset = HPTZC.
STZC is the TZC generated by sampling the TE signal at 700kHz. (when MCK = 128Fs)
DTZC is the delayed phase STZC. (The delay time can be selected by D14 of $36.)
HPTZC is the fast phase TZC passed through a HPF with a cut-off frequency of 1kHz.
See 5-13.
CETZ:
The input from the TE pin normally enters the TRK filter and is used to generate the TZC
signal. However, the input from the CE pin can also be used. This function is for the center
error servo.
When 0, the TZC signal is generated by using the signal input to the TE pin.
When 1, the TZC signal is generated by using the signal input to the CE pin.
CETF:
When 0, the signal input to the TE pin is input to the TRK servo filter.
When 1, the signal input to the CE pin is input to the TRK servo filter.
These commands output the TZC signal.
COT2, COT1:
This outputs the TZC signal from the COUT pin.
COSS
1
0
0
--
0
1
STZC
HPTZC
DTZC
COTS
TZC
: preset, --: don't care
BTS1
0
0
1
1
0
1
0
1
1
2
4
8
BTS0
Number of count-up steps per cycle
MRC1
0
0
1
1
0
1
0
1
5.669
11.338
22.675
45.351
MRC0
Setting time [s]
: preset (when MCK = 128Fs)
MOT2:
The STZC signal is output from the MIRR pin by setting MOT2 to 1.
These commands set the MIRR signal generation circuit.
BTS1, BTS0:
These set the count-up speed for the bottom hold value of the MIRR generation circuit.
The time per step is approximately 708ns (when MCK = 128Fs). The preset value is BTS1 = 1,
BTS0 = 0 like the CXD2586R. These commands are valid only when BTF of $3B is 0.
MRC1, MRC0: These set the minimum pulse width for masking the MIRR signal of the MIRR generation circuit.
As noted in 5-9, the MIRR signal is generated by comparing the waveform obtained by
subtracting the bottom hold value from the peak hold value with the MIRR comparator level.
Strictly speaking, however, for MIRR to become high, these levels must be compared
continuously for a certain time. These commands set that time.
The preset value is MRC1 = 0, MRC0 = 0 like the CXD2586R.
COT2
1
0
0
--
1
0
STZC
HPTZC
COUT
COT1
COUT pin output
: preset, --: don't care
145
CXD3021R
$3D (preset: $3D 00 00)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SFID SFSK THID THSK
0
TLD2 TLD1 TLD0
0
0
0
0
0
0
0
0
SFID:
SLED servo filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK
filter second-stage output.
When the low-frequency component of the tracking error signal obtained from the RF amplifier
is attenuated, the low frequency can be amplified and input to the SLD servo filter.
SFSK:
Only during TRK servo gain up2 operation, coefficient K30 is used instead of K00. Normally,
the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain
up2, creating a difference in the DC level at M0D. In this case, the DC level of the signal
transmitted to M00 can be kept uniform by adjusting the K30 value even during the above
switching.
THID:
TRK hold filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK
filter second-stage output.
When signals other than the tracking error signal from the RF amplifier are input to the SE
input pin, the signal transmitted from the TE pin can be obtained as the TRK hold filter input.
THSK:
Only during TRK servo gain up2 operation, coefficient K46 is used instead of K40. Normally,
the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain
up2, creating a difference in the DC level at M0D. In this case, the DC level of the signal
transmitted to M18 can be kept uniform by adjusting the K46 value even during the above
switching.
See " 5-20. Filter Composition" regarding the SFID, SFSK, THID and THSK commands.
TLD0 to 2:
These turn on and off SLD filter correction independently of the TRK filter.
See $38 (TLC0 to 2) and Fig. 5-3.
TLC0
0
1
--
0
1
OFF
ON
OFF
OFF
ON
ON
TLD0
VC level correction
TRK filter
SLD filter
: preset, --: don't care
TLC1
0
1
--
0
1
OFF
ON
OFF
OFF
ON
ON
TLD1
Tracking zero level correction
TRK filter
SLD filter
TLC2
0
1
--
0
1
OFF
ON
OFF
OFF
ON
ON
TLD2
Traverse center correction
TRK filter
SLD filter
146
CXD3021R
Input coefficient sign inversion when SFID = 1 and THID = 1
The preset coefficients for the TRK filter are negative for input and positive for output. With this, CXD3021R
outputs servo drives which have the reversed phase of input errors.
K19
TRK Filter
K22
Negative input coefficient
Positive output coefficient
TE
K00
SLD Filter
K05
Negative input coefficient
Positive output coefficient
SE
K40
TRK Hold Filter
K45
Positive input coefficient
Positive output coefficient
TRK Hold
When SFID = 1, the TRK filter negative input coefficient is applied to the SLD filter, so the SLD input coefficient
(K00) sign must be inverted. (For example, inverting the sign for coefficient K00: E0H results in 60H.)
For the same reason, when THID = 1, the TRK hold input coefficient (K40) sign must be inverted.
K19
TRK Filter
K22
Negative input coefficient
Positive output coefficient
TE
K00
SLD Filter
K05
Positive input coefficient
Positive output coefficient
SE
K40
TRK Hold Filter
K45
Negative input coefficient
Positive output coefficient
TRK Hold
MOD
For TRK servo gain normal
See " 5-20. Filter Composition".
147
CXD3021R
$3E (preset: $3E 00 00)
F1NM, F1DM:
Quasi double accuracy setting for FCS servo filter first-stage
On when 1; default is 0.
F1NM: Gain normal
F1DM: Gain down
T1NM, T1UM:
Quasi double accuracy setting for TRK servo filter first-stage
On when 1; default is 0.
T1NM: Gain normal
T1UM: Gain up
F3NM, F3DM:
Quasi double accuracy setting for FCS servo filter third-stage
On when 1; default is 0.
Generally, the advance amount of the phase becomes large by partially setting the FCS servo
third-stage filter which is used as the phase compensation filter to double accuracy.
F3NM: Gain normal
F3DM: Gain down
T3NM, T3UM:
Quasi double accuracy setting for TRK servo filter third-stage
On when 1; default is 0.
Generally, the advance amount of the phase becomes large by partially setting the TRK servo
third-stage filter which is used as the phase compensation filter to double accuracy.
T3NM: Gain normal
T3UM: Gain up
Note) Filter first- and third-stage quasi double accuracy settings can be set individually.
See " 5-20 Filter Composition" at the end of this specification concerning quasi double accuracy.
DFIS:
FCS hold filter input extraction node selection
0: M05 (Data RAM address 05); default
1: M04 (Data RAM address 04)
TLCD:
This command masks the TLC2 command of $38 only when FOK is low.
On when 1; default is 0
LKIN:
When 0, the internally generated LOCK signal is output to the LOCK pin. (default)
When 1, the LOCK signal can be input from an external source to the LOCK pin.
COIN:
When 0, the internally generated COUT signal is output to the COUT pin. (default)
When 1, the COUT signal can be input from an external source to the COUT pin.
The MIRR, DFCT and FOK signals can also be input from an external source.
MDFI:
When 0, the MIRR, DFCT and FOK signals are generated internally. (default)
When 1, the MIRR, DFCT and FOK signals can be input from an external source through the
MIRR, DFCT and FOK pins.
MIRI:
When 0, the MIRR signal is generated internally. (default)
When 1, the MIRR signal can be input from an external source through the MIRR pin.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD
0
LKIN COIN MDFI MIRI XT1D
XT1D:
The clock of the FSTIO pin is used without being frequency-divided as the master clock for the
servo block by setting XT1D to 1. This command takes precedence over the XTSL pin, XT2D
and XT4D. See the description of $3F for XT2D and XT4D.
MDFI
0
0
1
0
1
--
MIRR, DFCT and FOK are all generated internally.
MIRR only is input from an external source.
MIRR, DFCT and FOK are all input from an external source.
MIRI
: preset, --: don't care
148
CXD3021R
$3F (preset: $3F 00 00)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
AGG4 XT4D XT2D
0
DRR2 DRR1 DRR0
0
ASFG FTQ LPAS SRO1 SRO0 AGHF
0
XT4D, XT2D:
MCK (digital servo master clock) frequency division setting
This command forcibly sets the frequency division ratio to 1/4, 1/2 or 1/1 when MCK is
generated from the FSTIO pin clock. See the description of $3E for XT1D. And see " 4-12.
Clock System".
AGG4:
This varies the amplitude of the internally generated sine wave using the AGGF and AGGT
commands during AGC. When AGG4 = 0, the default is used. When AGG4 = 1, the setting is
as shown in the table below.
AGG4
0
1
AGGF
0
1
--
--
0
0
1
1
AGGT
--
--
0
1
0
1
0
1
FE input
conversion
1/32
V
DD
/2
1/16
V
DD
/2
--
--
TE input
conversion
--
--
1/16
V
DD
/2
1/8
V
DD
/2
DRR2 to DRR0: Partially clears the Data RAM values (0 write).
The following values are cleared when 1 (on) respectively; default = 0
DRR2: M08, M09, M0A
DRR1: M00, M01, M02
DRR0: M00, M01, M02 only when LOCK = low
Note) Set DRR1 and DRR0 on for 50s or more.
ASFG:
When vibration detection is performed during anti-shock circuit operation, the FCS servo filter
is forcibly set to gain normal status.
On when 1; default is 0
FTQ:
The focus search-up speed is set to the 1/4 value of that determined by FT1, FT0 and FTZ ($35).
On when 1; default is 0
See $37 for AGGF and AGGT.
The presets are AGG4 = 0,
AGGF = 1 and AGGT = 1.
: preset, --: don't care
: preset, --: don't care
XT1D
0
1
0
0
XT2D
0
--
1
0
XT4D
0
--
--
1
According to XTSL
1/1
1/2
1/4
Frequency division ratio
Sine wave amplitude
1/64
V
DD
/2
1/32
V
DD
/2
1/16
V
DD
/2
1/8
V
DD
/2
149
CXD3021R
LPAS:
Built-in analog buffer low-current consumption mode
This mode reduces the total analog buffer current consumption for the VC, TE, SE and FE
input analog buffers by using a single operational amplifier.
On when 1; default is 0
Note) When using this mode, first check whether each error signal is properly A/D converted
using the $3F commands SRO1 and SRO0.
SRO1, SRO0:
These commands are used to continuously externally output various data inside the digital
servo block which have been specified with the $39 command. (However, D15 (DAC) of $39
must be set to 1.)
Digital output (SOCK, XOLT and SOUT) can be obtained from three specified pins by setting
these commands to 1 respectively. The default is 0, 0. (no readout)
The output pins for each case are shown below.
SOCK
XOLT
SOUT
DA13 pin
DA12 pin
DA14 pin
DA10 pin
DA09 pin
DA11 pin
SRO1 = 1
SRO0 = 1
(See "Description of Data Readout" on the following page.)
AGHF:
This halves the frequency of the internally generated sine wave during AGC.
FTQ:
The slope of the output during focus search is 1/4 of the conventional output slope.
On when 1; default is 0
150
CXD3021R
Description of Data Readout
SOCK
(5.6448MHz)
XOLT
(88.2kHz)
SOUT
MSB
LSB
...
MSB
LSB
...
...
...
...
...
16-bit register
for serial/parallel
conversion
16-bit register
for latch
SOUT
SOCK
XOLT
CLK
CLK
MSB
LSB
To the 7-segment LED
To the 7-segment LED
Data is connected to the 7-segment LED
by 4 bits at a time. This enables Hex
display using four 7-segment LEDs.
MSB
LSB
SOUT
SOCK
XOLT
Serial data input
Clock input
Latch enable input
Analog
output
D/A
To an oscilloscope, etc.
Offset adjustment,
gain adjustment
Waveforms can be monitored with an oscilloscope using a serial
input-type D/A converter as shown above.
151
CXD3021R
5-19. List of Servo Filter Coefficients
<Coefficient Preset Value Table (1)>
Fix indicates that normal preset values should be used.
ADDRESS
K00
K01
K02
K03
K04
K05
K06
K07
K08
K09
K0A
K0B
K0C
K0D
K0E
K0F
E0
81
23
7F
6A
10
14
30
7F
46
81
1C
7F
58
82
7F
SLED INPUT GAIN
SLED LOW BOOST FILTER A-H
SLED LOW BOOST FILTER A-L
SLED LOW BOOST FILTER B-H
SLED LOW BOOST FILTER B-L
SLED OUTPUT GAIN
FOCUS INPUT GAIN
SLED AUTO GAIN
FOCUS HIGH CUT FILTER A
FOCUS HIGH CUT FILTER B
FOCUS LOW BOOST FILTER A-H
FOCUS LOW BOOST FILTER A-L
FOCUS LOW BOOST FILTER B-H
FOCUS LOW BOOST FILTER B-L
FOCUS PHASE COMPENSATE FILTER A
FOCUS DEFECT HOLD GAIN
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K1A
K1B
K1C
K1D
K1E
K1F
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K2A
K2B
K2C
K2D
K2E
K2F
4E
32
20
30
80
77
80
77
00
F1
7F
3B
81
44
7F
5E
FOCUS PHASE COMPENSATE FILTER B
FOCUS OUTPUT GAIN
ANTI SHOCK INPUT GAIN
FOCUS AUTO GAIN
HPTZC / Auto Gain HIGH PASS FILTER A
HPTZC / Auto Gain HIGH PASS FILTER B
ANTI SHOCK HIGH PASS FILTER A
HPTZC / Auto Gain LOW PASS FILTER B
Fix
TRACKING INPUT GAIN
TRACKING HIGH CUT FILTER A
TRACKING HIGH CUT FILTER B
TRACKING LOW BOOST FILTER A-H
TRACKING LOW BOOST FILTER A-L
TRACKING LOW BOOST FILTER B-H
TRACKING LOW BOOST FILTER B-L
82
44
18
30
7F
46
81
3A
7F
66
82
44
4E
1B
00
00
TRACKING PHASE COMPENSATE FILTER A
TRACKING PHASE COMPENSATE FILTER B
TRACKING OUTPUT GAIN
TRACKING AUTO GAIN
FOCUS GAIN DOWN HIGH CUT FILTER A
FOCUS GAIN DOWN HIGH CUT FILTER B
FOCUS GAIN DOWN LOW BOOST FILTER A-H
FOCUS GAIN DOWN LOW BOOST FILTER A-L
FOCUS GAIN DOWN LOW BOOST FILTER B-H
FOCUS GAIN DOWN LOW BOOST FILTER B-L
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
FOCUS GAIN DOWN DEFECT HOLD GAIN
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
FOCUS GAIN DOWN OUTPUT GAIN
NOT USED
NOT USED
DATA
CONTENTS
152
CXD3021R
<Coefficient Preset Value Table (2)>
ADDRESS
K30
K31
K32
K33
K34
K35
K36
K37
K38
K39
K3A
K3B
K3C
K3D
K3E
K3F
80
66
00
7F
6E
20
7F
3B
80
44
7F
77
86
0D
57
00
SLED INPUT GAIN
(Only when TRK Gain Up2 is accessed with SFSK = 1.)
ANTI SHOCK LOW PASS FILTER B
NOT USED
ANTI SHOCK HIGH PASS FILTER B-H
ANTI SHOCK HIGH PASS FILTER B-L
ANTI SHOCK FILTER COMPARATE GAIN
TRACKING GAIN UP2 HIGH CUT FILTER A
TRACKING GAIN UP2 HIGH CUT FILTER B
TRACKING GAIN UP2 LOW BOOST FILTER A-H
TRACKING GAIN UP2 LOW BOOST FILTER A-L
TRACKING GAIN UP2 LOW BOOST FILTER B-H
TRACKING GAIN UP2 LOW BOOST FILTER B-L
TRACKING GAIN UP PHASE COMPENSATE FILTER A
TRACKING GAIN UP PHASE COMPENSATE FILTER B
TRACKING GAIN UP OUTPUT GAIN
NOT USED
K40
K41
K42
K43
K44
K45
K46
K47
K48
K49
K4A
K4B
K4C
K4D
K4E
K4F
04
7F
7F
79
17
6D
00
00
02
7F
7F
79
17
54
00
00
TRACKING HOLD FILTER INPUT GAIN
TRACKING HOLD FILTER A-H
TRACKING HOLD FILTER A-L
TRACKING HOLD FILTER B-H
TRACKING HOLD FILTER B-L
TRACKING HOLD FILTER OUTPUT GAIN
TRACKING HOLD FILTER INPUT GAIN
(Only when TRK Gain Up2 is accessed with THSK = 1.)
NOT USED
FOCUS HOLD FILTER INPUT GAIN
FOCUS HOLD FILTER A-H
FOCUS HOLD FILTER A-L
FOCUS HOLD FILTER B-H
FOCUS HOLD FILTER B-L
FOCUS HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED
DATA
CONTENTS
153
CXD3021R
5-20. Filter Composition
The internal filter composition is shown below.
K
: Coefficient RAM address, M
: Data RAM address
K
0
D
K
0
C
K
0
E
K
1
0
Z
1
K
0
B
Z
1
K
0
9
K
0
A
M
0
4
M
0
3
2
7
M
0
6
Z
1
K
1
1
K
1
3
F
C
S
A
U
T
O
G
a
i
n
M
0
7
2
1
K
0
6
A
G
F
O
N
K
0
6
D
F
C
T
F
C
S
H
o
l
d
R
e
g
2
F
C
S
I
n
R
e
g
S
i
n
R
O
M
K
0
8
Z
1
M
0
5
K
0
F
F
C
S
H
o
l
d
R
e
g
1
K
2
9
K
2
8
K
2
A
K
2
C
Z
1
K
2
7
Z
1
K
2
5
K
2
6
M
0
4
M
0
3
2
7
2
7
M
0
6
Z
1
K
2
D
K
1
3
F
S
C
A
U
T
O
G
a
i
n
M
0
7
2
1
K
0
6
D
F
C
T
F
C
S
H
o
l
d
R
e
g
2
F
C
S
I
n
R
e
g
K
2
4
Z
1
M
0
5
K
2
8
F
C
S
H
o
l
d
R
e
g
1
2
7
F
C
S
S
e
r
v
o
G
a
i
n
D
o
w
n
f
s
=
8
8
.
2
k
H
z
N
o
t
e
)
S
e
t
t
h
e
M
S
B
b
i
t
o
f
t
h
e
K
0
B
a
n
d
K
0
D
c
o
e
f
f
i
c
i
e
n
t
s
t
o
0
.
N
o
t
e
)
S
e
t
t
h
e
M
S
B
b
i
t
o
f
t
h
e
K
2
7
a
n
d
K
2
9
c
o
e
f
f
i
c
i
e
n
t
s
t
o
0
.
F
C
S
S
e
r
v
o
G
a
i
n
N
o
r
m
a
l
f
s
=
8
8
.
2
k
H
z
2
7
D
A
C
B
K
2
Z
1
Z
1
F
C
S
S
R
C
H
B
K
1
B
K
5
Z
1
Z
1
B
K
4
F
P
S
1
,
0
B
K
3
B
K
6
154
CXD3021R
K
1
F
K
1
E
K
2
0
K
2
1
Z
1
K
1
D
Z
1
K
1
B
K
1
C
M
0
C
M
0
B
2
7
M
0
E
Z
1
K
2
2
K
2
3
T
R
K
A
U
T
O
G
a
i
n
M
0
F
2
1
K
1
9
A
G
T
O
N
K
1
9
D
F
C
T
T
R
K
H
o
l
d
R
e
g
T
R
K
I
n
R
e
g
S
i
n
R
O
M
K
1
A
Z
1
M
0
D
T
o
S
L
D
S
e
r
v
o
T
R
K
H
o
l
d
K
3
D
Z
1
Z
1
K
1
B
K
3
C
M
0
C
M
0
B
K
3
E
K
2
3
T
R
K
A
U
T
O
G
a
i
n
M
0
F
2
1
K
1
9
D
F
C
T
T
R
K
H
o
l
d
R
e
g
T
R
K
I
n
R
e
g
K
1
A
Z
1
M
0
E
2
7
T
R
K
S
e
r
v
o
G
a
i
n
U
p
1
f
s
=
8
8
.
2
k
H
z
N
o
t
e
)
S
e
t
t
h
e
M
S
B
b
i
t
o
f
t
h
e
K
1
D
a
n
d
K
1
F
c
o
e
f
f
i
c
i
e
n
t
s
t
o
0
.
K
3
B
K
3
A
K
3
C
K
3
D
Z
1
K
3
9
Z
1
K
3
7
K
3
8
M
0
C
M
0
B
2
7
M
0
E
Z
1
K
3
E
K
2
3
T
R
K
A
U
T
O
G
a
i
n
M
0
F
2
1
K
1
9
D
F
C
T
T
R
K
H
o
l
d
R
e
g
T
R
K
I
n
R
e
g
K
3
6
Z
1
M
0
D
2
7
T
R
K
S
e
r
v
o
G
a
i
n
U
p
2
f
s
=
8
8
.
2
k
H
z
N
o
t
e
)
S
e
t
t
h
e
M
S
B
b
i
t
o
f
t
h
e
K
3
9
a
n
d
K
3
B
c
o
e
f
f
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c
i
e
n
t
s
t
o
0
.
T
R
K
S
e
r
v
o
G
a
i
n
N
o
r
m
a
l
f
s
=
8
8
.
2
k
H
z
2
7
B
K
2
Z
1
Z
1
D
A
C
T
R
K
J
M
P
B
K
1
B
K
5
Z
1
Z
1
B
K
4
B
K
8
Z
1
Z
1
B
K
7
T
P
S
1
,
0
B
K
9
B
K
3
B
K
6
N
o
t
e
)
S
e
t
S
F
J
P
(
$
3
6
)
t
o
1
o
r
T
A
O
Z
(
$
3
4
D
)
t
o
0
i
n
o
r
d
e
r
t
o
b
o
o
s
t
t
h
e
l
o
w
f
r
e
q
u
e
n
c
y
f
o
r
t
h
e
T
R
K
J
u
m
p
o
p
e
r
a
t
i
o
n
.
155
CXD3021R
K
0
D
K
0
C
8
0
H
K
1
0
Z
1
K
0
B
Z
1
7
F
H
K
0
A
M
0
4
M
0
3
2
7
M
0
6
Z
1
K
1
1
K
1
3
F
C
S
A
U
T
O
G
a
i
n
M
0
7
2
1
K
0
6
A
G
F
O
N
K
0
6
D
F
C
T
F
C
S
H
o
l
d
R
e
g
2
F
C
S
I
n
R
e
g
S
i
n
R
O
M
8
1
H
Z
1
M
0
5
K
0
F
F
C
S
H
o
l
d
R
e
g
1
2
1
K
0
6
D
F
C
T
F
C
S
H
o
l
d
R
e
g
2
F
C
S
I
n
R
e
g
2
7
2
7
N
o
t
e
)
S
e
t
t
h
e
M
S
B
b
i
t
o
f
t
h
e
K
0
B
a
n
d
K
0
D
c
o
e
f
f
i
c
i
e
n
t
s
d
u
r
i
n
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n
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m
a
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r
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t
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o
n
,
a
n
d
o
f
t
h
e
K
0
B
,
K
0
9
a
n
d
K
0
E
c
o
e
f
f
i
c
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n
t
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d
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r
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g
q
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c
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r
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c
y
t
o
0
.
F
C
S
S
e
r
v
o
G
a
i
n
N
o
r
m
a
l
;
f
s
=
8
8
.
2
k
H
z
,
d
u
r
i
n
g
q
u
a
s
i
d
o
u
b
l
e
a
c
c
u
r
a
c
y
(
E
x
.
$
3
E
A
X
X
0
)
K
0
E
2
7
K
0
9
2
7
K
0
8
2
7
K
2
9
K
2
8
8
0
H
K
2
C
Z
1
K
2
7
Z
1
7
F
H
K
2
6
M
0
4
M
0
3
2
7
M
0
6
Z
1
K
2
D
K
1
3
F
C
S
A
U
T
O
G
a
i
n
M
0
7
8
1
H
Z
1
M
0
5
K
2
B
F
C
S
H
o
l
d
R
e
g
1
2
7
K
2
A
2
7
K
2
5
2
7
K
2
4
2
7
N
o
t
e
)
S
e
t
t
h
e
M
S
B
b
i
t
o
f
t
h
e
K
2
7
a
n
d
K
2
9
c
o
e
f
f
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c
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n
t
s
d
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r
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n
g
n
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m
a
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r
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t
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o
n
,
a
n
d
o
f
t
h
e
K
2
4
,
K
2
5
a
n
d
K
2
A
c
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f
f
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d
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r
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g
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r
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o
0
.
F
C
S
S
e
r
v
o
G
a
i
n
N
o
r
m
a
l
;
f
s
=
8
8
.
2
k
H
z
,
d
u
r
i
n
g
q
u
a
s
i
d
o
u
b
l
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a
c
c
u
r
a
c
y
(
E
x
.
$
3
E
5
X
X
0
)
B
K
2
Z
1
Z
1
F
C
S
S
R
C
H
B
K
1
B
K
5
Z
1
Z
1
B
K
4
F
P
S
1
,
0
D
A
C
B
K
3
B
K
6
8
1
H
,
7
F
H
a
n
d
8
0
H
a
r
e
e
a
c
h
H
e
x
d
i
s
p
l
a
y
8
-
b
i
t
f
i
x
e
d
v
a
l
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e
s
w
h
e
n
s
e
t
t
o
q
u
a
s
i
d
o
u
b
l
e
a
c
c
u
r
a
c
y
.
156
CXD3021R
2
1
K
1
9
A
G
T
O
N
K
1
9
D
F
C
T
T
R
K
H
o
l
d
R
e
g
T
R
K
I
n
R
e
g
S
i
n
R
O
M
2
1
K
1
9
D
F
C
T
T
R
K
H
o
l
d
R
e
g
T
R
K
I
n
R
e
g
2
1
K
1
9
D
F
C
T
T
R
K
H
o
l
d
R
e
g
T
R
K
I
n
R
e
g
K
1
F
K
1
E
8
0
H
K
2
1
Z
1
K
1
D
Z
1
7
F
H
K
1
C
M
0
C
M
0
B
2
7
M
0
E
Z
1
K
2
2
K
2
3
T
R
K
A
U
T
O
G
a
i
n
M
0
F
8
1
H
Z
1
M
0
D
2
7
K
2
0
2
7
K
1
B
2
7
K
1
A
2
7
K
3
D
Z
1
K
3
C
Z
1
7
F
H
8
0
H
M
0
C
M
0
B
K
3
E
K
2
3
T
R
K
A
U
T
O
G
a
i
n
M
0
F
8
1
H
Z
1
2
7
K
1
B
2
7
K
1
A
2
7
K
3
B
K
3
A
8
0
H
K
3
D
Z
1
K
3
9
Z
1
7
F
H
K
3
8
M
0
C
M
0
B
2
7
M
0
E
Z
1
K
3
E
K
2
3
T
R
K
A
U
T
O
G
a
i
n
M
0
F
8
1
H
Z
1
M
0
D
2
7
K
3
C
2
7
K
3
7
2
7
K
3
6
2
7
N
o
t
e
)
S
e
t
t
h
e
M
S
B
b
i
t
o
f
t
h
e
K
1
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a
n
d
K
1
F
c
o
e
f
f
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n
t
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d
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r
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157
CXD3021R
SLD Servo fs = 345Hz
K04
K03
Z
1
K02
Z
1
K01
K00
M00
2
7
2
7
M01
K05
K07
TRK
AUTO Gain
DAC
2
7
SLD MOV
M02
SLD
In Reg
2
1
K30
SFSK (only when TGUP2 is used)
SFID
M0D
TRK SERVO FILTER
Second-stage output
Note) Set the MSB bit of the K02 and K04 coefficients to 0.
HPTZC/Auto Gain fs = 88.2kHz
K15
K17
Z
1
K14
M08
M09
M0A
Z
1
AUTO Gain
Reg
2
1
AGTON
AGFON
AGFON
FCS
In Reg
TRK
In Reg
Sin ROM
Z
1
Slice
TZC Reg
Slice
2
1
158
CXD3021R
Anti Shock fs = 88.2kHz
K34
K33
K31
K16
Z
1
M09
M08
2
7
M0A
K35
Comp
K12
Anti Shock
Reg
2
1
TRK
In Reg
Z
1
Z
1
Note) Set the MSB bit of the K34 coefficient to 0.
The comparator level is 1/16 the maximum amplitude of the comparator input.
AVRG fs = 88.2kHz
M08
AVRG Reg
2
1
VC, TE, FE,
RFDC
2
7
Z
1
TRK Hold fs = 345Hz
K44
K43
K42
K41
K40
M18
2
7
2
7
M19
K45
TRK
Hold Reg
SLD
In Reg
2
1
K46
THSK (only when TGUP2 is used.)
THID
M0D
TRK SERVO FILTER
Second-stage output
Z
1
Z
1
Note) Set the MSB bit of the K42 and K44 coefficients to 0.
FCS Hold fs = 345Hz
K4C
K4B
K4A
K49
K48
M10
2
7
2
7
M11
K4D
FCS
Hold Reg 1
FCS
Hold Reg 2
Z
1
Z
1
Note) Set the MSB bit of the K4A and K4C coefficients to 0.
159
CXD3021R
5-21. TRACKING and FOCUS Frequency Response
f Frequency [Hz]
20k
1k
100
10
2.1
10
0
10
20
30
40
G
G
a
i
n
[
d
B
]
180
P
h
a
s
e
[
d
e
g
r
e
e
]
0
180
90
90
FOCUS frequency response
NORMAL
GAINDOWN
G
f Frequency [Hz]
20k
1k
100
10
2.1
10
0
10
20
30
40
G
G
a
i
n
[
d
B
]
180
P
h
a
s
e
[
d
e
g
r
e
e
]
0
180
90
90
TRACKING frequency response
G
NORMAL
GAIN UP
When using the preset coefficients with the boost function off.
When using the preset coefficients with the boost function off.
160
CXD3021R
DF
CT
X
P
L
C
K
XO
LT
SO
CK
SO
UT
WD
CK
P
D
O
A
D
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1
M
N
T
2
M
N
T
3
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N
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M
C
K
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C
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M
C
1
6
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D
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C
K
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M
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C
K
SC
LK
MU
TE
SC
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SQ
CK
SQ
SO
GF
S
CL
OK
XL
AT
DA
TA
XR
ST
SE
NS
FO
K
LD
ON
XW
O
SC
SY
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N
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V
C
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T
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Dri
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r C
irc
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Dri
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irc
uit
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2
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6
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4
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5
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3
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D
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3
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4
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A
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6
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D
D
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A
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D
A
0
8
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A
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9
D
A
1
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D
A
1
1
E
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C
K
S
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C
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W
F
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M
D
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3
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D
A
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2
FS
W
FO
K
DF
CT
MIR
R
CO
UT
CL
OK
XL
AT
LM
UT
O
DA
TA
AT
SK
SC
LK
SE
NS
DV
DD
4
AV
DD
3
AV
SS
3
AV
SS
5
XT
LI
XT
LO
AV
DD
5
AV
DD
4
PW
MR
N
AV
SS
4
DV
SS
3
XW
O
TE
SO
DV
SS
4
PW
MR
P
B
S
S
D
A
V
D
D
6
M
O
N
M
D
P
M
D
S
L
O
C
K
S
S
T
P
D
V
S
S
5
T
E
S
2
T
E
S
3
D
V
D
D
5
V
C
O
O
V
C
O
I
T
E
S
T
P
D
O
V
C
K
I
V
1
6
M
A
V
D
D
2
I
G
E
N
A
V
S
S
2
A
D
I
O
R
F
D
C
C
E
T
E
F
A
O
SE
VP
CO
2
VC
TL
FIL
O
FIL
I
PC
O
CL
TV
AV
SS
1
RF
AC
BIA
S
AS
YI
AS
YO
AV
DD
1
DV
DD
1
DV
SS
1
AS
YE
PS
SL
WD
CK
LR
CK
LR
CK
I
DA
16
PC
MD
I
DA
15
DA
13
DA
12
VC
VP
CO
1
FE
DA
14
BC
KI
T
A
O
S
A
O
A
V
S
S
6
RM
UT
O
D
T
S
0
P
W
M
I
PW
ML
N
PW
ML
P
[6] Application Circuit
Application circuits shown are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any
infringement of third party patent and other right due to same.
161
CXD3021R
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
COPPER ALLOY
0.5
0.22 0.05
M
0.1
DETAIL A
DETAIL B
0.22 0.05
(0.2)
(
0
.
1
2
5
)
0
.
1
4
5
0
.
0
3
1.7 MAX
1.4 0.1
B
A
120PIN LQFP (PLASTIC)
LQFP-120P-L01
LQFP120-P-1616
0.8g
1
30
31
60
61
90
91
120
0.1
S
S
S
18.0 0.2
16.0 0.1
(
1
7
.
0
)
(
0
.
5
)
0 to 10
0.1 0.05
0
.
6
0
.
1
5
0.25
Package Outline
Unit: mm
120
120PIN LQFP(PLASTIC)
(
0
.
5
)
0 to 10
DETAIL A
1.7MAX
A
S
S
0.10
B
16.0 0.1
18.0 0.2
1
91
90
61
60
31
30
0.5
b
M
S
0.10
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY RESIN
SOLDER
COPPER ALLOY
LQFP-120P-L051
P-LQFP120-16x16-0.5
0.8g
b=0.22 0.05
0
.
1
7
DETAIL B
1.4 0.1
0.1 0.05
(
1
7
.
0
)
1
.
0
0
.
2
(
0
.
1
5
)
(0.2)
+
0
.
0
8
-
0
.
0
5
0.25
0
.
6
0
.
1
5
PDF 
ZIP