Timing Generator for Frame Readout CCD Image Sensor

Description

The CXD3605R is a timing generator IC which

generates the timing pulses for performing frame

readout using the ICX406 CCD image sensor.

Features

· Base oscillation frequency 36MHz

· High-speed/low-speed shutter function

· Supports draft (octuple speed)/AF(auto focus) drive

· Horizontal driver for CCD image sensor

· Vertical driver for CCD image sensor

Applications

Digital still cameras

Structure

Silicon gate CMOS IC

Applicable CCD Image Sensors

ICX406 (Type 1/1.8, 3980K pixels)

Pin Configuration

Absolute Maximum Ratings

· Supply voltage V

0.3 to +7.0

10.0 to V

0.3 to +26.0

· Input voltage

0.3 to V

+ 0.3 V

· Output voltage

0.3 to V

+ 0.3 V

0.3 to V

+ 0.3

0.3 to V

+ 0.3

· Operating temperature

Topr

20 to +75

°C

· Storage temperature

Tstg

55 to +150

°C

Recommended Operating Conditions

· Supply voltage V

3.0 to 5.25

a, V

c, V

3.0 to 3.6

0.0

14.55 to 15.45

7.0 to 8.0

· Operating temperature

Topr

20 to +75

°C

Groups of pins enclosed in the figure indicate

sections for which power supply separation is

possible.

E00Z48

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXD3605R

48 pin LQFP (Plastic)

XSHP

XSHD

XRS

PBLK

CLPDM

OBCLP

ADCLK

CKO

CKI

OSCO

OSCI

MCKO

SSI

SCK

SEN

SSGSL

WEN

ID/EXP

SNCSL

RST

TEST2

SUB

V3B

V3A

V1B

V1A

TEST1

CXD3605R

Block Diagram

V1B

V3A

V1A

WEN

ID/EXP

ADCLK

OBCLP

CLPDM

PBLK

XRS

XSHD

XSHP

MCKO

CKO

CKI

OSCO

OSCI

Pulse Generator

TEST2

TEST1

RST

SUB

V3B

SEN

SCK

SSI

V Driver

SSGSL

SNCSL

1/2

Selector

Latch

SSG

CXD3605R

Pin Description

GND

Internal system reset input.

High: Normal operation, Low: Reset control

Normally apply reset during power-on.

Schmitt trigger input

Control input used to switch sync system. High: CKI sync, Low: MCKO sync

With pull-down resistor

Vertical direction line identification pulse output/exposure time identification pulse
output. Switching possible using the serial interface data. (Default: ID)

Memory write timing pulse output.

Internal SSG enable.

High: Internal SSG valid, Low: External sync valid.

With pull-down resistor

3.3V power supply. (Power supply for common logic block)

3.3V power supply. (Power supply for RG)

CCD reset gate pulse output.

GND

CCD horizontal register clock output.

3.3 to 5.0V power supply. (Power supply for H1/H2)

3.3V power supply. (Power supply for CDS block)

CCD precharge level sample-and-hold pulse output.

CCD data level sample-and-hold pulse output.

Sample-and-hold pulse output for analog/digital conversion phase alignment.

Pulse output for horizontal and vertical blanking period pulse cleaning.

CCD dummy signal clamp pulse output.

GND

CCD optical black signal clamp pulse output.
The horizontal/vertical OB pattern can be changed using the serial interface data.

Clock output for analog/digital conversion IC.
Logical phase adjustment possible using the serial interface data.

GND

Inverter output.

Inverter input.

Inverter output for oscillation.

When not used, leave open or connect a capacitor.

Inverter input for oscillation.

When not used, fix low.

3.3V power supply. (Power supply for common logic block)

System clock output for signal processing IC.

RST

SNCSL

ID/EXP

WEN

SSGSL

XSHP

XSHD

XRS

PBLK

CLPDM

OBCLP

ADCLK

CKO

CKI

OSCO

OSCI

MCKO

No.

Symbol

I/O

Description

CXD3605R

Serial interface data input for internal mode settings.

Schmitt trigger input

Serial interface clock input for internal mode settings.

Schmitt trigger input

Serial interface strobe input for internal mode settings.

Schmitt trigger input

Vertical sync signal input/output.

Horizontal sync signal input/output.

GND

IC test pin 1; normally fixed to GND.

With pull-down resistor

GND (GND for vertical driver)

CCD vertical register clock output.

15.0V power supply. (Power supply for vertical driver)

CCD vertical register clock output.

7.5V power supply.(Power supply for vertical driver)

CCD vertical register clock output.

CCD electronic shutter pulse output.

IC test pin 2; normally fixed to GND.

With pull-down registor

SSI

SCK

SEN

TEST1

V1A

V1B

V3A

V3B

SUB

TEST2

I/O

No.

Symbol

I/O

Description

CXD3605R

Electrical Characteristics

DC Characteristics

(Within the recommended operating conditions)

DD2

DD3

DD4

DD1

, V

DD5

RST, SSI, SCK,
SEN

TEST1, TEST2,
SNCSL, SSGSL

VD, HD

H1, H2

XSHP, XSHD,
XRS, PBLK,
OBCLP, CLPDM,
ADCLK

CKO

MCKO

ID/EXP,
WEN

V1A, V1B,
V3A, V3B,
V2, V4

SUB

IH1

IL1

IH2

IL2

OH1

OL1

OH2

OL2

OH3

OL3

OH4

OL4

OH5

OL5

OH6

OL6

OH7

OL7

OM1

OM2

OSL

OSH

3.0

0.8V

0.7V

0.8V

d 0.8

b 0.8

a 0.8

c 0.8

d 0.8

10.0

5.0

5.4

3.3

3.6

5.25

3.6

0.2V

0.4

5.0

7.2

4.0

Feed current where I

= 1.2mA

Pull-in current where I

= 2.4mA

Feed current where I

= 22.0mA

Pull-in current where I

= 14.4mA

Feed current where I

= 3.3mA

Pull-in current where I

= 2.4mA

Feed current where I

= 3.3mA

Pull-in current where I

= 2.4mA

Feed current where I

= 6.9mA

Pull-in current where I

= 4.8mA

Feed current where I

= 3.3mA

Pull-in current where I

= 2.4mA

Feed current where I

= 2.4mA

Pull-in current where I

= 4.8mA

V1A/B, V2, V3A/B, V4 = 8.25V

V1A/B, V2, V3A/B, V4 = 0.25V

V1A/B, V3A/B = 0.25V

V1A/B, V3A/B = 14.75V

SUB = 8.25V

SUB = 14.75V

Supply
voltage 1

Supply
voltage 2

Supply
voltage 3

Supply
voltage 4

Input
voltage 1

Input
voltage 2

Input/output
voltage

Output
voltage 1

Output
voltage 2

Output
voltage 3

Output
voltage 4

Output
voltage 5

Output
voltage 6

Output
current 1

Output
current 2

Item

Pins

Symbol

Conditions

Min.

Typ.

Max.

Unit

This input pin is a schmitt trigger input.

This input pin is with pull-down registor in the IC.

Note) The above table indicates the condition for 3.3V drive.

CXD3605R

Inverter I/O Characteristics for Oscillation

(Within the recommended operating conditions)

Item

Logical Vth

Input voltage

Output
voltage

Feedback
resistor

Oscillation
frequency

Pins

OSCI

OSCO

OSCI, OSCO

Symbol

LVth

RFB

Conditions

Feed current where I

= 3.6mA

Pull-in current where I

= 2.4mA

= V

d or V

Min.

0.7V

d 0.8

500k

Typ.

d/2

Max.

0.3V

0.4

Unit

MHz

Item

Logical Vth

Input voltage

Input amplitude

Pins

CKI

Symbol

LVth

Conditions

fmax 50MHz sine wave

Min.

0.7V

0.3

Typ.

d/2

Max.

0.3V

Unit

Vp-p

Item

Rise time

Fall time

Output noise voltage

Symbol

TTLM

TTMH

TTLH

TTML

TTHM

TTHL

VCLH

VCLL

VCMH

VCML

Conditions

VL to VM

VM to VH

VL to VH

VM to VL

VH to VM

VH to VL

Min.

200

Typ.

350

Max.

500

1.0

Unit

Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment

(Within the recommended operating conditions)

Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude

is the input amplitude characteristics in the case of input through a capacitor.

Switching Characteristics

(VH = 15.0V, VM = GND, VL = 7.5V)

Note)
1) The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for

measures to prevent electrostatic discharge.

2) For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between

each power supply pin (VH, VL) and GND.

3) To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor.

CXD3605R

Measurement Circuit

10 11 12

CKI

CXD3605R

Serial interface data

+3.3V

7.5V

+15.0V

C1 3300pF

C2 560pF

C3 820pF

C4 8pF

C5 215pF

C6 10pF

R1 30

R2 10

CXD3605R

AC Characteristics

AC characteristics between the serial interface clocks

SSI

0.2V

0.8V

ts2

th1

ts1

ts3

0.8V

SCK

SEN

Symbol

Definition

SSI setup time, activated by the rising edge of SCK

SSI hold time, activated by the rising edge of SCK

SCK setup time, activated by the rising edge of SEN

SEN setup time, activated by the rising edge of SCK

Min.

Typ.

Max.

Unit

Serial interface clock internal loading characteristics (1)

(Within the recommended operating conditions)

th1

Enlarged view

Example: During frame mode

0.2V

ts1

0.2V

V1A

SEN

0.8V

Symbol

Definition

SEN setup time, activated by the falling edge of HD

SEN hold time, activated by the falling edge of HD

Min.

Typ.

Max.

110

Unit

µs

Be sure to maintain a constantly high SEN logic level near the falling edge of the HD in the horizontal period

during which V1A/B and V3A/B values take the ternary value and during that horizontal period.

(Within the recommended operating conditions)

CXD3605R

Serial interface clock output variation characteristics

Normally, the serial interface data is loaded to the CXD3605R at the timing shown in "Serial interface clock

internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is

loaded to the CXD3605R and controlled at the rising edge of SEN. See "Description of Operation".

0.8V

SEN

Output signal

tpdPULSE

Symbol

tpdPULSE

Definition

Output signal delay, activated by the rising edge of SEN

Min.

Typ.

Max.

100

Unit

(Within the recommended operating conditions)

Serial interface clock internal loading characteristics (2)

th1

0.2V

ts1

0.2V

SEN

0.8V

Enlarged view

Example: During frame mode

Symbol

Definition

SEN setup time, activated by the falling edge of VD

SEN hold time, activated by the falling edge of VD

Min.

Typ.

Max.

200

Unit

Be sure to maintain a constantly high SEN logic level near the falling edge of VD.

(Within the recommended operating conditions)

CXD3605R

RST

0.2V

tw1

0.8V

ts1

th1

0.2V

RST loading characteristics

Symbol

Definition

RST pulse width

Min.

Typ.

Max.

Unit

(Within the recommended operating conditions)

VD and HD phase characteristics

Symbol

Definition

VD setup time, activated by the falling edge of HD

VD hold time, activated by the falling edge of HD

Min.

Typ.

Max.

100

Unit

(Within the recommended operating conditions)

MCKO

ts1

th1

0.2V

0.8V

0.2V

HD loading characteristics

Symbol

Definition

HD setup time, activated by the rising edge of MCKO

HD hold time, activated by the rising edge of MCKO

Min.

Typ.

Max.

Unit

MCKO load capacitance = 10pF

(Within the recommended operating conditions)

CXD3605R

Description of Operation

Pulses output from the CXD3605R are controlled mainly by the RST pin and by the serial interface data. The

Pin Status Table is shown below, and the details of serial interface control are described on the following

pages.

Pin Status Table

It is for output. For input, all items are "ACT".

Note) ACT means that the circuit is operating, and DIS means that loading is stopped. L indicates a low

output level, and H a high output level in the controlled status.

Also, VH, VM and VL indicate the voltage levels applied to VH (Pin 42), VM (Pin 38) and VL (Pin 45),

respectively, in the controlled status.

No.

RST

SNCSL

ID/EXP

WEN

SSGSL

XSHP

XSHD

XRS

PBLK

CLPDM

OBCLP

ADCLK

ACT

CKO

CKI

OSCO

OSCI

MCKO

SSI

SCK

SEN

TEST1

V1A

V1B

V3A

V3B

SUB

TEST2

ACT

DIS

Symbol

CAM

SLP

STB

RST

No.

Symbol

CAM

SLP

STB

RST

CXD3605R

Serial Interface Control

The CXD3605R basically loads and reflects the serial interface data sent in the following format in the readout

portion at the falling edge of HD. Here, readout portion specifies the horizontal period during which V1A/B and

V3A/B, etc. take the ternary value.

Note that some items reflect the serial interface data at the falling edge of VD or the rising edge of SEN.

SSI

SCK

SEN

These are two categories of serial interface data: the CXD3605R drive control data (hereafter "control data")

and electronic shutter data (hereafter "shutter data").

The details of each data are described below.

CXD3605R

Control Data

Data

D00

D07

D08

D09

D10

D12

D13

D14

D15

D16

D17

D18

D31

D32

D33

D34

D35

D36

D37

D38

D39

D40

D47

Symbol

CHIP

CTG

MODE

SMD

HTSG

NTPL

FGOB

EXP

PTOB

LDAD

STB

Function

Chip enable

Category switching

Drive mode switching

Electronic shutter mode switching

HTSG control switching

SSG function switching

Wide OBCLP generation switching

ID/EXP output switching

OBCLP waveform patterm switching

ADCLK logic phase adjustment

Standby control

Data = 0

Data = 1

10000001

Enabled

Other values

Disabled

See D08 to D09 CTG.

See D10 to D12 MODE.

OFF

NTSC

PAL

OFF

EXP

See D34 to D35 PTOB.

See D36 to D37 LDAD.

See D38 to D39 STB.

RST

All

See D13 SMD.

CXD3605R

Shutter Data

Data

D00

D07

D08

D09

D10

D19

D20

D31

D32

D41

D42

D47

Symbol

CHIP

CTG

SVD

SHD

SPL

Function

Chip enable

Category switching

Electronic shutter vertical period
specification

Electronic shutter horizontal period
specification

High-speed shutter position
specification

Data = 0

Data = 1

10000001

Enabled

Other values

Disabled

See D08 to D09 CTG.

See D10 to D19 SVD.

See D20 to D31 SHD.

See D32 to D41 SPL.

RST

All

CXD3605R

Detailed Description of Each Data

Shared data: D08 to D09 CTG [Category]
Of the data provided to the CXD3605R by the serial interface, the CXD3605R loads D10 and subsequent
data to each data register as shown in the table below according to the combination of D08 and D09 .

D09

D08

Description of operation

Loading to control data register

Loading to shutter data register

Test mode

D11

D12

D10

D11

D12

D10

Description of operation

Draft mode (default)

AF1 mode

AF2 mode

Frame mode

Draft mode

Frame mode (A field read out)

Frame mode (B field read out)

Test mode

Note that the CXD3605R can apply these categories consecutively within the same vertical period. However,
care should be taken as the data is overwritten if the same category is applied.

Control data: D10 to D12 MODE [Drive mode]
The CXD3605R drive mode can be switched as follows. However, the drive mode bits are located to the
CXD3605R and reflected at the falling edge of VD.

Draft mode is the pulse eliminator drive mode called octuple speed mode in the ICX406. This is a high frame
rate drive mode that can be used for purposes such as monitoring and auto focus (AF).
AF1 and AF2 modes are the pulse eliminator drive modes called by the same names in the ICX406. These
drive modes are based on draft mode, and are used to increase the frame rate for auto focus (AF). In these
modes, the screen is swept in the vertical direction and the center portion lines are cut out.
Frame mode is the ICX406 drive mode in which the data for all lines are read. This drive mode is comprised of
A and B Fields, so when it is established, repeated drive is performed in the manner of A

and so

on.
Frame mode (A or B Field) is the drive mode in which each field can be specified separately.

Control data: D17 NTPL [SSG function switching]
The CXD3605R internal SSG output pattern can be switched as follows. However, the SSG function switching
bits are loaded to the CXD3605R and reflected at the falling edge of VD.

D17

Description of Operation

NTSC equivalent pattern output

PAL equivalent pattern output

VD period in each pattern is defined as follows.

See the Timing Charts for the actual operation.

NTSC equivalent pattern

PAL equivalent pattern

Frame mode

1012H + 1672ck

944H + 464ck

Draft mode

224H + 1372ck

269H + 2039ck

AF1 mode

112H + 1372ck

134H + 2354ck

AF2 mode

56H + 686ck

67H + 1178ck

CXD3605R

Control data: D32 FGOB [Wide OBCLP generation]

This controls wide OBCLP generation during the vertical OPB period. See the Timing Charts for the actual

operation. The default is "OFF".

D32

Description of operation

Wide OBCLP generation OFF

Wide OBCLP generation ON

Control data: D34 to D35 PTOB [OBCLP waveform pattern]

This indicates the OBCLP waveform pattern. The default is "Normal".

D35

D34

Waveform pattern

(Normal)

(Shifted rearward)

(Shifted forward)

(Wide)

Control data: D36 to D37 LOAD [ADCLK logical phase]

This indicates the ADCLK logic phase adjustment data. The default is 90° relative to MCKO.

D37

D36

Degree of adjustment (°)

180

270

Control data: D38 to D39 STB [Standby]

The operating mode is switched as follows. However, the standby bits are loaded to the CXD3605R and

control is applied immediately at the rising edge of SEN.

D39

D38

Symbol

CAM

SLP

STB

Operating mode

Normal operating mode

Sleep mode

Standby mode

See the Pin Status Table for the pin status in each mode.

CXD3605R

Control data/shutter data: [Electronic shutter]
The CXD3605R realizes various electronic shutter functions by using control data D13 SMD and D14 HTSG
and shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL.
These functions are described in detail below.
First, the various modes are shown below.
These modes are switched using control data D13 SMD.

D13

Description of operation

Electronic shutter stopped mode

Electronic shutter mode

The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example.
However, MSB (D31) is a reserve bit for the future specification, and it is handled as a dummy on this IC.

MSB

LSB

D29

D28

D31

D30

D27

D26

D25

D24

D23

D22

D21

D20

SHD is expressed as 1C3h .

[Electronic shutter stopped mode]
During this mode, all shutter data items are invalid.
SUB is not output in this mode, so the shutter speed is the accumulation time for one field.

[Electronic shutter mode]
During this mode, the shutter data items have the following meanings.

Note) The bit data definition area is assured in terms of the CXD3605R functions, and does not assure the

CCD characteristics.

The period during which SVD and SHD are specified together is the shutter speed. An image of the exposure

time calculation formula is shown below. In actual operation, the precise exposure time is calculated from the

operating frequency, VD and HD periods, decoding value during the horizontal period, and other factors.

(Exposure time) = SVD + {(number of HD per 1V) (SHD + 1)}

Concretely, when specifying high-speed shutter, SVD is set to "000h". (See the figure.) During low-speed

shutter, or in other words when SVD is set to "001h" or higher, the serial interface data is not loaded until this

period is finished.

The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of

horizontal periods applied to SHD can be considered as (number of SUB pulses 1).

Symbol

SVD

SHD

SPL

Data

D10 to D19

D20 to D31

D32 to D41

Description

Number of vertical periods specification (000h

SVD

3FFh)

Number of horizontal periods specification (000h

SHD

7FFh)

Vertical period specification for high-speed shutter operation (000h

SPL

3FFh)

CXD3605R

SHD

V1A

SUB

WEN

SMD

000h

002h

SVD

050h

10Fh

SHD

SVD

EXP

Exposure time

SPL

001

002

000

SHD

V1A

SUB

WEN

SMD

000h

001h

SPL

000h

002h

SVD

0A3h

10Fh

SHD

EXP

Exposure time

SVD

Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the

low-speed shutter period.

In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods.

Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVD.

Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed

shutter to high-speed shutter or vice versa.

CXD3605R

V1A

SUB

WEN

HTSG

SMD

Vck

Exposure time

EXP

[HTSG control mode]

This mode controls the V1A/B and V3A/B ternary level outputs (readout pulse block) using D14 HTSG.

D14

Description of operation

Readout pulse (SG) normal operation

HTSG control mode

[EXP pulse]

The ID/EXP pin (Pin 4) output can be switched between the ID pulse or the EXP pulse using D33 EXP. The

default is the "ID" pulse. See the Timing Charts for the ID pulse. The EXP pulse indicates the exposure time

when it is high. The transition point is the last SUB pulse falling edge, and midpoint value (1338ck) of each

V1A/B and V3A/B ternary out put falling edge. When there is no SUB pulse, the later ternary output falling

edge (1416ck) is used. See the EXP pulse indicated in the explanatory diagrams under [Electronic shutter] for

an image of operation.

Note that the above specification is based on draft mode. For frame mode, the former value is 1260ck and the

latter value is 1416ck.

CXD3605R

SUB

OBCLP

CLPDM

V1A

V1B

V3A

V3B

CCD OUT

1547

1719

1712

1714

1716

1718

1720

1709

1711

1713

1715

3
1

2468

468

13579

PBLK

ID/EXP

WEN

Field

B Field

1013

943

1013

High-speed sweep block

The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in e

ach horizontal period.

ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT con

tains the B component.

VD of this chart is NTSC equivalent pattern (1012H + 1672ck units). For PAL equivalent pattern, it is 944H + 464ck units.

Chart-1

Vertical Direction Timing Chart

MODE

Frame mode

Applicable CCD image sensor

·
ICX406

CXD3605R

SUB

V1A

V3A

V3B

OBCLP

CLPDM

ID/EXP

PBLK

V1B

CCD OUT

14
5

10
1

6
1

WEN

218

1717

1710

1713

1706

1717

1710

1713

1706

226

The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in e

ach horizontal period.

ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT con

tains the B component.

VD of this chart is NTSC equivalent pattern (224H + 1372ck + 1372ck units). For PAL equivalent pattern, it is 269H + 2039ck uni

ts.

Chart-2

Vertical Direction Timing Chart

MODE

Draft mode

Applicable CCD image sensor

·
ICX406

CXD3605R

SUB

OBCLP

CLPDM

V1A

V1B

V3A

V3B

CCD OUT

PBLK

ID/EXP

WEN

106

High-speed

sweep block

Frame shift block

High-speed

sweep block

Frame shift block

The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in e

ach horizontal period.

ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT con

tains the B component.

240 stages are fixed for high-speed sweep block; 232 stages are fixed for frame shift block.

VD of this chart is NTSC equivalent pattern (112H + 1372ck units). For PAL equivalent pattern, it is 134H + 2354ck units.

Chart-3

Vertical Direction Timing Chart

MODE

AF1 mode

Applicable CCD image sensor

·
ICX406

CXD3605R

SUB

OBCLP

CLPDM

V1A

High-speed sweep block

V1B

V3A

V3B

CCD OUT

PBLK

ID/EXP

WEN

Frame shift block

High-speed sweep block

Frame shift block

The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in e

ach horizontal period.

ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT con

tains the B component.

360 stages are fixed for high-speed sweep block; 360 stages are fixed for frame shift block.

VD of this chart is NTSC equivalent pattern (56H + 686ck units). For PAL equivalent pattern, it is 67H + 1178ck units.

Chart-4

Vertical Direction Timing Chart

MODE

AF2 mode

Applicable CCD image sensor

·
ICX406

CXD3605R

MCKO

V1A/B

V3A/B

SUB

PBLK

OBCLP

(1)

OBCLP

(2)

OBCLP

(3)

OBCLP

(4)

OBCLP

CLPDM

(2669)

100

200

150

250

300

350

400

450

500

550

ID/EXP

WEN

317

345

361

365

188

347

343

319

252

156

220

343

284

124

232

168

124

The HD of this chart indicates the actual CXD3605R load timing.

The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.

The HD fall period should be between approximately 3.3 to 17.6µ

(when the drive frequency is 18MHz). This chart shows a period

of 115ck (6.4µ

s). Internal SSG is at this timing.

SUB is output at the timing shown above when output is controlled by the serial interface data.

ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-1.

Chart-5

Horizontal Direction Timing Chart

MODE

Frame mode

Applicable CCD image sensor

·
ICX406

CXD3605R

MCKO

V1A/B

V3A/B

SUB

PBLK

OBCLP

(1)

OBCLP

(2)

OBCLP

(3)

OBCLP

(4)

OBCLP

CLPDM

(2669)

100

200

150

250

300

350

400

450

500

550

ID/EXP

WEN

317

345

361

365

347

343

319

108

100

343

232

168

124

156

132

172

148

164

124

180

140

220

196

212

228

188

244

204

284

260

300

276

292

252

308

268

236

The HD of this chart indicates the actual CXD3605R load timing.

The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.

The HD fall period should be between approximately 3.3 to 17.6µ

(when the drive frequency is 18MHz). This chart shows a period

of 115ck (6.4µ

s). Internal SSG is at this timing.

SUB is output at the timing shown above when output is controlled by the serial interface data.

ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-2, 3 and 4.

Chart-6

Horizontal Direction Timing Chart

MODE

Draft mode, AF1 mode, AF2 mode

Applicable CCD image sensor

·
ICX406

CXD3605R

MCKO

V1A/B

V3A/B

SUB

PBLK

OBCLP

CLPDM

(2669)

100

200

150

250

300

350

400

450

500

550

ID/EXP

WEN

317

345

361

365

232

168

172

228

284

340

396

452

508

564

172

228

284

340

396

452

508

564

144

200

256

312

368

424

480

536

144

200

256

312

368

424

480

536

The HD of this chart indicates the actual CXD3605R load timing.

The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.

The HD fall period should be between approximately 3.3 to 17.6µ

(when the drive frequency is 18MHz). This chart shows a period

of 115ck (6.4µ

s). Internal SSG is at this timing.

SUB is output at the timing shown above when output is controlled by the serial interface data.

ID/EXP of this chart shows ID.

High-speed sweep of V1A/B, V2, V3A/B, V4 is performed up to 72H of 2660ck (#1739).

Chart-7

Horizontal Direction Timing Chart

(High-speed sweep: C)

MODE

Frame mode

Applicable CCD image sensor

·
ICX406

CXD3605R

MCKO

V1A/B

V3A/B

SUB

PBLK

OBCLP

CLPDM

(2669)

100

200

150

250

300

350

400

450

500

550

ID/EXP

WEN

317

345

361

365

232

168

124

100

124

164

188

228

252

292

316

356

380

420

444

484

508

548

108

148

172

212

236

276

300

340

364

404

428

468

492

532

556

132

156

196

220

260

284

324

348

388

412

452

476

516

540

140

180

204

244

268

308

332

372

396

436

460

500

524

The HD of this chart indicates the actual CXD3605R load timing.

The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.

The HD fall period should be between approximately 3.3 to 17.6µ

(when the drive frequency is 18MHz). This chart shows a period

of 115ck (6.4µ

s). Internal SSG is at this timing.

SUB is output at the timing shown above when output is controlled by the serial interface data.

ID/EXP of this chart shows ID. PBLK, OBCLP, ID/EXP and WEN are output at the timing shown above at the position shown in Chart-

2, 3 and 4.

Frame shift of V1A/B, V2, V3A/B and V4 is performed up to 7H 1563ck (#232) in AF1 mode and 10H 1688ck (#360) in AF2 mode.

In addition, high-speed sweep is performed up to 111H 2015ck (#240) in AF1 mode and 55H 1688ck (#360) in AF2 mode.

Chart-8

Horizontal Direction Timing Chart

(Frame shift: F)

(High-speed sweep: G)

MODE

AF1 mode, AF2 mode

Applicable CCD image sensor

·
ICX406

CXD3605R

Field]

[B Field]

V3B

V1A

V1B

V3A

V1A

V1B

V3A

(2669)

1104

1136

1168

12001202

1260

1292

124

156

188

220

252

284

The HD of this chart indicates the actual CXD3605R load timing.

The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.

The HD fall period should be between approximately 3.3 to 17.6µ

(when the drive frequency is 18MHz). This chart shows a period

of 115ck (6.4µ

s). Internal SSG is at this timing.

Chart-9

Horizontal Direction Timing Chart

MODE

Frame mode

Applicable CCD image sensor

·
ICX406

CXD3605R

V3B

V1A

V1B

V3A

(2669)

1104

1136

1168

12001202

13561358

1260

1292

1324

1416

108

124

140

156

172

100

116

132

148

164

180

The HD of this chart indicates the actual CXD3605R load timing.

The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.

The HD fall period should be between approximately 3.3 to 17.6µ

(when the drive frequency is 18MHz). This chart shows a period

of 115ck (6.4µ

s). Internal SSG is at this timing.

Chart-10

Horizontal Direction Timing Chart

MODE

Draft mode

Applicable CCD image sensor

·
ICX406

CXD3605R

V3B

V1A

V1B

V3A

(2669)

1104

1136

1168

12001202

13561358

1260

1292

1324

1416

108

124

140

156

172

100

116

132

148

164

180

188

204

220

236

252

268

284

300

196

212

228

244

260

276

292

308

1448

1464

1480

1496

1512

1528

1544

1560

1456

1472

1488

1504

1520

1536

1552

1568

The HD of this chart indicates the actual CXD3605R load timing.

The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.

The HD fall period should be between approximately 3.3 to 17.6µ

(when the drive frequency is 18MHz). This chart shows a period

of 115ck (6.4µ

s). Internal SSG is at this timing.

Chart-11

Horizontal Direction Timing Chart

MODE

AF1 mode, AF2 mode

Applicable CCD image sensor

·
ICX406

CXD3605R

V1A

V1B

V3A

V3B

SUB

Mechanical

shutter

Exposure

time

CCD OUT

MODE

SMD

SHD

Open

000

111

050h

50h

050h

00h

000h

50h

This chart is a drive timing chart example of electronic shutter normal operation.

Data exposed at D includes the blooming component. For details, see the CCD image sensor data sheet.

The CXD3605R does not generate the pulse to control mechanical shutter operation.

The switching timing of drive mode and electronic shutter data is not the same.

Chart-13

Vertical Direction Sequence Chart

MODE

Draft

Frame

Draft

Applicable CCD image sensor

·
ICX406

CXD3605R

Application Circuit Block diagram

37 48

31 32

MCKO

CKO

D OUT

ADCLK

OBCLP

CLPDM

PBLK

XRS

XSHD

XSHP

SCK

SEN

SSI

TEST2

TEST1

OSCO

CKI

OSCI

CCD OUT

V-Dr

SSG

SSGSL

SNCSL

RST

WEN

ID/EXP

V1B

V1A

SUB

V3B

V3A

CCD

ICX406

CDS/ADC Block

CXD3605R

Controller

Signal Processor Block

Notes for Power-on

Of the three 7.5V, +15.0V, 3.3V power supplies, be sure to start up the 7.5V and +15.0V power supplies in

the following order to prevent the SUB pin of the CCD image sensor from going to negative potential.

15.0V

7.5V

20%

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

CXD3605R

Sony Corporation

Package Outline

Unit: mm

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN

COPPER ALLOY

PACKAGE STRUCTURE

48PIN LQFP (PLASTIC)

9.0

0.2

7.0

0.1

(0.22)

0.18 0.03

+ 0.08

0.2g

LQFP-48P-L01

P-LQFP48-7x7-0.5

(8.0)

0.5

0.2

0.127 0.02

+ 0.05

1.5 0.1

+ 0.2

0.1

PALLADIUM PLATING

NOTE: Dimension "

" does not include mold protrusion.

0.1

0.5

0.2

to 10

DETAIL A

0.13 M

0.5

DETAIL B: PALLADIUM

0.127

0.04

0.18

0.03

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXD3605R

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXD3605R