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Электронный компонент: CXG1091TN

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SP4T GSM Dualband Antenna Switch 5V + Logic
Description
The SP4T + logic is a high power antenna switch
MMIC for use in dualband GSM handsets.
One Antenna can be routed to either of the 2 Tx or
2 Rx ports. It operates from 3 CMOS control lines (Tx
ON/OFF and GSM900/1800 and Standby).
The Sony's J-FET process is used for low insertion
loss.
Features
3 CMOS compatible control lines
34dBm power handling at 5.0V (GSM900)
Low second harmonic < 30dBm at 34dBm
Small package size: 16-pin TSSOP (3.9
4.1mm)
Applications
Dualband handsets using combinations of GSM900/GSM1800/GSM1900 and DECT
Structure
GaAs J-FET MMIC
Truth Table
1
E99758A9Y-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXG1091TN
16 pin TSSOP (Plastic)
Absolute Maximum Ratings (Ta = 25C)
Bias voltage
V
DD
7
V
Control voltage
Vctl
5
V
Operating temperature Topr
35 to +85
C
Storage temperature
Tstg
65 to +150
C
GaAs MMICs are ESD sensitive devices. Special handling precautions are required.
On Pass
Ant.-Tx1 GSM900
Ant.-Tx2 GSM1800
Ant.-Rx1 GSM900/1800
Ant.-Rx2 GSM900/1800
OFF
Band select
H
L
L
H
--
Tx (H)/Rx (L)
H
H
L
L
--
Standby
H
H
H
H
L
For the availability of this product, please contact the sales office.
2
CXG1091TN
Electrical Characteristics
(Ta = 25C)
1
Pin = 34dBm, 880 to 915MHz, V
DD
= 5.0V
2
Pin = 32dBm, 1710 to 1785MHz, V
DD
= 5.0V
3
Pin = 10dBm, 925 to 960MHz
4
Pin = 10dBm, 1805 to 1880MHz
Note) Harmonics measured with Tx inputs harmonically matched.
CMOS Logic Values
(Ta = 25C)
Logic
High
Low
Min.
2.4V
Typ.
3.0V
0.0V
Max.
0.8V
Item
Insertion loss
Isolation
VSWR
Harmonics
Note)
P
1dB
compression input power
Switching speed
Control current
Supply current
Leakage current
IL
ISO.
VSWR
2fo
3fo
P
1dB
TSW
I
CTL
I
DD
I
IK
Port
Ant-Tx1, Tx2
Ant-Rx1, Rx2
Ant-Tx1, Tx2
Ant-Rx1, Rx2
Ant-Tx1, Tx2
Ant-Tx1, Tx2
Condition
1
2
3
4
1
2
3
4
1
,
2
1
,
2
1
,
2
STBY = H
STBY = L
Min.
20
17
24
20
Typ.
0.5
0.6
0.55
0.7
25
20
28
24
1.2
36
1
100
0.5
Max.
0.75
0.85
0.75
0.9
30
30
1
50
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dBm
dBm
dBm
s
A
mA
A
Symbol
3
CXG1091TN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Tx1
GND
Tx2
GND
Rx1
GND
Rx2
STDBY
GND
GND
ANT
GND
V
DD
GND
Band Select
Tx/Rx
100pF
100pF
100pF
100pF
100pF
100pF
100pF
100pF
100pF
( )
RRF
Recommended Circuit
PCB Layout Recommendations
As indicated in the diagram AC coupling capacitors are necessary to the Ant, Tx1, Tx2, Rx1, Rx2 pins.
Ground plane should be included under the device and all ground pins connected to this.
RRF (68k
) is used to be stabilized the electrical characteristics at high power signal input.
4
CXG1091TN
Package Outline
Unit: mm
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
COPPER ALLOY
PACKAGE STRUCTURE
0.03g
TSSOP-16P-L01
16PIN TSSOP(PLASTIC)
0.2 0.02
0.22 0.03
+ 0.036
0
.
1


0
.
0
1
0
.
1
2


0
.
0
2
+

0
.
0
2
6
DETAIL B
X
X

0
.
1
1
0.5
0.08
S A
M
0.1
A B
X4
S
B
0.2
A B
X2
S
0
.
1
16
A
2.05
4.1
9
0 to 8
2
.
9
3
.
9
0.1 0.05
0
.
4
5


0
.
1
0.25
(
3
.
0
)
0.08 S
S
1.2MAX
B
8