CXG1212UR(EF).b..(1).fm
- 1 -
PE05729-PS
Preliminary
This IC is ESD sensitive device. Special handling precautions are required.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license
by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating
the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Preliminary
CXG1212UR
High Power 3P3T Switch with Logic Control
Description
This IC can be used in wireless communication systems, for example, CDMA EV-DO handsets.
The IC has on-chip logic for operation with 3 CMOS control inputs.
The Sony JPHEMT process is used for low insertion loss and on-chip logic circuit.
(Applications: Antenna switch for cellular handsets, CDMA, EV-DO)
Features
Low insertion loss: 0.3dB@900MHz
3 CMOS compatible control line
Package
Small package size: 20-pin UQFN
Structure
GaAs JPHEMT MMIC
Absolute Maximum Ratings
(Ta = 25
C)
Bias voltage
V
DD
7
V
Control voltage
Vctl
5
V
Operating temperature
Topr
35 to +85
C
Storage temperature
Tstg
60 to +150
C
RF input power
Pin = 37dBm
CXG1212UR
- 2 -
Block Diagram and Recommended Circuit
When using this IC, the following external components should be used:
C
RF
: This capacitor is used for RF decoupling and must be used for all applications.
Cbypass: This capacitor is used for DC line filtering.
Truth Table
Cbypass
(100pF)
17
16
20
15
5
GND
4
RF1 (CDMA1)
3
GND
1
GND
CTLA
CTLB
CTLC
V
DD
GND
RF5 (Ext)
6
GND
RF3 (GPS)
GND
9
GND
RF4 (Main-Ant)
13
GND6
12
RF6 (Sub-Ant)
11
GND
C
RF
14
GND4
C
RF
8
C
RF
C
RF
2
C
RF
RF2 (CDMA2)
C
RF
19
F10
10
7
18
F8
F9
F3
F12
F13
F11
F4
F2
F1
F5
F6
F7
State CTLA CTLB CTLC
Mode
ON state
F1
F2
F3
F4
F5
F6
F7
F8
F9 F10 F11 F12 F13
1
L
L
L
CDMA1 Ext
RF1 RF5 OFF ON OFF OFF OFF OFF OFF OFF ON ON ON OFF ON
2
L
L
H
CDMA1 Ext
CDMA2 Sub
RF1 RF5
RF2 RF6
OFF ON ON OFF OFF OFF OFF OFF OFF ON ON OFF OFF
3
H
L
L
CDMA1 Main RF1 RF4 ON OFF OFF OFF OFF OFF OFF OFF ON ON OFF ON ON
4
H
L
H
CDMA1 Main
CDMA2 Sub
RF1 RF4
RF2 RF6
ON OFF ON OFF OFF OFF OFF OFF OFF ON OFF ON OFF
5
L
H
L
GPS Ext
RF3 RF5 OFF OFF OFF OFF OFF OFF ON ON ON OFF ON OFF ON
6
L
H
H
CDMA2 Ext
RF2 RF5 OFF OFF OFF ON OFF OFF OFF ON OFF ON ON OFF ON
7
H
H
L
GPS Main
RF3 RF4 OFF OFF OFF OFF ON OFF OFF ON ON OFF OFF ON ON
8
H
H
H
GPS Sub
RF3 RF6 OFF OFF OFF OFF OFF ON OFF ON ON OFF ON ON OFF
CXG1212UR
- 3 -
DC Bias Conditions
(Ta = 25
C)
Pin Description
Item
Min.
Typ.
Max.
Unit
Vctl (H)
2.0
2.85
3.2
V
Vctl (L)
0
--
0.5
V
V
DD
2.6
2.85
3.2
V
Pin No.
Symbol
Pin No.
Symbol
1
GND
11
GND
2
RF2 (CDMA2)
12
RF6 (Sub-Ant)
3
GND
13
GND6
4
RF1 (CDMA1)
14
GND4
5
GND
15
RF4 (Main-Ant)
6
GND
16
GND
7
RF3 (GPS)
17
V
DD
8
GND
18
CTLA
9
GND
19
CTLB
10
RF5 (Ext)
20
CTLC
CXG1212UR
- 4 -
Electrical Characteristics
(Ta = 25
C, V
DD
= 2.85V)
*1
Pin = 25dBm, 0/2.85V control, V
DD
= 2.85V, 900MHz
*2
Pin = 25dBm (900MHz) + 25dBm (901MHz), 0/2.85V control, V
DD
= 2.85V
*3
Pin = 25dBm, 0/2.85V control, V
DD
= 2.85V, 1.9GHz
*4
Pin = 25dBm (1.9GHz) + 25dBm (1.901GHz), 0/2.85V control, V
DD
= 2.85V
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Insertion loss
IL
900MHz
0.30
0.55
dB
1.5GHz
0.40
0.65
dB
1.9GHz
0.50
0.75
dB
Isolation
ISO.
900MHz
23
30
dB
1.5GHz
20
30
dB
1.9GHz
18
25
dB
VSWR
VSWR
50
1.2
--
Harmonics
2fo
*1
75
60
dBc
*3
75
60
dBc
3fo
*1
75
60
dBc
*3
75
60
dBc
Input IP3
IIP3
*2
55
65
dBm
*4
55
65
dBm
1dB compression input power
P1dB
V
DD
= 2.85V
32
dBm
Switching speed
TSW
4
10
s
Bias current
I
DD
V
DD
= 2.85V
270
450
A
Control current
Ictl
Vctl (H) = 2.85V
15
45
A
CXG1212UR
- 5 -
Sony Corporation
Package Outline
(Unit: mm)
PIN 1 INDEX
C
0.1
S A-B
0.4
0.05 M
S
C
C
A-B
S
0.05 S
MAX0.02
+ 0.09
20PIN UQFN (PLASTIC)
0.25 0.03
+ 0.09
0.14 0.03
x 4
2.7
1
5
11
15
16
20
6
10
2.7
S
0.4 0.1
1.3
0.55 0.05
4-R0.3
0.26
A
B
0.25
0.14
0.07
0.18
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SOLDER PLATING
COPPER ALLOY
0.02g
PACKAGE STRUCTURE
UQFN-20P-01
PACKAGE MASS
TERMINAL SECTION
Note:Cutting burr of lead are 0.05mm MAX.
Solder Plating
LEAD PLATING SPECIFICATIONS
ITEM
LEAD MATERIAL
COPPER ALLOY
SOLDER COMPOSITION
Sn-Bi Bi:1-4wt%
PLATING THICKNESS
5-18m
SPEC.
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