Description
The CXK77B1810AGB-5/6 is a high speed 1M bit
Bi-CMOS synchronous static RAM organized as
65536 words by 18 bits. This SRAM integrates input
registers, high speed SRAM and write buffer onto a
single monolithic IC and features the delayed write
system to reduce the dead cycles.
Features
Fast cycle time
(Cycle)
(Frequency)
CXK77B1810AGB-5
5ns
200MHz
-6
6ns
167MHz
Inputs and outputs are GTL/HSTL compatible
Controlled Impedance Driver
Single 3.3V power supply: 3.3V0.15V
Byte-write possible
OE asynchronization
JTAG test circuit
Package 119TBGA
4 kinds of synchronous operation mode
Register-Register mode (R-R mode)
Register-Flow Thru mode (R-F mode)
Register-Latch mode (R-L mode)
Dual clock mode (D-C mode)
Function
65536 word x 18bit High Speed Bi-CMOS Synchronous SRAM
Structure
Silicon gate Bi-CMOS IC
1
CXK77B1810AGB
-5/6
119 pin BGA (Plastic)
PE96811
High Speed Bi-CMOS Synchronous Static RAM
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Preliminary
For the availability of this product, please contact the sales office.
3
CXK77B1810AGB
Pin Configuration (Top View)
V
DD
Q
NC
NC
DQb
NC
V
DD
Q
NC
DQb
V
DD
Q
NC
DQb
V
DD
Q
DQb
NC
NC
NC
V
DD
Q
A
DQx
K
K
C
C
VREF
W
Address Input
Data I/O in byte
(a to b)
Positive Clock
Negative Clock
Output Positive Clock(
)
Output Negative
Clock(
)
Input Reference
Write Enable
BWX
S
G
ZZ
TCK
TMS
TDI
TDO
Byte Write Enable
(a to b)
Chip Select
Asyn Output Enable
Sleep Mode Select
JTAG Clock
JTAG Mode Select
JTAG Data In
JTAG Data Out
V
DD
V
DD
Q
V
SS
M1, M2
ZQ
NC
+3.3V power supply
Output power supply
Ground
Mode Select
Output Impedance
Control
No Connect
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
A
NC
A
NC
DQb
NC
DQb
NC
V
DD
DQb
NC
DQb
NC
DQb
A
A
TMS
A
NC
A
V
SS
V
SS
V
SS
BWb
V
SS
VREF
V
SS
V
SS
V
SS
V
SS
V
SS
M1
A
TDI
NC
NC
V
DD
ZQ
S
G
C
C
V
DD
K
K
W
A
A
V
DD
NC
TCK
A
NC
A
V
SS
V
SS
V
SS
V
SS
V
SS
VREF
V
SS
BWa
V
SS
V
SS
V
SS
M2
A
TDO
A
NC
A
DQa
NC
DQa
NC
DQa
V
DD
NC
DQa
NC
DQa
NC
A
A
NC
V
DD
Q
NC
NC
NC
DQa
V
DD
Q
DQa
NC
V
DD
Q
DQa
NC
V
DD
Q
NC
DQa
NC
ZZ
V
DD
Q
1
2
3
4
5
6
7
Pin Description
Symbol
Description
Symbol
Description
Symbol
Description
(
) These pins should be tied to V
DD
or V
SS
except D-C mode.
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