16Mb DDR1, rev 1.3
1 / 23
July 19, 2002
CXK77L18162GB
SONY
25/27/3
16Mb DDR1 HSTL High Speed Synchronous SRAM (1M x 18)
Preliminary
Description
Features
3 Speed Bins
Cycle Time / Access Time
Data Rate
-25
2.5ns / 1.8ns
800 Mbps
-27
2.7ns / 1.9ns
740 Mbps
-3
3.0ns / 1.9ns
666 Mbps
Single 1.8V power supply (V
DD
): 1.8V
0.1V
Dedicated output supply voltage (V
DDQ
): 1.5V to 1.8V typical
HSTL-compatible I/O interface with dedicated input reference voltage (V
REF
): V
DDQ
/2 typical
DDR1 functional compatibility
Register - Register (R-R) read protocol
Late Write (LW) write protocol
Single Data Rate (SDR) and Double Data Rate (DDR) data transfers
Burst capability via Continue commands
Linear or interleaved burst order, selectable via dedicated mode pin (LBO)
Full read/write coherency
Two cycle deselect
Differential input clocks (CK/CK)
Positive and negative output clocks (CQ/CQ) - one pair per 18 bits of output data (DQ)
Asynchronous output enable (G)
Programmable output driver impedance
JTAG boundary scan (subset of IEEE standard 1149.1)
153 pin (9x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package
The CXK77L18162GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 1,048,576 words
by 18 bits. This synchronous SRAM integrates input registers, high speed RAM, output registers, and a two-deep write buffer
onto a single monolithic IC. Single Data Rate (SDR) and Double Data Rate (DDR) Register - Register (R-R) Read operations
and Late Write (LW) Write operations are supported, providing a flexible, high-performance user interface. Continue operations
are supported, providing burst capability. Positive and negative output clocks are provided for applications requiring source-
synchronous operation.
All address and control input signals except the G output enable signal are registered on the rising edge of the CK differential
input clock. All commands are input via the B(1:3) control signals.
During SDR read operations, output data is driven valid once, from the rising edge of CK, one full clock cycle after the address
is registered. During DDR read operations, output data is driven valid twice, first from the rising edge of CK and then from the
falling edge of CK, beginning one full clock cycle after the address is registered. In both cases, output data transitions are closely
aligned with output clock transitions.
During SDR write operations, input data is registered once, on the rising edge of CK, one full clock cycle after the address is
registered. During DDR write operations, input data is registered twice, first on the rising edge of CK and then on the falling
edge of CK, beginning one full clock cycle after the address is registered.
Output drivers are series terminated, and output impedance is programmable via the ZQ input pin. By connecting an external
control resistor RQ between ZQ and V
SS
, the impedance of all data and clock output drivers can be precisely controlled.
400 MHz operation (800 Mbps) is obtained from a single 1.8V power supply. JTAG boundary scan interface is provided using
a subset of IEEE standard 1149.1 protocol.
SONY
CXK77L18162GB
Preliminary
16Mb DDR1, rev 1.3
2 / 23
July 19, 2002
Pin Assignment (Top View)
Notes:
1. Pad Location 6L is a true no-connect. However, it may be defined as a mode pin in future versions of DDR SRAMs.
2. Pad Location 7U must be left unconnected. It is used by Sony for internal test purposes.
1
2
3
4
5
6
7
8
9
A
V
SS
V
DDQ
SA
SA
ZQ
SA
SA
V
DDQ
V
SS
B
NC
DQ
SA
V
SS
B1
V
SS
SA
NC
DQ
C
V
SS
V
DDQ
SA
SA
G
SA
SA
V
DDQ
V
SS
D
DQ
NC
SA
V
SS
V
DD
V
SS
SA
DQ
NC
E
V
SS
V
DDQ
V
SS
V
DD
V
REF
V
DD
V
SS
V
DDQ
V
SS
F
NC
CQ
NC
V
DD
V
DD
V
DD
DQ
NC
DQ
G
V
SS
V
DDQ
V
SS
V
SS
CK
V
SS
V
SS
V
DDQ
V
SS
H
DQ
NC
DQ
V
DD
CK
V
DD
NC
DQ
NC
J
V
SS
V
DDQ
V
SS
V
DD
V
DD
V
DD
V
SS
V
DDQ
V
SS
K
NC
DQ
NC
V
SS
B2
V
SS
DQ
NC
DQ
L
V
SS
V
DDQ
V
SS
LBO
B3
NC
(1)
V
SS
V
DDQ
V
SS
M
DQ
NC
DQ
V
DD
V
DD
V
DD
NC
CQ
NC
N
V
SS
V
DDQ
V
SS
V
DD
V
REF
V
DD
V
SS
V
DDQ
V
SS
P
NC
DQ
SA
(x18)
V
SS
V
DD
V
SS
SA
NC
DQ
R
V
SS
V
DDQ
V
DD
SA
SA1
SA
V
DD
V
DDQ
V
SS
T
DQ
NC
SA
V
SS
SA0
V
SS
SA
DQ
NC
U
V
SS
V
DDQ
TMS
TDI
TCK
TDO
RSVD
(2)
V
DDQ
V
SS
SONY
CXK77L18162GB
Preliminary
16Mb DDR1, rev 1.3
3 / 23
July 19, 2002
Pin Description
Symbol
Type
Description
SA
Input
Synchronous Address Inputs - Registered on the rising edge of CK.
SA1, SA0
Input
Synchronous Address Inputs (1:0) - Registered on the rising edge of CK. Initialize burst counter.
DQ
I/O
Synchronous Data Inputs / Outputs - Registered on the rising edge of CK during SDR Write opera-
tions. Registered on the rising and falling edges of CK during DDR Write operations. Driven from
the rising edge of CK during SDR Read operations. Driven from the rising and falling edges of CK
during DDR Read operations.
CK, CK
Input
Differential Input Clocks
CQ, CQ
I/O
Output Clocks
B1, B2, B3
Input
Synchronous Control Inputs (1:3) - Registered on the rising edge of CK. Specify the type of opera-
tion (SDR Read, SDR Write, DDR Read, DDR Write, Continue, or Deselect) to be executed by the
SRAM. See the Clock Truth Table and State Diagram sections for further information.
G
Input
Asynchronous Output Enable Input - Deasserted (high) disables the data output drivers.
LBO
Input
Burst Order Select Input - This mode pin must be tied "high" or "low" at power-up.
LBO = 0 selects Linear burst order
LBO = 1 selects Interleaved burst order
ZQ
Input
Output Impedance Control Resistor Input - This pin must be connected to V
SS
through an external
control resistor RQ to program data and clock output driver impedance. See the Programmable Out-
put Driver Impedance section for further information.
V
DD
1.8V Core Power Supply - Core supply voltage.
V
DDQ
Output Power Supply - Output buffer supply voltage.
V
REF
Input Reference Voltage - Input buffer threshold voltage.
V
SS
Ground
TCK
Input
JTAG Clock
TMS
Input
JTAG Mode Select - Weakly pulled "high" internally.
TDI
Input
JTAG Data In - Weakly pulled "high" internally.
TDO
Output
JTAG Data Out
RSVD
Reserved - This pin is used for Sony test purposes only. It must be left unconnected.
NC
No Connect - These pins are true no-connects, i.e. there is no internal chip connection to these pins.
They can be left unconnected or tied directly to V
DD
, V
DDQ
, or V
SS
.
SONY
CXK77L18162GB
Preliminary
16Mb DDR1, rev 1.3
4 / 23
July 19, 2002
Clock Truth Table
CK
B1
(t
n
)
B2
(t
n
)
B3
(t
n
)
Previous
Operation
Current Operation
DQ
(t
n
)
DQ
(t
n+
)
DQ
(t
n+1
)
DQ
(t
n+1
)
0
1
0
1
1
---
Single Data Rate Read
Load New Address
X
Q1(t
n
)
0
1
0
1
0
---
Double Data Rate Read
Load New Address
X
X
Q1(t
n
)
Q2(t
n
)
0
1
0
0
1
---
Single Data Rate Write
Load New Address
Flush Write Buffer
X
D1(t
n
)
0
1
0
0
0
---
Double Data Rate Write
Load New Address
Flush Write Buffer
X
X
D1(t
n
)
D2(t
n
)
0
1
1
1
X
SDR Read
Single Data Rate Read Continue
Increment Address by One
Q1(t
n-1
)
Q2(t
n
)
0
1
1
1
X
DDR Read
Double Data Rate Read Continue
Increment Address by Two
Q1(t
n-1
)
Q2(t
n-1
)
Q3(t
n
)
Q4(t
n
)
0
1
1
1
X
SDR Write
Single Data Rate Write Continue
Increment Address by One
Flush Write Buffer
D1(t
n-1
)
D2(t
n
)
0
1
1
1
X
DDR Write
Double Data Rate Write Continue
Increment Address by Two
Flush Write Buffer
D1(t
n-1
)
D2(t
n-1
)
D3(t
n
)
D4(t
n
)
0
1
1
0
X
not Deselect
Deselect
X
Hi - Z
0
1
1
X
X
Deselect
Deselect (Continue)
Hi - Z
Hi - Z
State Diagram
Power Up
Deselect
SDR Read
SDR Write
DDR Read
DDR Write
Load New
Address
Increment
Address By One
Increment
Address By One
Increment
Address By Two
Increment
Address By Two
B1.B2
B1.B2
B1.B2
B1.B2
B1.B2
B2.B3
B1
B1
B2.B3
B2.B3
Flush WB
Flush WB
B1
B2.B3
B1
Flush WB
B1
B1.B2
B1.B2
B1.B2
B1
SONY
CXK77L18162GB
Preliminary
16Mb DDR1, rev 1.3
5 / 23
July 19, 2002
Continue Operations
These devices support Continue (Burst) operations via the synchronous B(1:3) control input signals. They have the ability
to burst transfer a maximum of four (4) distinct pieces of data per single external address input, regardless whether the data
transfers are SDR or DDR.
SDR Read and Write operations transfer one (1) piece of data. Consequently, one (1), two (2), or three (3) Continue opera-
tions may be initiated immediately after an SDR Read or Write operation to burst transfer two (2), three (3), or four (4) dis-
tinct pieces of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address
wraps back to the initial external (base) address.
DDR Read and Write operations transfer two (2) pieces of data. Consequently, one (1) Continue operation may be initiated
immediately after a DDR Read or Write operation to burst transfer four (4) distinct pieces of data per single external address
input. If a second (2nd) Continue operation is initiated, the internal address wraps back to the initial external (base) address.
The order (i.e. address sequence) in which multiple pieces of data are transferred during DDR and/or Continue operations is
determined by the state of LBO mode pin.
When LBO = 1, data transfers follow the Interleaved Burst address sequence depicted in the table below:
When LBO = 0, data transfers follow the Linear Burst address sequence depicted in the table below:.
Programmable Impedance Output Drivers
These devices have programmable impedance output drivers. The output impedance is controlled by an external resistor RQ
connected between the SRAM's ZQ pin and V
SS
, and is equal to one-fifth the value of this resistor, nominally. See the DC
Electrical Characteristics section for further information.
Output Driver Impedance Power-Up Requirements
Output driver impedance will reach the programmed value within 8192 cycles after power-up. Consequently, it is recom-
mended that Read operations not be initiated until after the initial 8192 cycles have elapsed.
Output Driver Impedance Updates
Data output impedance is updated during Write and Deselect operations when the output driver is disabled.
Clock pull-up output impedance is updated during Write and Deselect operations when the output driver is driving "low".
Clock pull-down output impedance is updated during Write and Deselect operations when the output driver is driving "high".
Interleaved Burst Address Sequence
Address Sequence
SA(1:0)
Sequence Key
1st (Base) Address
00
01
10
11
SA1, SA0
2nd Address
01
00
11
10
SA1, SA0
3rd Address
10
11
00
01
SA1, SA0
4th Address
11
10
01
00
SA1, SA0
Linear Burst Address Sequence
Address Sequence
SA(1:0)
Sequence Key
1st (Base) Address
00
01
10
11
SA1, SA0
2nd Address
01
10
11
00
(SA1 xor SA0), SA0
3rd Address
10
11
00
01
SA1, SA0
4th Address
11
00
01
10
(SA1 xor SA0), SA0
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