Description
The CXK77V3211Q is a 32K
32 high performance
synchronous SRAM with a 2-bit burst counter and
output register. All synchronous inputs pass through
register controlled by a positive-edge-triggered
single clock input (CLK). The synchronous inputs
include all addresses, all data inputs, chip enable
(CE), two additional chip enables for easy depth
expansion (CE2, CE2), burst control inputs (ADSC,
ADSP, ADV), four individual byte write enables
(BW1, BW2, BW3, BW4), one byte write enable
(BWE), and global write enable (SGW).
Asynchronous inputs include the output enable
(OE) and power down control (ZZ). Two mode
control pins (LBO, FT) define four different operation
modes: Linear/Interleaved burst sequence and
Flow-Thru/Pipelined operations.
WRITE cycles can be from one to four bytes wide
as controlled by BW1 through BW4 and BWE or
SGW. The output register is included on-chip and
controlled by clock, it can be activated by connecting
FT to high for high speed pipeline operation.
Burst operation can be initiated with either address
status processor (ADSP) or address status
controller (ADSC) input pins. Subsequent burst
addresses can be internally generated as controlled
by the burst advance pin (ADV). Burst order
sequence can be controlled by connecting LBO to
high for Interleaved burst order (i486/PentiumTM) or
by connecting LBO to low for Linear burst order.
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed
WRITE cycles. Individual byte enables allow
individual bytes to be written. WRITE pass through
makes written data immediately available at the
output register during READ cycle following a
WRITE as controlled by OE.
The CXK77V3211Q operates from a +3.3V power
supply and all inputs and outputs are LVTTL
compatible. The device is ideally suited for i486 and
PentiumTM
systems and those systems which
benefit from a very wide data bus.
i486/Pentium is a trademark of Intel Corp.
Structure
Silicon gate CMOS IC
Features
Fast address access times and High frequency
operation
5V tolerant inputs except I/O pins
A FT pin for pipelined or flow-thru architecture
A LBO mode pin as burst control pin
(i486/PentiumTM and Linear burst sequence)
Single +3.3V power supply
Common data inputs and data outputs
All inputs and outputs are LVTTL compatible
Four Individual BYTE WRITE enables, GLOBAL
WRITE and BYTE WRITE ENABLE
Three Chip Enables for simple depth expansion
One cycle output disable for both pipelined and
flow-thru operation
Internal input registers for address, data and
control signals
Self-timed WRITE cycle
Write pass through capability
High 30pF output drive capability at rated access
time
A ZZ pin for powerdown
100-lead QFP package for high density, high
speed operation
1
CXK77V3211Q
-12/14
E95721-PS
32768-word by 32-bit High Speed Synchronous Static RAM
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
100 pin QFP (Plastic)
Symbol
-12
-14
Access
12ns
14ns
Cycle
60MHz
50MHz
Access
7ns
8ns
Cycle
75MHz
66MHz
Flow-through
Pipeline
+10%
5%
For the availability of this product, please contact the sales office.
4
CXK77V3211Q
Pin Description
Symbol
I/O
Description
A0 to A14
BW1, BW2,
BW3, BW4
CLK
CE
CE2
CE2
OE
ADV
ADSP
ADSC
NC
DQ1 to DQ32
BWE
SGW
FT
LBO
ZZ
V
DD
V
SS
V
DD
q
V
SS
q
I
I
I
I
I
I
I
I
I
I
--
I/O
I
I
I
I
I
Supply
Supply
Supply
Supply
Synchronous Address Inputs: These inputs are registered and must meet the
setup and hold times around the rising edge of CLK.
Synchronous Individual Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold times around the
rising edge of CLK. A BYTE WRITE enable is LOW for a WRITE cycle and HIGH
for a READ cycle. BW1 controls DQ1 to DQ8. BW2 controls DQ9 to DQ16. BW3
controls DQ17 to DQ24. BW4 controls DQ25 to DQ32. Data I/O are tristated if
any of these four inputs are LOW.
Clock: This signal latches the address, data, chip enable, byte write enables and
burst control inputs on its rising edge. All synchronous inputs must meet setup
and hold times around the clock's rising edge.
Synchronous Chip Enable: This active LOW input is used to enable the device
and conditions internal use of ADSP. This input is sampled only when a new
external address is loaded.
Synchronous Chip Enable: This active LOW input is used to enable the device.
This input is sampled only when a new external address is loaded. This input can
be used for memory depth expansion.
Synchronous Chip Enable: This active HIGH input is used to enable the device.
This input is sampled only when a new external address is loaded. This input can
be used for memory depth expansion.
Output Enable: This active LOW asynchronous input enables the data I/O output
drivers.
Synchronous Address Advance: This active LOW input is used to advance the
internal burst counter, controlling burst access after the external address is
loaded. A HIGH on this pin effectively causes wait status to be generated (no
address advance). This pin must be HIGH at the rising edge of the first clock after
an ADSP cycle is initiated if a WRITE cycle is desired (to ensure use of correct
address).
Synchronous Address Status Processor: This active LOW input interrupts any
ongoing burst, causing a new external address to be latched. A READ is
performed using the new address, independent of the byte write enables and
ADSC but dependent upon CE2 and CE2. ADSP is ignored if CE is HIGH. Power
down state is entered if CE2 is LOW or CE2 is HIGH.
Synchronous Address Status Controller: This active LOW input interrupts any
ongoing burst and causes a new external address to be latched. A READ or
WRITE is performed using the new address if all chip enables are active. Power-
down state is entered if one or more chip enables are inactive.
No Connect: These signals are not internally connected.
SRAM Data I/O: Byte 1 is DQ1 to DQ8; Byte 2 is DQ9 to DQ16; Byte 3 is DQ17 to
DQ24; Byte 4 is DQ25 to DQ32. Input data must meet setup and hold times
around the rising edge of CLK.
Byte Write Enable: This active low input enables individual byte to write.
Global Write: This active low input enables to write all bytes.
Flow Through: This active low input selects flow through output.
Linear Burst: This active high input selects interleaved burst sequence.
ZZ: This active high input enables the device in powerdown mode.
Power Supply: +3.3V
Ground: GND
Isolated Output Buffer Supply: +3.3V
Isolated Output Buffer Ground: GND
+10%
5%
+10%
5%
5
CXK77V3211Q
Interleaved Burst Sequence Table
First access, latch external address
Second access (first burst address)
Third access (second burst address)
Fourth access (third burst address)
A14 to A2
A14 to A2
latched A14 to A2
latched A14 to A2
latched A14 to A2
A1
A1
latched A1
latched A1
latched A1
A0
A0
latched A0
latched A0
latched A0
Operation
X...X00
X...X01
X...X10
X...X11
First address
X...X01
X...X00
X...X11
X...X10
Second address
X...X10
X...X11
X...X00
X...X01
Third address
X...X11
X...X10
X...X01
X...X00
Fourth address
Address used
Interleaved Burst Address Table
X...X00
X...X01
X...X10
X...X11
First address
Initial WRITE cycle, all bytes
Address = A (n 1),
data = D (n 1)
Initial WRITE cycle, all bytes
Address = A (n 1),
data = D (n 1)
Initial WRITE cycle, all bytes
Address = A (n 1),
data = D (n 1)
Initial WRITE cycle, one byte
Address = A (n 1),
data = D (n 1)
All L
All L
All L
One L
Initial READ cycle
Register A (n), Q = D (n 1)
No new cycle
Q = D (n 1)
No new cycle
Q = HIGH-Z
No new cycle
Q = D (n 1) for one byte
L
H
H
H
H
H
H
H
L
L
H
L
Read D (n)
No carryover from
previous cycle
No carryover from
previous cycle
No carryover from
previous cycle
Operation
BWs
Operation
CE
BWs
OE
Operation
Previous cycle
Present cycle
Next cycle
X...X01
X...X10
X...X11
X...X00
Second address
X...X10
X...X11
X...X00
X...X01
Third address
X...X11
X...X00
X...X01
X...X10
Fourth address
Linear Burst Address Table
Pass-Through Truth Table
Note) Previous cycle may be either BURST or NONBURST cycle.
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