CMOS-CCD 1H/2H Delay Line for PAL
Description
The CXL1506M/N is a CMOS-CCD delay line
developed for video signal processing. Usage in
conjunction with an external low pass filter provides
1H and 2H delay signals simultaneously (For PAL
signals).
Features
Single power supply (5V)
Low power consumption
Built-in peripheral circuits
Built-in tripling PLL circuit
For PAL signals
1 input and 2 outputs
(Outputs for both 1H and 2H delays)
Absolute Maximum Ratings (Ta = 25C)
Supply voltage
V
DD
6
V
Operating temperature
Topr
10 to +60
C
Storage temperature
Tstg
55 to +150
C
Allowable power dissipation
P
D
CXL1506M 400 mW
CXL1506N 300 mW
Recommended Operating Voltage (Ta = 25C)
V
DD
5 0.25
V
Recommended Clock Conditions (Ta = 25C)
Input clock amplitude
V
CLK
0.2 to 1.0Vp-p (0.4Vp-p Typ.)
Input clock frequency
f
CLK
4.433619
MHz
Input clock waveform
sine wave
Input Signal Amplitude
V
SIG
575 (Max.) mVp-p (at internal clamp condition)
1
E89X22C78-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXL1506M/N
CXL1506M
16 pin SOP (Plastic)
CXL1506N
20 pin SSOP (Plastic)
Blook Diagram
CXL1506M
CXL1506N
Autobias circuit
Driver
Bias
circuit
PLL
Timing
CCD (1698bits)
Clamp circuit
Output circuit
S/H 1bit
14
12
13
10
11
2
5
6
7
1
V
SS
V
DD
VCO
IN
PC
OUT
V
SS
IN
VG1
VG2
OUT1
(1H)
V
SS
OUT2
(2H)
8
CLK
V
SS
(VCO OUT)
15
16
AB
V
DD
V
SS
Output circuit
S/H 1bit
9
4
847bits
1698bits
3
Autobias circuit
Driver
Bias
circuit
PLL
Timing
CCD (1698bits)
Clamp circuit
Output circuit
S/H 1bit
14
12
13
10
11
2
5
6
7
1
V
SS
NC
V
DD
VCO
IN
PC
OUT
V
SS
IN
VG1
VG2
OUT1
(1H)
V
SS
OUT2
(2H)
8
CLK
V
SS
(VCO OUT)
NC
15
16
17
18
19
20
AB
V
DD
NC
NC
V
SS
Output circuit
S/H 1bit
9
4
847bits
1698bits
3
For the availability of this product, please contact the sales office.
2
CXL1506M/N
Pin Description (CXL1506M)
Pin No.
Symbol
I/O
Description
Impedance [
]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IN
VG1
VG2
OUT1
V
SS
OUT2
V
SS
(VCO OUT)
V
SS
V
DD
CLK
V
SS
PC OUT
VCO IN
V
DD
AB
V
SS
I
O
I
O
--
O
(O)
--
--
I
--
O
I
--
O
--
Signal input
(Non-inverted signal)
Gate bias 1 DC output
Gate bias 2 DC input
1H signal output
(Inverted signal)
GND
2H signal output
(Inverted signal)
GND or VCO output (3fsc)
GND
Power supply (5V)
Clock input (fsc)
GND
Phase comparator output
VCO input
Power supply (5V)
Autobias DC output
GND
> 10k
(at no clamp)
40 to 500
40 to 500
> 10k
600 to 200k
Note) Description of VG2
Control of input signal clamp condition
0V ... Sync tip clamp condition
5V ... Center bias condition
The input signal is biased to approx. 2.1V by means of the IC internal resistance (approx. 10k
).
In this mode the input signal is limited to the APL 50% and the maximum input signal amplitude is
at 200mVp-p.
(Note)
3
CXL1506M/N
Pin Description (CXL1506N)
Pin No.
Symbol
I/O
Description
Impedance [
]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NC
IN
VG1
VG2
OUT1
V
SS
OUT2
NC
V
SS
(VCO OUT)
V
SS
V
DD
CLK
NC
V
SS
PC OUT
VCO IN
V
DD
AB
NC
V
SS
--
I
O
I
O
--
O
--
(O)
--
--
I
--
--
O
I
--
O
--
--
--
Signal input
(Non-inverted signal)
Gate bias 1 DC output
Gate bias 2 DC input
1H signal output
(Inverted signal)
GND
2H signal output
(Inverted signal)
--
GND or VCO output (3fsc)
GND
Power supply (5V)
Clock input (fsc)
--
GND
Phase comparator output
VCO input
Power supply (5V)
Autobias DC output
--
GND
> 10k
(at no clamp)
40 to 500
40 to 500
> 10k
600 to 200k
Note) Description of VG2
Control of input signal clamp condition
0V ... Sync tip clamp condition
5V ... Center bias condition
The input signal is biased to approx. 2.1V by means of the IC internal resistance (approx. 10k
).
In this mode the input signal is limited to the APL 50% and the maximum input signal amplitude is
at 200mVp-p.
(Note)
4
CXL1506M/N
Electrical Characteristics
(Ta = 25C, V
DD
= 5V, f
CLK
= 4.433619MHz, V
CLK
= 400mVp-p sine wave)
See Electrical Characteristics Test Circuit.
Item
Symbol
Test conditions
(Note 1)
SW conditions
Min.
Typ.
Max.
Unit
Note
1
2 3 4
2
3
4
5
5
6
7
mA
dB
dB
%
degree
dB
mVp-p
37
2
2
0.7
0.8
7
7
7
7
--
--
350
350
27
0
0
1.7
1.8
5
5
5
5
56
56
--
--
17
2
2
2.7
2.8
--
--
--
--
52
52
--
--
a
b
b
b
b
c
c
c
c
d
d
a
a
a
a
b
a
b
a
b
a
b
a
b
a
b
b
b
b
a
a
b
b
b
b
b
b
b
b
a
a
a
b
c
b
c
d
d
d
d
e
e
e
e
--
200kHz
500mVp-p sine wave
200kHz
4.434MHz
150mVp-p sine wave
5 staircase wave
5 staircase wave
No signal input
No signal input
I
DD
GL1
GL2
fR1
fR2
DG1
DG2
DP1
DP2
SN1
SN2
CP1
CP2
Supply current
Low frequency
gain
Frequency
response
Differential gain
Differential phase
S/N ratio
S/H pulse coupling
5
CXL1506M/N
1
3
.
3
M
1
3
.
3
M
0
3
.
3
V
S
S
A
B
V
D
D
V
C
O
I
N
P
C
O
U
T
V
D
D
C
L
K
1
0
0
0
P
1
2
0
3
.
3
8
2
k
1
C
L
K
f
S
C
(
4
.
4
3
3
6
1
9
M
H
z
)
,
4
0
0
m
V
p
-
p
s
i
n
e
w
a
v
e
I
N
V
G
1
V
G
2
O
U
T
1
V
S
S
V
s
s
(
V
C
O
O
U
T
)
V
S
S
a
b
1
M
1
2
0
0
k
H
z
5
0
0
m
V
p
-
p
s
i
n
e
w
a
v
e
2
0
0
k
H
z
1
5
0
m
V
p
-
p
s
i
n
e
w
a
v
e
4
.
4
3
4
M
H
z
1
5
0
m
V
p
-
p
s
i
n
e
w
a
v
e
5
-
s
t
a
i
r
c
a
s
e
w
a
v
e
a
b
d
a
S
W
4
2
3
4
5
6
7
1
b
c
d
N
o
t
e
1
)
N
o
t
e
2
)
L
P
F
B
P
F
N
o
t
e
1
)
L
P
F
f
r
e
q
u
e
n
c
y
r
e
s
p
o
n
s
e
0
3
5
0
6
M
f
-
F
r
e
q
u
e
n
c
y
[
H
z
]
[
d
B
]
N
o
t
e
2
)
B
P
F
f
r
e
q
u
e
n
c
y
r
e
s
p
o
n
s
e
0
3
5
0
6
M
f
-
F
r
e
q
u
e
n
c
y
[
H
z
]
[
d
B
]
2
0
0
8
9
1
1
1
3
1
4
S
W
1
S
W
3
1
5
1
6
O
U
T
2
V
S
S
1
0
1
2
A
0
.
1
1
0
0
0
P
1
0
0
0
P
a
b
c
5
V
1
0
0
0
P
S
W
2
0
e
0
.
1
S
p
e
c
t
r
u
m
a
n
a
l
y
z
e
r
V
e
c
t
o
r
s
c
o
p
e
N
o
i
s
e
m
e
t
e
r
O
s
c
i
l
l
o
s
c
o
p
e
Electrical Characteristics
Test Circuit
(CXL1506M)
When using CXL1506N, change the connection terminal only.
(See the block diagram and pin configuration. For NC pins, ground them.)
6
CXL1506M/N
2) This is the IC supply current value during clock and signal input.
3) GL is the output gain of pin OUT when a 500mVp-p, 200kHz sine wave is fed to pin IN.
GL = 20 log [dB]
4) Indicates the dissipation at 4.434MHz in relation to 200kHz. From the output voltage at pin OUT when a
150mVp-p, 200kHz sine wave is fed to pin IN, and from the output voltage at pin OUT when a 150mVp-p,
4.434MHz sine wave is fed to same, calculation is made according to the following formula.
fR = 20 log [dB]
5) The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the following figure
is fed, are tested with a vector scope:
pin OUT output voltage [mVp-p]
500 [mVp-p]
pin OUT output voltage (4.434MHz) [mVp-p]
pin OUT output voltage (200kHz) [mVp-p]
1H 64s
150mV
275mV
500mV
150mV
Notes)
1) By switching SW2, input condition turns out as follows.
SW2 condition
Input condition
a
b
Center bias condition (approx. 2.1V)
Approx. 2.1V bias is applied internally to the input signal
Sync tip and clamp conditions
7
CXL1506M/N
GL
20
6) The noise level of the output signal at no-input signal is tested with a video noise meter in the Sub Carrier
Trap mode at BPF 100kHz to 5MHz. (Vn [Vrms])
The signal component is determined either by testing the output voltage (the same testing system as for
noise level) at the input of 350mVp-p, 200kHz, or by utilizing values from GL to calculate according to the
following formula. (Vs [Vp-p])
(Example of Vs calculation)
Vs = 0.35
10
(Example of SN ratio calculation)
SN = 20 log [dB]
7) The internal clock component to the output signal during no-signal input and the leakage of that high
harmonic component are tested.
Clock
Vn (noise component) [Vrms]
Vs (signal component) [Vp-p]
Test value [mVp-p]
400mVp-p
(typ.)
fsc (4.433619MHz) sine wave
8
CXL1506M/N
Application Circuit
(CXL1506M)
3
.
3
1
0
0
0
P
1
2
0
3
.
3
8
2
k
1
C
L
K
f
S
C
(
4
.
4
3
3
6
1
9
M
H
z
)
,
4
0
0
m
V
p
-
p
s
i
n
e
w
a
v
e
1
M
2
3
4
5
6
7
1
8
9
1
1
1
3
1
4
1
0
0
1
5
1
6
1
2
0
.
1
1
0
0
0
P
1
0
0
0
P
5
V
1
0
0
0
P
0
.
1
4
7
0
3
3
0
k
5
6
0
k
1
k
6
2
P
L
P
F
2
.
2
k
2
.
2
k
2
.
2
k
5
V
T
r
a
n
s
i
s
t
o
r
u
s
e
d
P
N
P
:
2
S
A
1
1
7
5
T
r
a
n
s
i
s
t
o
r
u
s
e
d
N
P
N
:
2
S
C
4
0
3
1
H
O
u
t
p
u
t
(
N
o
n
-
i
n
v
e
r
t
e
d
s
i
g
n
a
l
)
0
.
1
1
0
0
4
7
0
3
3
0
k
5
6
0
k
1
k
6
2
P
L
P
F
2
.
2
k
2
.
2
k
2
.
2
k
5
V
T
r
a
n
s
i
s
t
o
r
u
s
e
d
P
N
P
:
2
S
A
1
1
7
5
T
r
a
n
s
i
s
t
o
r
u
s
e
d
N
P
N
:
2
S
C
4
0
3
2
H
O
u
t
p
u
t
0
.
1
V
1
(
I
n
v
e
r
t
e
d
s
i
g
n
a
l
)
(
N
o
n
-
i
n
v
e
r
t
e
d
s
i
g
n
a
l
)
S
i
g
n
a
l
i
n
p
u
t
(
N
o
n
-
i
n
v
e
r
t
e
d
s
i
g
n
a
l
)
(
I
n
v
e
r
t
e
d
s
i
g
n
a
l
)
D
e
l
a
y
t
i
m
e
2
3
0
n
s
C
X
L
1
5
0
6
M
1
0
1
W
h
e
n
u
s
i
n
g
C
X
L
1
5
0
6
N
,
c
h
a
n
g
e
t
h
e
c
o
n
n
e
c
t
i
o
n
t
e
r
m
i
n
a
l
o
n
l
y
.
(
S
e
e
t
h
e
b
l
o
c
k
d
i
a
g
r
a
m
a
n
d
p
i
n
c
o
n
f
i
g
u
r
a
t
i
o
n
.
F
o
r
N
C
p
i
n
s
,
g
r
o
u
n
d
t
h
e
m
.
)
2
S
C
4
0
3
3
f
s
c
O
U
T
1
.
8
k
1
.
8
k
5
V
7
N
o
t
e
)
W
h
e
n
V
C
O
O
U
T
i
s
r
e
q
u
i
r
e
d
,
u
s
e
t
h
e
c
i
r
c
u
i
t
b
e
l
o
w
.
D
e
l
a
y
t
i
m
e
2
1
0
n
s
N
o
t
e
)
W
h
e
n
u
s
i
n
g
P
i
n
7
(
V
C
O
O
U
T
)
,
u
s
e
t
h
e
c
i
r
c
u
i
t
a
s
s
h
o
w
n
b
e
l
o
w
.
W
h
e
n
n
o
t
u
s
i
n
g
i
t
,
G
N
D
.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility fo
r
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same
.
9
CXL1506M/N
Example of Representative Characteristics
Low frequency gain (1H) vs. Ambient temperature
20
0
20
40
60
80
2
1
0
1
2
Ambient temperature [C]
L
o
w
f
r
e
q
u
e
n
c
y
g
a
i
n
1
H
[
d
B
]
Supply current vs. Ambient temperature
20
0
20
40
60
80
15
35
25
Ambient temperature [C]
S
u
p
p
l
y
c
u
r
r
e
n
t
[
m
A
]
Low frequency gain (2H) vs. Ambient temperature
20
0
20
40
60
80
0
1
2
Ambient temperature [C]
L
o
w
f
r
e
q
u
e
n
c
y
g
a
i
n
2
H
[
d
B
]
Differential gain (1H) vs. Ambient temperature
20
0
20
40
60
80
2
4
6
8
10
0
Ambient temperature [C]
D
i
f
f
e
r
e
n
t
i
a
l
g
a
i
n
1
H
[
%
]
2
1
Frequency response (1H) vs. Ambient temperature
2
1
0
3
Ambient temperature [C]
F
r
e
q
u
e
n
c
y
r
e
s
p
o
n
s
e
1
H
[
d
B
]
20
0
20
40
60
80
Frequency response (2H) vs. Ambient temperature
2
1
0
3
Ambient temperature [C]
F
r
e
q
u
e
n
c
y
r
e
s
p
o
n
s
e
2
H
[
d
B
]
20
0
20
40
60
80
10
CXL1506M/N
Supply current vs. Supply voltage
4.75
5
5.25
15
35
25
Supply voltage [V]
S
u
p
p
l
y
c
u
r
r
e
n
t
[
m
A
]
Low frequency gain (1H) vs. Supply voltage
0
1
2
Supply voltage [V]
L
o
w
f
r
e
q
u
e
n
c
y
g
a
i
n
1
H
[
d
B
]
Differential gain (2H) vs. Ambient temperature
20
0
20
40
60
80
2
4
6
8
10
0
Ambient temperature [C]
D
i
f
f
e
r
e
n
t
i
a
l
g
a
i
n
2
H
[
%
]
2
1
Frequency response (2H) vs. Supply voltage
2
1
0
3
Supply voltage [V]
F
r
e
q
u
e
n
c
y
r
e
s
p
o
n
s
e
2
H
[
d
B
]
Frequency response (1H) vs. Supply voltage
2
1
0
3
Supply voltage [V]
F
r
e
q
u
e
n
c
y
r
e
s
p
o
n
s
e
1
H
[
d
B
]
Low frequency gain (2H) vs. Supply voltage
0
1
2
Supply voltage [V]
L
o
w
f
r
e
q
u
e
n
c
y
g
a
i
n
2
H
[
d
B
]
2
1
4.75
5
5.25
4.75
5
5.25
4.75
5
5.25
4.75
5
5.25
11
CXL1506M/N
Differential gain (1H) vs. Supply voltage
4.75
5
5.25
2
4
6
8
10
0
Supply voltage [V]
D
i
f
f
e
r
e
n
t
i
a
l
g
a
i
n
1
H
[
%
]
Differential gain (2H) vs. Supply voltage
2
4
6
8
10
0
Supply voltage [V]
D
i
f
f
e
r
e
n
t
i
a
l
g
a
i
n
2
H
[
%
]
4.75
5
5.25
Frequency response (1H)
10K
100K
1M
6
4
2
0
2
Frequency [Hz]
G
a
i
n
[
d
B
]
10M
Frequency response (2H)
10K
100K
1M
6
4
2
0
2
Frequency [Hz]
G
a
i
n
[
d
B
]
10M
Note) 1H and 2H shown in brackets indicate 1H and 2H outputs.
12
CXL1506M/N
Package Outline
Unit: mm
CXL1506M
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
SONY CODE
EIAJ CODE
JEDEC CODE
SOP-16P-L01
SOP016-P-0300
COPPER ALLOY
SOLDER PLATING
EPOXY RESIN
16PIN SOP (PLASTIC)
9.9 0.1
+ 0.4
16
9
1
8
1.27
0.45 0.1
5
.
3
0
.
1
+
0
.
3
7
.
9
0
.
4
6
.
9
1.85 0.15
+ 0.4
0
.
5
0
.
2
0.2 0.05
+ 0.1
0.1 0.05
+ 0.2
0.2g
0.15
M
0.24
20PIN SSOP (PLASTIC)
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER / PALLADIUM
42/COPPER ALLOY
0.1g
SSOP-20P-L01
SSOP020-P-0044
0.1 0.1
0
.
5
0
.
2
0 to 10
DETAIL A
PLATING
6.5 0.1
4
.
4
0
.
1
0.22 0.05
+ 0.1
0.65
20
11
10
1
A
0.1
+ 0.05
1.25 0.1
+ 0.2
0.15 0.02
6
.
4
0
.
2
NOTE: Dimension "
" does not include mold protrusion.
0.13 M
CXL1506N
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