CMOS-CCD 1H Delay Line for NTSC
Description
The CXL5504M/P are CMOS-CCD delay line ICs
that provide 1H delay time for NTSC signals including
the external low-pass filter.
Features
Single power supply (5V)
Low power consumption 90mW (Typ.)
Built-in peripheral circuits
Clamp level of I/O signal can be selected
Functions
905-bit CCD register
Clock driver
Autobias circuit
Input clamp circuit
Sample and hold circuit
Structure
CMOS-CCD
Absolute Maximum Ratings (Ta = 25C)
Supply voltage
V
DD
6
V
Operating temperature Topr
10 to +60
C
Storage temperature
Tstg
55 to +150
C
Allowable power dissipation
P
D
CXL5504M
350
mW
CXL5504P
480
mW
Recommended Operating Condition (Ta = 25C)
Supply voltage
V
DD
5 5%
V
Recommended Clock Conditions (Ta = 25C)
Input clock amplitude
V
CLK
0.4 to 1.0
Vp-p
(0.5Vp-p typ.)
Clock frequency
f
CLK
14.318182
MHz
Input clock waveform
Sine wave
Input Signal Amplitude
V
SIG
500mVp-p (Typ.), 572mVp-p (Max.)
(at internal clamp condition)
1
E89931C79-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXL5504M/P
CXL5504M
8 pin SOP (Plastic)
CXL5504P
8 pin DIP (Plastic)
Blook Diagram and Pin Configration (Top View)
Output circuit
(S/H 1bit)
CLK
1
2
3
4
5
7
8
Autobias circuit
Timing circuit
Bias circuit
CCD
(905bit)
Clock driver
Bias circuit (A)
Bias circuit (B)
I/O control
Clamp circuit
6
I/O1
V
DD
AB
V
SS
OUT
I/O2
IN
For the availability of this product, please contact the sales office.
2
CXL5504M/P
Description of Function
In the CXL5504M/P, the condition of I/O control pins (Pins 2 and 6) control the input signal clamp condition and
the mode of the output signal with relation to its input signal.
There are 2 modes for the I/O signal.
(1) PN mode
(Low level clamp/reverse phase output mode)
(2) NP mode
(High level clamp/positive phase output mode)
I/O Control Pin
(1) I/O1 (Pin 6)
Control of the I/O signal condition
DC open .....
Input signal is low level clamped and the output signal is inverted in relation to the input
signal. As the pin is biased to 2.5V by means of the resistance inside the IC, a decoupling
capacitor of around 1000pF is necessary.
GND ............. Input signal is high level clamped and the output signal turns into an inverted signal.
(2) I/O2 (Pin 2)
Control of the input signal clamp condition
0V ................. Internal clamp condition
5V ................. Non internal clamp condition
Center biased to approx. 2.1V by means of the IC internal resistance (several 10k
).
Usage in this mode is limited to APL 50% signals and in this mode, the maximum input
signal amplitude is 200mVp-p.
Clamp
level
Input waveform
Output waveform
Clamp
level
Pin Description
Pin No.
Symbol
I/O
Description
Impedance
1
2
3
4
5
6
7
8
IN
I/O2
OUT
V
SS
CLK
I/O1
V
DD
AB
I
I
O
--
I
I
--
O
Signal input
I/O control 2
Signal output
GND
Clock input
I/O control 1
Power supply (5V)
Autobias DC output
> 10k
at no clamp
40 to 500
> 100k
600 to 200k
3
CXL5504M/P
--
--
2.1
--
--
VINPN + 0.5
VINNP
--
b
a
b
a
b
a
b
a
b
a
b
a
b
a
b
a
b
a
b
a
b
a
b
a
b
a
b
a
10
2
2
0
0
--
52
18
0
1
5
5
--
56
28
2
0
7
7
350
--
mA
dB
dB
%
degree
mVp-p
dB
2
3
4
5
5
6
7
Unit
Note
Max.
Min.
Typ.
Bias condition
Vbias1 (V)
(Note 1)
Electrical Characteristics
(Ta = 25C, V
DD
= 5V, f
CLK
= 14.318182MHz, V
CLK
= 500mVp-p, Sine wave)
See "Electrical Characteristics Test Circuit"
Notes
(1) VINPN and VINNP are defined as follows.
VINPN and VINNP are the input signal clamp levels of PN and NP modes clamping the video signal sync
tip level.
Testing of VINPN and VINNP is executed with a voltmeter under the following SW conditions.
Item
Symbol
Test condition
SW condition
1 2 3 4 5 6 7
--
a
b
c
d
d
--
e
c
a
a
a
b
a
b
c
a
b
b
b
a
b
b
a
b
a
a
b
a
a
b
a
--
b
b
c
c
a
d
--
200kHz,
500mVp-p,
sine wave
200kHz
3.57MHz,
150mVp-p,
sine wave
5-staircase wave
(See Note 5)
5-staircase wave
(See Note 5)
No signal input
50% white
video signal
(See Note 7)
IDDPN
IDDNP
GLPN
GLNP
fPN
fNP
DGPN
DGNP
DPPN
DPNP
CPPN
CPNP
SNPN
SNNP
Supply
current
Low
frequency
gain
Frequency
response
Differential
gain
Differential
phase
S/H pulse
coupling
S/N ratio
1
Input
(IN)
VINPN
CXL5504
VINNP
SW condition
Item
VINPN
VINNP
Test
point
V1
1
--
--
2
c
c
3
b
b
4
b
a
5
b
a
6
a
a
7
--
--
4
CXL5504M/P
(2) This is the IC supply current value during clock and signal input.
(3) GLPN, GLNP are output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin.
(Example of calculation)
GLPN = 20 log [dB]
(4) Indicates the dissipation at 3.57MHz in relation to 200kHz.
From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the
output voltage at OUT pin when a 150mVp-p, 3.57MHz sine wave is fed to same, calculation is made
according to the following formula. The input part bias is tested at 2.1V.
(Example of calculation)
fPN = 20 log [dB]
(5) The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the figure below is
input are tested at the vector scope.
Input waveform (Input waveform of NP mode is the inverted waveform in the figure above)
(6) The internal clock component to the output signal during no-signal input and the leakage of that high
harmonic component are tested. The input part bias is tested at VINPN + 0.5V and VINNP for PN and NP
modes respectively.
OUT pin output voltage (PN mode) [mVp-p]
500 [mVp-p]
OUT pin otuput voltage (PN mode, 3.57MHz) [mVp-p]
OUT pin output voltage (PN mode, 200kHz) [mVp-p]
1H 63.56s
143mV
357mV
500mV
143mV
Test value
(mVp-p)
5
CXL5504M/P
(7) S/N ratio during a 50% white video signal input shown in figure below is tested at a video noise meter, in
BPF 100kHz to 4MHz, Sub Carrier Trap mode.
Input waveform (Input waveform of NP mode is the inverted waveform in the figure above)
Clock
1H 63.56s
143mV
178mV
321mV
0.4 to 1.0Vp-p
(0.5Vp-p typ.)
fsc (14.318182MHz) sine wave
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