CMOS-CCD 1H Delay Line for PAL
Description
The CXL5506M/P are CMOS-CCD delay line ICs
that provide 1H delay time for PAL signals including
the external low-pass filter.
Features
Single 5V power supply
Low power consumption 95mW (Typ.)
Built-in peripheral circuits
Functions
1130-bit CCD register
Clock driver
Auto-bias circuit
Input clamp circuit
Sample-and-hold circuit
Structure
CMOS-CCD
Absolute Maximum Ratings (Ta = 25C)
Supply voltage
V
DD
6
V
Operating temperature Topr
10 to +60
C
Storage temperature
Tstg
55 to +150
C
Allowable power dissipation
P
D
CXL5506M
350
mW
CXL5506P
480
mW
Recommended Operating Condition (Ta = 25C)
Supply voltage
V
DD
5 5%
V
Recommended Clock Conditions (Ta = 25C)
Input clock amplitude
V
CLK
0.3 to 1.0
Vp-p
(0.5Vp-p typ.)
Clock frequency
f
CLK
17.734475
MHz
Input clock waveform
Sine wave
Input Signal Amplitude
V
SIG
575mVp-p (Max.) (at internal clamp condition)
1
E90632B7X-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXL5506M/P
Blook Diagram and Pin Configuration (Top View)
Output circuit
(S/H 1bit)
CLK
1
2
3
4
5
7
8
Auto-bias circuit
Timing circuit
Bias circuit
CCD
(1130bit)
Clock driver
Bias circuit (A)
Bias circuit (B)
Clamp circuit
6
VG1
V
DD
AB
V
SS
OUT
VG2
IN
CXL5506M
8 pin SOP (Plastic)
CXL5506P
8 pin DIP (Plastic)
2
CXL5506M/P
Description of Pin 2 (VG2)
Control of input signal clamp condition
0V ........ Sync tip clamp condition
5V ........ Center bias condition
Center biased to approx. 2.1V by means of the IC internal resistance (approx. 10k
).
In this mode, the input signal is limited to APL 50% and the maximum input signal amplitude is
200mVp-p.
Clamp
level
Input waveform
Output waveform
Pin Description
Pin No.
Symbol
Description
Impedance
1
2
3
4
5
6
7
8
IN
VG2
OUT
V
SS
CLK
VG1
V
DD
AB
Signal input
Gate bias 2 DC input
Signal output
GND
Clock input
Gate bias 1 DC output
Power supply (5V)
Auto-bias DC output
> 10k
at no clamp
40 to 500
> 10k
600 to 200k
I
I
O
--
I
O
--
O
I/O
3
CXL5506M/P
Electrical Characteristics
(Ta = 25C, V
DD
= 5V, f
CLK
= 17.734475MHz, V
CLK
= 500mVp-p, sine wave)
See "Electrical Characteristics Test Circuit"
Notes
(1) This is the IC supply current value during clock and signal input.
(2) GL is the output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin.
GL = 20 log [dB]
(3) Indicates the dissipation at 4.43MHz in relation to 200kHz.
From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the
output voltage at OUT pin when a 150mVp-p, 4.43MHz sine wave is fed to same, calculation is made
according to the following formula.
fR = 20 log [dB]
a
a
b
c
d
d
f
e
10
2
2
0
0
--
52
19
0
1
3
3
--
56
28
2
0
5
5
350
--
mA
dB
dB
%
degree
mVp-p
dB
1
2
3
4
4
5
6
Unit
Note
Max.
Min.
Typ.
Item
Symbol
Test condition
SW condition
1
a
a
b
a
a
b
a
2
--
b
b
c
c
a
d
3
--
200kHz,
500mVp-p,
sine wave
200kHz
4.43MHz,
150mVp-p,
sine wave
5-staircase wave
(See Note 4)
5-staircase wave
(See Note 4)
No signal input
50% white
video signal
(See Note 6)
I
DD
GL
fR
DG
DP
CP
SN
Supply current
Low frequency gain
Frequency response
Differential gain
Differential phase
S/H pulse coupling
S/N ratio
OUT pin output voltage [mVp-p]
500 [mVp-p]
OUT pin otuput voltage (4.43MHz) [mVp-p]
OUT pin output voltage (200kHz) [mVp-p]
4
CXL5506M/P
4fsc (17.734475MHz) sine wave
0.3 to 1.0Vp-p
(0.5Vp-p typ.)
(4) In figure below, differential gain (DG) and differential phase (DP) are tested with a vector scope when
the 5-staircase wave is fed.
Input waveform
(5) The internal clock component to the output signal during no-signal input and the leakage of that high
harmonic component are tested.
(6) S/N ratio during a 50% white video signal input shown in figure below is tested at a video noise meter, in
BPF 100kHz to 5MHz, Sub Carrier Trap mode.
Input waveform
Clock
1H 64s
150mV
350mV
500mV
150mV
1H 64s
150mV
175mV
325mV
Test value
(mVp-p)
5
CXL5506M/P
Electrical Characteristics Test Circuit
1
A
B
V
D
D
V
G
1
C
L
K
1
0
0
0
p
1
0
0
0
p
3
.
3
0
.
1
C
L
K
4
f
S
C
(
1
7
.
7
3
4
4
7
5
M
H
z
)
0
.
5
V
p
-
p
s
i
n
e
w
a
v
e
I
N
V
G
2
O
U
T
V
S
S
a
b
S
W
2
1
M
5
V
1
S
W
1
c
a
b
d
e
a
S
W
3
2
.
1
k
9
V
2
3
4
5
6
7
1
b
c
d
3
3
L
P
F
B
P
F
0
3
5
0
7
M
1
7
.
7
M
F
r
e
q
u
e
n
c
y
[
H
z
]
[
d
B
]
7
M
1
7
.
7
M
F
r
e
q
u
e
n
c
y
[
H
z
]
2
0
0
8
1
0
0
0
p
0
3
5
0
[
d
B
]
f
O
s
c
i
l
l
o
s
c
o
p
e
S
p
e
c
t
r
u
m
a
n
a
l
y
z
e
r
V
e
c
t
o
r
s
c
o
p
e
N
o
i
s
e
m
e
t
e
r
N
o
t
e
1
)
N
o
t
e
2
)
2
0
0
k
H
z
5
0
0
m
V
p
-
p
s
i
n
e
w
a
v
e
2
0
0
k
H
z
1
5
0
m
V
p
-
p
s
i
n
e
w
a
v
e
4
.
4
3
M
H
z
1
5
0
m
V
p
-
p
s
i
n
e
w
a
v
e
5
-
s
t
a
i
r
c
a
s
e
w
a
v
e
5
0
%
w
h
i
t
e
v
i
d
e
o
s
i
g
n
a
l
N
o
t
e
1
)
L
P
F
f
r
e
q
u
e
n
c
y
r
e
s
p
o
n
s
e
N
o
t
e
2
)
B
P
F
f
r
e
q
u
e
n
c
y
r
e
s
p
o
n
s
e
6
CXL5506M/P
Application Circuit
1
0
0
0
p
3
.
3
0
.
1
1
4
f
S
C
(
1
7
.
7
3
4
4
7
5
M
H
z
)
0
.
5
V
p
-
p
s
i
n
e
w
a
v
e
1
M
1
3
3
0
k
8
1
0
1
2
5
V
2
3
4
6
7
1
I
n
p
u
t
4
7
0
5
6
0
k
1
k
L
P
F
2
7
p
2
2
0
0
2
2
0
0
5
V
2
2
0
0
1
O
u
t
p
u
t
T
r
a
n
s
i
s
t
o
r
u
s
e
d
P
N
P
:
2
S
A
1
1
7
5
T
r
a
n
s
i
s
t
o
r
u
s
e
d
N
P
N
:
2
S
C
2
7
8
5
D
e
l
a
y
t
i
m
e
1
9
0
n
s
(
e
x
.
T
H
3
2
8
L
N
L
S
-
2
6
2
0
T
o
u
k
o
u
m
a
d
e
)
(
N
o
n
-
i
n
v
e
r
t
e
d
s
i
g
n
a
l
)
(
N
o
n
-
i
n
v
e
r
t
e
d
s
i
g
n
a
l
)
(
I
n
v
e
r
t
e
d
s
i
g
n
a
l
)
5
1
0
0
0
p
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility fo
r
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same
.
7
CXL5506M/P
Example of Representative Characteristics
4.75
1
2
2
5.25
5
0
1
4.75
20
30
10
5.25
5
0
20
2
0
3
80
20
40
60
1
0
20
6
10
0
80
20
40
60
8
4
2
0
20
0
2
2
80
20
40
60
1
1
0
20
20
30
10
80
20
40
60
Ambient temperature [C]
Supply current vs. Ambient temperature
S
u
p
p
l
y
c
u
r
r
e
n
t
[
m
A
]
Ambient temperature [C]
Low frequency gain vs. Ambient temperature
L
o
w
f
r
e
q
u
e
n
c
y
g
a
i
n
[
d
B
]
Ambient temperature [C]
Frequency response vs. Ambient temperature
F
r
e
q
u
e
n
c
y
r
e
s
p
o
n
s
e
[
d
B
]
Ambient temperature [C]
Differential gain vs. Ambient temperature
D
i
f
f
e
r
e
n
t
i
a
l
g
a
i
n
[
%
]
Supply voltage [V]
Low frequency gain vs. Supply voltage
L
o
w
f
r
e
q
u
e
n
c
y
g
a
i
n
[
d
B
]
Supply voltage [V]
Supply current vs. Supply voltage
S
u
p
p
l
y
c
u
r
r
e
n
t
[
m
A
]
8
CXL5506M/P
4.75
Frequency response vs.Supply voltage
2
0
3
5.25
5
1
Differential gain vs. Supply voltage
6
10
0
8
4
2
4.75
5.25
5
4
2
6
0
2
10k
1M
100k
10M
Supply voltage [V]
F
r
e
q
u
e
n
c
y
r
e
s
p
o
n
s
e
[
d
B
]
D
i
f
f
e
r
e
n
t
i
a
l
g
a
i
n
[
%
]
Supply voltage [V]
Frequency response
Frequency [Hz]
G
a
i
n
[
d
B
]
9
CXL5506M/P
Package Outline
Unit: mm
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
42/COPPER ALLOY
8PIN SOP (PLASTIC)
6.1
+ 0.4
0.1
5
.
3
+
0
.
3
0
.
1
1.85
+ 0.4
0.15
0.1
+ 0.2
0.05
0.2
+ 0.1
0.05
0.45 0.1
1.27
4
1
7
.
9
0
.
4
6
.
9
0
.
5
0
.
2
0.24 M
0.1g
SOP-8P-L01
SOP008-P-0300
8
5
0.15
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
COPPER ALLOY
8PIN DIP (PLASTIC)
9.4 0.1
+ 0.4
2.54
1
4
5
8
1.2 0.15
0.5 0.1
3
.
0
M
I
N
0
.
5
M
I
N
3
.
7
0
.
1
+
0
.
4
7
.
6
2
6
.
4
0
.
1
+
0
.
3
0
.
2
5
0
.
0
5
+
0
.
1
0 to 15
0.5g
DIP-8P-01
DIP008-P-0300
CXL5506M
CXL5506P
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