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E93Y19-TE
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Input Signal Amplitude
V
SIG
500mVp-p (typ.), 572 mVp-p (max.)
(at internal clamp condition)
Functions
680-bit CCD register
Clock driver
Auto-bias circuit
Sync tip clamp circuit
Sample and hold circuit
Tripling PLL circuit
Inverted output
Structure
CMOS-CCD
Description
The CXL5512M/P are CMOS-CCD delay line ICs
designed for processing video signals. This ICs
provide a 1H delay time for NTSC signals including
the external lowpass filter.
Features
Single 5 V power supply
Low power consumption
Built-in peripheral circuit
Built-in tripling PLL circuit
Sync tip clamp mode
Absolute Maximum Ratings (Ta=25 C)
Supply voltage
V
DD
+6
V
Operating temperature Topr
10 to +60
C
Storage temperature
Tstg
55 to +150
C
Allowable power dissipation
P
D
CXL5512M
350
mW
CXL5512P
480
mW
Recommended Operating Range (Ta=25 C)
V
DD
5 V5 %
Recommended Clock Conditions (Ta=25 C)
Input clock amplitude
V
CLK
400mVp-p (Typ.)
Clock frequency
f
CLK
3.579545
MHz
Input clock waveform Sine wave
CMOS-CCD 1H Delay Line for NTSC
CXL5512M
CXL5512P
8 pin SOP (Plastic)
8 pin DIP (Plastic)
Block Diagram and Pin Configuration
V
SS
OUT
AB
IN
V
DD
CLK
VCO IN
CCD
(680bit)
1
2
3
4
5
6
7
8
Auto-bias circuit
Clamp circuit
Output circuit
(S/H 1 bit)
PLL
Timing circuit
Clock driver
Bias circuit A
Bias circuit B
VCO OUT
CXL5512M/P
--2--
CXL5512M/P
Pin Description
Electrical Characteristics
(Ta=25C, V
DD
=5 V, f
CLK
=3.579545 MHz, V
CLK
=400mVp-p, sine wave)
See "Electrical Characteristics Test Circuit".
1
2
3
4
5
6
7
8
IN
AB
OUT
V
SS
CLK
VCO IN
VCO OUT
V
DD
I
O
O
I
I
O
Signal input
Auto-bias DC output
Signal output
GND
Clock input (fsc)
VCO input
VCO output (3fsc)
5 V power supply
>10 K
40 to 500
>10 K
Pin No.
Symbol
I/O
Description
Impedance
Supply current
Low frequency gain
Frequency response
Differential gain
Differential phase
S/H pulse coupling
S/N ratio
I
DD
GL
fR
DG
DP
CP
SN
------
200kHz
500mVp-p
Sine wave
200kz
3.57 MHz
150mVp-p
Sine wave
5-staircase wave
(See Note 4.)
5-staircase wave
(See Note 4.)
No signal input
50 % white video signal
(See Note 6.)
a
6
12
20
mA
1
a
b
-2
0
2
dB
2
b
c
b
2.5
1.5
0.5
dB
3
d
c
0
3
5
%
4
d
c
0
3
5
degree
4
f
a
--
--
350
mVp-p
5
e
d
52
56
--
dB
6
Item
Symbol
Conditions
SW conditions
Min.
Typ.
Max.
Unit
Note
1
2
--3--
CXL5512M/P
NOTE
1 This is the IC supply current value during clock and signal input.
2 GL is the output gain of OUT pin when a 500 mVp-p, 200 kHz sine wave is fed to IN pin.
GL = 20 log
OUT pin output voltage [mVp-p]
[dB]
500 [mVp-p]
3 Indicates the dissipation at 3.58 MHz in relation to 200 kHz. From the output voltage at OUT pin when a
150 mVp-p, 200 kHz sine wave is fed to IN pin, and from the output voltage at OUT pin when a 150 mVp-p,
3.58 MHz sine wave is fed to the same, calculation is made according to the following formula.
fR = 20 log
OUT pin output voltage (3.58 MHz) [mVp-p]
[dB]
OUT pin output voltage (200 kHz) [mVp-p]
4 In Fig. below, the differential gain (DG) and the differential phase (DP) are tested with a vector scope when
the 5-staircase wave is fed.
5 Leakage of internal clock components and related high frequency component to the output signal, during
no signal input, is tested.
143mV
357mV
143mV
500mV
1H 63.56S
Test value
(mVp-p)
--4--
CXL5512M/P
6 S/N ratio during a 50 % white video signal input shown in Fig. below is tested at the video noise meter, in
BPF 100 kHz to 4 MHz, Sub Carrier Trap mode.
CLOCK
321mV
143mV
1H 63.56S
178mV
400mVp-p (Typ.)
fSC (3.579545MHz) Sine wave
--5--
CXL5512M/P
CXL5512M/P
SW2
1
a
b
c
d
e
SW1
f
0
3
50
5.8M
10.7M
0
3
50
4.1M
10.7M
200
50
fSC (3.579545MHz)
400mVp-p
Sine wave
5V
+15V
0.1
0.1
2.2k
V
DD
VCO IN
CLK
IN
AB
OUT
V
SS
BPF
LPF
c
d
3
3
a
b
A
1M
VCO OUT
1
3
4
5
6
7
8
5-staircase wave
BPF frequency response
Note 1)
Note 2)
LPF frequency response
Note 1)
Note 2)
Frequency
Frequency
2200p
6.8
Oscilloscop
e
Spectrum
analyzer
Vector scope
Noise
meter
0.1
2
200kHz
150mVp-p
Sine wave
3.57MHz
150mVp-p
Sine wave
200kHz
500mVp-p
Sine wave
50 % white
video signal
[dB]
[dB]
[Hz]
[Hz]
Electrical Characteristics Test Circuit
--6--
CXL5512M/P
0.1
0.1
1
1.8k
2.2k
3fSC OUT
6.8
2200p
CLK
IN
AB
OUT
CXL5512M/P
1
LPF
5V
33k
56k
470
1k
2.2k
5V
fSC (3.579545MHz)
400mVp-p
Sine wave
5V
2SC403
1M
V
DD
VCO IN
V
SS
VCO OUT
1
3
4
5
6
7
8
When VCO OUT (7 Pin) in use
Output
Input
Transistor used
NPN: 2SC403
Transistor used
PNP: 2SA1175
0.1
2
7
Application Circuit
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party and other right due to same.
--7--
CXL5512M/P
Example of Representative Characteristics
20
18
16
14
12
10
20
0
20
40
60
80
Ambient temperature (C)
Supply current (mA)
Supply current vs. Ambient temperature
1
0
1
2
3
20
0
20
40
60
80
Ambient temperature (C)
Low frequency gain (dB)
Low frequency gain vs. Ambient temperature
0
1
2
3
20
0
20
40
60
80
Ambient temperature (C)
Frequency response (dB)
Frequency response vs. Ambient temperature
16
14
12
10
4.7
5
5
5.25
Supply voltage (V)
Supply current (mA)
Supply current vs. Supply voltage
18
20
--8--
CXL5512M/P
1
0
1
2
3
Supply voltage (V)
Low frequency gain (dB)
Low frequency gain vs. Supply voltage
4.7
5
5
5.25
0
1
2
3
Supply voltage (V)
Frequency response (dB)
Frequency response vs. Supply voltage
4.7
5
5
5.25
0
2
4
6
8
10
10k
100k
1M
10
M
Frequency (Hz)
Gain (dB)
Frequency response
M
PACKAGE STRUCTURE
MOLDING COMPOUND
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY / PHENOL RESIN
SOLDER PLATING
42 ALLOY
8
5
1
4
4.4 0.1
+ 0.3
1.27
0.4 0.05
+ 0.1
0.12
0 to 10
1.25 0.15
+ 0.4
0.15 0.05
+ 0.1
0.10
6.4
0.4
A
0.1 0.1
+ 0.15
0.5
0.2
5.0 0.1
+ 0.4
0.1g
SOP-8P-L03
SOP008-P-0225-A
8PIN SOP (PLASTIC)
DETAILA
SONY CODE
EIAJ CODE
JEDEC CODE
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY RESIN
SOLDER PLATING
COPPER ALLOY
8PIN DIP (PLASTIC) 300mil
9.4 0.1
+ 0.4
2.54
1
4
5
8
1.2 0.15
0.5 0.1
3.0 MIN
0.5 MIN
3.7 0.1
+ 0.4
7.62
6.4 0.1
+ 0.3
0.25 0.05
+ 0.1
0 to 15
0.5g
DIP-8P-01
DIP008-P-0300-A
Package Outline Unit : mm
CXL5512M
CXL5512P
CXL5512M/P
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