1
CXL5515M/P
E94904-ST
CMOS-CCD 1H Delay Line for PAL
Description
The CXL5515M/P are CMOS-CCD delay line ICs
designed for processing video signals. This ICs
provide a 1H delay time for PAL chroma signals
including the external lowpass filter.
Features
Single 5V power supply
Low power consumption
Built-in peripheral circuit
Built-in tripling PLL circuit
Center bias mode
Absolute Maximum Ratings (Ta = 25C)
Supply voltage
V
DD
+6
V
Operating temperature Topr
10 to +60
C
Storage temperature
Tstg
55 to +150
C
Allowable power dissipation
P
D
CXL5515M
350
mW
CXL5515P
480
mW
Recommended Operating Range (Ta = 25C)
V
DD
5V 5%
Recommended Clock Conditions (Ta = 25C)
Input clock amplitude
V
CLK
0.2 to 1.0Vp-p (0.4Vp-p Typ.)
Clock frequency
f
CLK
4.433619MHz
Input clock waveform
Sine wave
Block Diagram and Pin Configuration (Top View)
Input Signal Amplitude
V
SIG
500mVp-p (Typ.), 575mVp-p (Max.)
Functions
848-bit CCD register
Clock driver
Auto bias circuit
Input center bias circuit
Sample and hold circuit
Tripling PLL circuit
Inverted output
Structure
CMOS-CCD
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Auto-bias circuit
CCD
(848 bit)
Output circuit
(S/H 1 bit)
Bias circuit
PLL
Timing circuit
Clock driver
Bias circuit A
Bias circuit B
5
6
7
8
V
DD
VCO OUT
VCO IN
CLK
2
3
4
1
IN
AB
OUT
V
SS
CXL5515M
CXL5515P
8 pin SOP (Plastic)
8 pin DIP (Plastic)
2
CXL5515M/P
Pin Description
Electrical Characteristics
(Ta = 25C, V
DD
=5V, f
CLK
= 4.433619MHz, V
CLK
= 400mVp-p, sine wave)
See "Electrical Characteristics Test Circuit".
1
2
3
4
5
6
7
8
IN
AB
OUT
V
SS
CLK
VCO IN
VCO OUT
V
DD
I
O
O
--
I
I
O
--
Signal input
Auto-bias DC output
Signal output
GND
Clock input (fsc)
VCO input
VCO output (3fsc)
5V power supply
>10K
40 to 500
>10K
Pin No.
Symbol
I/O
Description
Impedance
Supply current
Low frequency gain
Frequency response
Differential gain
Differential phase
S/H pulse coupling
S/N ratio
I
DD
GL
f
R
DG
DP
CP
SN
--
200kHz
500mVp-p
Sine wave
200kHz
4.434MHz
150mVp-p Sine wave
5-staircase wave
(See Note 4.)
5-staircase wave
(See Note 4.)
No signal input
50% white video signal
(See Note 6.)
a
--
10
15
20
mA
1
a
b
2
0
2
dB
2
b
2.7
1.7
2.7
dB
3
d
c
0
3
5
%
4
d
c
0
3
5
degree
4
f
a
--
--
350
mVp-p
5
e
d
52
56
--
dB
6
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
1
2
SW conditions
NOTE
b
c
3
CXL5515M/P
NOTE
1. This is the IC supply current value during clock and signal input.
2. GL is the output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin.
GL = 20 log
OUT pin output voltage [mVp-p]
[dB]
500 [mVp-p]
3. Indicates the dissipation at 4.434MHz in relation to 200kHz. From the output voltage at OUT pin when a
150mVp-p, 200kHz sine wave is fed to IN pin, and from the output voltage at OUT pin when a 150mVp-p,
4.434MHz sine wave is fed to the same, calculation is made according to the following formula.
f
R
= 20 log
OUT pin output voltage (4.434MHz) [mVp-p]
[dB]
OUT pin output voltage (200kHz) [mVp-p]
4. In Fig. below, the differential gain (DG) and the differential phase (DP), are tested with a vector scope
when the 5-staircase wave is fed.
5. Leakage of internal clock components and related high frequency component to the output signal, during
no signal input, is tested.
150mV
1H 64s
350mV
150mV
500mV
Test value
[mVp-p]
4
CXL5515M/P
6. S/N ratio during a 50% white video signal input shown in Fig. below is tested at the video noise meter, in
BPF 100kHz to 5MHz, Sub Carrier Trap mode.
CLOCK
1H 64s
175mV
150mV
325mV
400mVp-p (Typ.)
f
SC
(4.433619MHz) Sine wave
5
CXL5515M/P
V
DD
VCO OUT
VCO IN
CLK
IN
AB
OUT
V
SS
CXL5515M/P
0.1
6.8
2200p
0.1
0.1
fsc (4.433619MHz)
400mVp-p
Sine wave
5V
200kHz
500mVp-p
Sine wave
a
200kHz
150mVp-p
Sine wave
b
4.434MHz
150mVp-p
Sine wave
c
5-staircase wave
d
50% white
video signal
e
f
1
SW1
Oscilloscope
Spectrum analyzer
Vector scope
Noise meter
b
SW2
2.2k
+15V
c
a
LPF
Note1)
d
BPF
Note 2)
Note1)
Note 2)
[dB]
Frequency [Hz]
6M
13.3M
3
50
0
LPF frequency response
[dB]
Frequency [Hz]
6M
13.3M
3
50
0
BPF frequency response
50
200
5
6
7
8
2
3
4
1
3
3
Electrical Characteristics Test Circuit
6
CXL5515M/P
Application Circuit
V
DD
VCO OUT
VCO IN
CLK
IN
AB
OUT
V
SS
CXL5515M/P
0.1
6.8
2200p
0.1
0.1
fsc (4.433619MHz)
400mVp-p
Sine wave
5V
1
33k
2
3
4
1
5
6
7
8
1
470
56k
1k
LPF
5V
2.2k
Output
Transistor used
NPN: 2SC403
7
When VCO OUT (7Pin) in use
5V
2.2k
3fsc OUT
1.8k
2SC403
Input
Transistor used
NPN: 2SA403
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
7
CXL5515M/P
Example of Representative Characteristics
4.75
Supply current vs. Supply voltage
Supply voltage [V]
5
5.25
10
15
20
Supply current [mA]
20
Supply current vs. Ambient temperature
Ambient temperature [C]
40
80
10
14
20
Supply current [mA]
12
18
16
0
60
20
4.75
Low frequency Gain vs. Supply voltage
Supply voltage [V]
5
5.25
2
1
1
Low frequency Gain [dB]
0
4.75
Frequency response vs. Supply voltage
Supply voltage [V]
5
5.25
3
2
0
Frequency response [dB]
1
Low frequency Gain vs. Ambient temperature
2
1
1
Low frequency Gain [dB]
0
20
Ambient temperature [C]
40
80
0
60
20
4.75
Differential gain vs. Supply voltage
Supply voltage [V]
5
5.25
0
2
10
Differential gain [%]
6
8
4
8
CXL5515M/P
Frequency response vs. Ambient temperature
3
2
0
Frequency response [dB]
1
20
Ambient temperature [C]
40
80
0
60
20
Differential gain vs. Ambient temperature
0
2
10
Differential gain [%]
6
8
4
20
Ambient temperature [C]
40
80
0
60
20
Frequency response
10
6
2
Gain [dB]
2
10k
Frequency [Hz]
10M
100k
1M
8
0
4
9
CXL5515M/P
Package Outline
Unit : mm
CXL5515M
CXL5515P
M
PACKAGE STRUCTURE
MOLDING COMPOUND
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY / PHENOL RESIN
SOLDER PLATING
42 ALLOY
8
5
1
4
4.4 0.1
+ 0.3
1.27
0.4 0.05
+ 0.1
0.12
0 to 10
1.25 0.15
+ 0.4
0.15 0.05
+ 0.1
0.10
6.4
0.4
A
0.1 0.1
+ 0.15
0.5
0.2
5.0 0.1
+ 0.4
0.1g
SOP-8P-L03
SOP008-P-0225-A
8PIN SOP (PLASTIC)
DETAILA
SONY CODE
EIAJ CODE
JEDEC CODE
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY RESIN
SOLDER PLATING
COPPER ALLOY
8PIN DIP (PLASTIC) 300mil
9.4 0.1
+ 0.4
2.54
1
4
5
8
1.2 0.15
0.5 0.1
3.0 MIN
0.5 MIN
3.7 0.1
+ 0.4
7.62
6.4 0.1
+ 0.3
0.25 0.05
+ 0.1
0 to 15
0.5g
DIP-8P-01
DIP008-P-0300-A
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