CXP80712B/80716B/80720B/80724B

E95Z43A71

CMOS 8-bit Single Chip Microcomputer

Description

The CXP80712B/80716B/80720B/80724B is a CMOS

8-bit microcomputer which consists of A/D converter,
serial interface, timer/counter, time base timer, high
precision timing pattern generation circuit, PWM output,
VISS/VASS circuit, 32kHz timer/counter, remote
control receiving circuit, VSYNC separator and the
measurement circuit which measures signals of
capstan FG and drum FG/PG and other servo
systems, as well as basic configurations like 8-bit
CPU, ROM, RAM and I/O port. They are integrated
into a single chip.

Also CXP80712B/80716B/80720B/80724B provides

sleep/stop function which enables to lower power
consumption.

Features
· A wide instruction set (213 instructions) which cover various types of data

-- 16-bit arithmetic/multiplication and division/boolean bit operation instructions

· Minimum instruction cycle

250ns at 16MHz operation
122µs at 32kHz operation

· Incorporated ROM capacity

12K bytes (CXP80712B)
16K bytes (CXP80716B)
20K bytes (CXP80720B)
24K bytes (CXP80724B)

· Incorporated RAM capacity

800 bytes

· Peripheral functions

-- A/D converter

8 bits, 12 channels, successive approximation system
(Conversion time of 20.0µs/16MHz)

-- Serial Interface

Incorporated 8-bit and 8-stage FIFO, 1 channel
(1 to 8 bytes auto transfer)
8-bit serial I/O, 1 channel

-- Timer

8-bit timer
8-bit timer/counter
19-bit time base timer
32kHz timer/counter

-- High precision timing pattern generator

PPG for 19 pins, 32-stage programmable
RTG for 5 pins, 2 channels

-- PWM/DA gate output

12 bits, 2 channels (Repetitive frequency of 62.5kHz/16MHz)

-- Servo input control

Capstan FG, Drum FG/PG, CTL input

-- VSYNC separator
-- FRC capture unit

Incorporated 26-bit and 8-stage FIFO

-- PWM output

14 bits, 1 channel

-- VISS/VASS circuit

Pulse duty auto detection circuit

-- Remote control receiving circuit

8-bit pulse measurement counter, 6-stage FIFO

· Interruption

21 factors, 15 vectors, multi-interruption possible

· Standby mode

SLEEP/STOP

· Package

100-pin plastic QFP/LQFP

· Piggyback/evaluation chip

CXP87700 100-pin ceramic PQFP

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

100 pin QFP (PIastic)

Structure

Silicon gate CMOS IC

100 pin LQFP (PIastic)

CXP80712B/80716B/80720B/80724B

PA0 to PA7

PB0 to PB7

PC0 to PC7

PD0 to PD7

PE0 to PE1

PE2 to PE7

PF0 to PF3

PF4 to PF7

PG0 to PG7

PI1 to PI7

PJ0 to PJ7

Vss
V

RST
XTAL

EXTAL

CLOCK

GENERATOR/

SYSTEM CONTROL

RAM

800 BYTES

SPC700

CPU CORE

ROM

12K/16K/20K/24K

BYTES

INTERRUPT CONTROLLER

32kHz

TIMER/COUNTER

FIFO

FRC

CAPTURE UNIT

PROGRAMMABLE

PATTERN

GENERATOR

RAM

AVss

REF

A/D CONVERTER

SERIAL

INTERFACE UNIT

(CH0)

FIFO

8 BIT TIMER/COUNTER 0

8 BIT TIMER 1

V SYNC SEPARATOR

14 BIT PWM GENERATOR

12 BIT PWM GENERATOR CH0

SERVO INPUT

CONTROL

CAPSTAN

DRUM

CTL

12 BIT PWM GENERATOR CH1

DAB1

DAA1

PWM1

DAB0

DAA0

PWM0

PWM

DPG

RMC

PBCTL

DFG

CFG

EXI1

EXI0

SYNC1

SYNC0

SCK1

SO1

SI1

SCK0

SO0

SI0

CS0

AN0 to AN11

REALTIME

PULSE

GENERATOR

INT2

INT0

INT1

PORT A

PORT B

PORT C

PORT D

PORT E

PORT F

PORT G

PORT H

PORT I

PH0 to PH7

TEX

NMI

PRESCALER/

TIME BASE TIMER

VISS/VASS

REMOCON INPUT

FIFO

SERIAL INTERFACE UNIT

(CH1)

CH0

CH1

PORT J

PPO0 to PPO18

ADJ

RTO3 to RTO7

NMI

DDO

Block Diagram

CXP80712B/80716B/80720B/80724B

Pin Assignment 1 (Top View) 100 pin QFP package

PB5/PPO13

PB4/PPO12

PB3/PPO11

PB2/PPO10

PB1/PPO9

PB0/PPO8

PC7/RTO7

PC6/RTO6

PC5/RTO5

PC4/RTO4

PC3/RTO3

PC2/PPO18

PC1/PPO17

PC0/PPO16

PJ7

PJ6

PJ5

PJ4

PJ3

PJ2

PJ1

PJ0

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PI6/SO1

PI7/SI1

PE0/INT0

PE1/EC/INT2

PE2/PWM0

PE3/PWM1

PE4/DAA0

PE5/DAA1

PE6/DAB0

PE7/DAB1

PG0/CFG

PG1/DFG

PG2/DPG

PG3/PBCTL

PG4/SYNC0

PG5/SYNC1

PG6/EXI0

PG7/EXI1

AN0

AN1

AN2

AN3

PF0/AN4

PF1/AN5

PF2/AN6

PF3/AN7

REF

PF4/AN8

PB6/PPO14

PB7/PPO15

PA0/PPO0

PA1/PPO1

PA2/PPO2

PA3/PPO3

PA4/PPO4

PA5/PPO5

PA6/PPO6

PA7/PPO7

TEX

PI1/RMC

PI2/PWM

PI3/TO/DDO/ADJ

PI4/INT1/NMI

PI5/SCK1

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

RST

XTAL

EXTAL

CS0

SI0

SO0

SCK0

PF7/AN11

PF6/AN10

PF5/AN9

31 32 33

41 42 43 44 45 46 47 48 49 50

88 87 86 85

100 99 98 97 96 95 94

Note)

1. NC (Pin 90) is always connected to V

2. Vss (Pins 41 and 88) are both connected to GND.

3. MP (Pin 39) is always connected to GND.

CXP80712B/80716B/80720B/80724B

Pin Assignment 2 (Top View) 100 pin LQFP package

PB3/PPO11

PB2/PPO10

PB1/PPO9

PB0/PPO8

PC7/RTO7

PC6/RTO6

PC5/RTO5

PC4/RTO4

PC3/RTO3

PC2/PPO18

PC1/PPO17

PC0/PPO16

PJ7

PJ6

PJ5

PJ4

PJ3

PJ2

PJ1

PJ0

PD7

PD6

PD5

PD4

PD3

PE1/EC/INT2

PE2/PWM0

PE3/PWM1

PE4/DAA0

PE5/DAA1

PE6/DAB0

PE7/DAB1

PG0/CFG

PG1/DFG

PG2/DPG

PG3/PBCTL

PG4/SYNC0

PG5/SYNC1

PG6/EXI0

PG7/EXI1

AN0

AN1

AN2

AN3

PF0/AN4

PF1/AN5

PF2/AN6

PF3/AN7

REF

PB4/PPO12

PB5/PPO13

PB6/PPO14

PB7/PPO15

PA0/PPO0

PA1/PPO1

PA2/PPO2

PA3/PPO3

PA4/PPO4

PA5/PPO5

PA6/PPO6

PA7/PPO7

TEX

PI1/RMC

PI2/PWM

PI3/TO/DDO/ADJ

PI4/INT1/NMI

PI5/SCK1

PI6/SO1

PI7/SI1

PE0/INT0

PD2

PD1

PD0

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

RST

XTAL

EXTAL

CS0

SI0

SO0

SCK0

PF7/AN11

PF6/AN10

PF5/AN9

PF4/AN8

26 27 28 29 30

31 32 33

41 42 43 44 45 46 47 48 49 50

88 87 86 85

100 99 98 97 96 95 94

Note)

1. NC (Pin 88) is always connected to V

2. Vss (Pins 39 and 86) are both connected to GND.

3. MP (Pin 37) is always connected to GND.

CXP80712B/80716B/80720B/80724B

Output/
Real-time
output

I/O/
Real-time
output

I/O

Input/Input

Input/Input/Input

Output/Output

Input

Input/Input

Output/Input

I/O

Ouput

Input

(Port A)
8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)

(Port B)
8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)

(Port C)
8-bit I/O port. I/O can be set
in a unit of single bits.
Data is gated with PPO or
RTO contents by OR-gate
and they are output.
(8 pins)

(Port D)
8-bit I/O port. I/O can be set in a unit of 4 bits.
Can 12mA sink current.
(8 pins)

(Port E)
8-bit port. Lower 2 bits are for
inputs; upper 6 bits are for
outputs.
(8 pins)

Analog input pins to A/D converter. (12 pins)

(Port F)
Lower 4 bits are for inputs; upper 4 bits are for outputs.
Lower 4 bits also serve as standby release input pin.
(8 pins)

Serial clock (CH0) I/O pin.

Serial data (CH0) output pin.

Serial data (CH0) input pin.

Serial chip select (CH0) input pin.

External event
input pin for
timer/counter.

Input pin to request
external interruption.
Active when falling edge.

Input pin to request external interruption.
Active when falling edge.

PWM output pins.
(2 pins)

DA gate pulse output pins.
(4 pins)

Programmable pattern generator (PPG)
output.
Functions as high precision real-time
pulse output port.
(19 pins)

Real-time pulse generator (RTG) output.
Functions as high precision real-time
pulse output port. (5 pins)

Symbol

I/O

Description

PA0/PPO0

PA7/PPO7

PB0/PPO8

PB7/PPO15

PC0/PPO16

PC2/PPO18

PC3/RTO3

PC7/RTO7

PD0 to PD7

PE0/INT0

PE1/EC/INT2

PE2/PWM0

PE3/PWM1

PE4/DAA0

PE5/DAA1

PE6/DAB0

PE7/DAB1

AN0 to AN3

PF0/AN4

PF3/AN7

PF4/AN8

PF7/AN11

SCK0

SO0

SI0

CS0

Pin Description

CXP80712B/80716B/80720B/80724B

PG0/CFG

PG1/DFG

PG2/DPG

PG3/PBCTL

PG4/SYNC0

PG5/SYNC1

PG6/EXI0

PG7/EXI1

PH0 to PH7

PI1/RMC

PI2/PWM

PI3/TO/
DDO/ADJ

PI4/INT1/
NMI

PI5/SCK1

PI6/SO1

PI7/SI1

PJ0 to PJ7

EXTAL

XTAL

TEX

RST

REF

AVss

Vss

Input/Input

Output

I/O/Input

I/O/Output

I/O/Output/
Output/Output

I/O/Input/Input

I/O/I/O

I/O/Output

I/O/Input

I/O

Input

Output

Input

Output

Input

Capstan FG input pin.

Drum FG input pin.

Drum PG input pin.

Playback CTL pulse input pin.

Composite sync signal input pin.
(2 pins)

External input pin to FRC capture unit.
(2 pins)

(Port G)
8-bit input port.
(8 pins)

(Port H)
8-bit output port; N-ch open drain output of medium drive voltage (12V)
and large current (12mA).
(8 pins)

Remote control receiving circuit input pin.

14-bit PWM output pin.

Timer/counter, CTL duty detection, 32kHz
oscillation adjustment output pin.

Input pin to request external interruption and non
maskable interruption. Active when falling edge.

Serial clock (CH1) I/O pin.

Serial data (CH1) output pin.

Serial data (CH1) input pin.

(Port I)
7-bit I/O port.
I/O port can be
set in a unit of
single bits.
(7 pins)

(Port J)
8-bit I/O port. Function as standby release input can be set in a unit of
single bits. I/O can be set in a unit of single bits.

Connecting pin of crystal oscillator for system clock. When supplying
the external clock, input the external clock to EXTAL pin and input
opposite phase clock to XTAL pin.

Connecting pin of crystal oscillator for 32kHz timer clock. When used
as event counter, input to TEX pin and leave TX pin open. (Feedback
resistor is not removed.)

System reset pin of active Low level.

Test mode input pin. Always connect to GND.

Positive power supply pin of A/D converter.

Reference voltage input pin of A/D converter.

GND pin of A/D converter.

Positive power supply pin.

NC pin.
Connect this pin to V

for normal operation.

GND pin. Connect both Vss pins to GND.

Symbol

I/O

Description

CXP80712B/80716B/80720B/80724B

Data bus

RD (Port D)

Port D direction

Port D data

Large
current
12mA

PPO, RTO data

Data bus

RD (Port C)

Port C direction

Port C data

Input
protection
circuit

Port C

16 pins

Hi-Z

When reset

PA0/PPO0

PA7/PPO7

PB0/PPO8

PB7/PPO15

PC0/PPO16

PC2/PPO18

PC3/RTO3

PC7/RTO7

Port D

8 pins

Hi-Z

PD0

PD7

PPO data

Data bus

Output becomes active from high
impedance by data writing to port register.

Ports A and B data

RD (Ports A and B)

Input/Output Circuit Formats for Pins

Port A

Port B

Circuit format

CXP80712B/80716B/80720B/80724B

RD (Port F)

Data bus

Input multiplexer

A/D converter

2 pins

Hi-Z

When reset

Circuit format

PE0/INT0
PE1/EC/INT2

PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1

4 pins

2 pins

4 pins

Hi-Z

High level

PE6/DAB0
PE7/DAB1

Data bus

RD (Port E)

DA gate output

Hi-Z control

MPX

Port E data

Port/DA output
select

Data bus

RD (Port E)

DA gate output
PWM output

Hi-Z control

MPX

Port E data

Port/DA output
select

RD (Port E)

Data bus

Schmitt input

Port E

AN0

AN3

A/D converter

Input multiplexer

4 pins

PF0/AN4

PF3/AN7

Port F

Port E

CXP80712B/80716B/80720B/80724B

4 pins

Hi-Z

When reset

Circuit format

PF4/AN8

PF7/AN11

A/D
converter

Data bus

RD
(Port F)

Port/AD select

Port F data

Input multiplexer

Port F

8 pins

Hi-Z

PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0
PG5/SYNC1
PG6/EXI0
PG7/EXI1

RD (Port G)

Data bus

Schmitt input

Servo input

Note) For PG4/SYNC0 and PG5/SYNC1, CMOS schmitt input or TTL schmitt
input can be selected with the mask option.

Port G

8 pins

Hi-Z

PH0

PH7

Data bus

RD (Port H)

Port H data

Large current
12mA

Medium drive
voltage 12V

Port H

2 pins

Hi-Z

PI2/PWM
PI3/TO/
DDO/ADJ

PI2: 14-bit PWM
PI3: Timer/counter,
CTL duty detection circuit,
32kHz timer

MPX

Port I data

Data bus

RD (Port I)

Port I direction

Port I function
select

Port I

CXP80712B/80716B/80720B/80724B

SO0 output enable

From Serial CH0

3 pins

Hi-Z

When reset

Circuit format

PI1/RMC
PI4/INT1/NMI
PI7/SI1

PI5/SCK1
PI6/SO1

2 pins

8 pins

1 pin

Hi-Z

PJ0

PJ7

Standby release

Port J data

Data bus

RD
(Port J)

Port J direction

Edge detection

MPX

Port I data

Data bus

RD (Port I)

Port I direction

Port I function
select

MPX

Serial CH1

Note)
PI5 is schmitt input
PI6 is inverter input

Serial CH1

PI1: Remote control circuit
PI4: Interruption circuit
PI7: Serial CH1

Port I data

Data bus

RD (Port I)

Port I direction

Schmitt input

Port J

CS0

SI0

Serial CH0

Schmitt input

2 pins

SO0

Port I

CXP80712B/80716B/80720B/80724B

2 pins

Oscillation

When reset

Circuit format

EXTAL
XTAL

EXTAL

XTAL

· Shows the circuit
composition during
oscillation.

· Feedback resistor is
removed and XTAL
becomes High level
during stop.

2 pins

Oscillation

TEX
TX

TEX

· Shows the circuit
composition during
oscillation.
· Feedback resistor is
removed during 32kHz
oscillation circuit stop
by software.
At this time TEX pin
outputs Low level and TX
pin outputs High level.

32kHz
timer counter

1 pin

Hi-Z

SCK0

SCK0 output enable

Internal serial clock
from serial CH0

Schmitt input

External serial clock
to serial CH0

1 pin

Low level

RST

Schmitt input

Pull-up resistor

Mask option

CXP80712B/80716B/80720B/80724B

, V

and V

OUT

must not exceed V

+ 0.3V.

The large current output ports are Port D (PD) and Port H (PH).

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

better take place under the recommended operating conditions. Exceeding those conditions may

adversely affect the reliability of the LSI.

Supply voltage

Input voltage

Output voltage

Medium drive output voltage

High level output current

High level total output current

Low level total output current

Operating temperature

Storage temperature

Allowable power dissipation

OUT

OUTP

OLC

Topr

Tstg

Low level output current

0.3 to +7.0

AVss to +7.0

0.3 to +0.3

0.3 to +7.0

0.3 to +15.0

130

20 to +75

55 to +150

600

380

°C

Port H (PH)

Total of output pins

Other than large current output
port (value per pin)

Large current port

(value per pin)

Total of output pins

QFP package type

LQFP package type

Item

Symbol

Rating

Unit

Remarks

Absolute Maximum Ratings

(Vss = 0V)

CXP80712B/80716B/80720B/80724B

Analog power supply

HIgh level
input voltage

Low level
input voltage

Operating temperature

Supply voltage

5.5

+ 0.3

0.3V

0.2V

0.8

0.4

+75

°C

Item

Symbol

Min.

Max.

Unit

Remarks

4.5

3.5

2.7

2.5

4.5

0.7V

0.8V

2.2

0.4

0.3

IHS

IHTS

IHEX

ILS

ILTS

ILEX

Topr

Guaranteed operation range for 1/2, 1/4
frequency dividing clock

Guaranteed operation range for 1/16 frequency
dividing clock or during SLEEP mode.

Guaranteed operation range by TEX clock

Guaranteed data hold operation range
during STOP

CMOS schmitt input

TTL schmitt input

EXTAL pin

TEX pin

CMOS schmitt input

TTL schmitt input

EXTAL pin

TEX pin

and V

should be set to the same voltage.

Normal input port (each pin of PC, PD, PE0, PE1, PF0 to PF3, PG, PI and PJ), MP pin.

Each pin of CS0, SI0, SCK0, RST, PE0/INT0, PE1/EC/INT2, PG (For PG4 and PG5, when CMOS schmitt

input is selected with mask option), PI1/RMC, PI4/INT1/NMI, PI5/SCK1 and PI7/SI1.

Each pin of PG4 and PG5 (When TTL schmitt input is selected with mask option)

Specifies only during external clock input.

Specifies only during event count clock input.

Recommended Operating Conditions

(Vss = 0V)

CXP80712B/80716B/80720B/80724B

= 4.5V, I

= 0.5mA

= 4.5V, I

= 1.2mA

= 4.5V, I

= 1.8mA

= 4.5V, I

= 3.6mA

= 4.5V, I

= 12.0mA

= 5.5V, V

= 5.5V

= 5.5V, V

= 0.4V

= 5.5V, V

= 5.5V

High level
output voltage

4.0

3.5

0.5

0.1

1.5

µA

PD, PH

PA to PD,
PE2 to PE7,
PF4 to PF7,
PH (V

only)

PI1 to PI7
PJ, SO0, SCK0

EXTAL

TEX

RST

Item

Symbol

Pins

Conditions

Min.

Clock 1MHz
0V other than the measured pins

DD1

LOH

DDS1

DD2

DDS2

DDS3

IHE

ILE

IHT

ILT

ILR

Low level
output voltage

Input current

Typ.

0.4

0.6

1.5

400

±10

Max. Unit

DC Characteristics

Electrical Characteristics

(Ta = 20 to +75°C, Vss = 0V)

RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current

when no resistance is selected.

When entire output pins are open.

When setting upper 2 bits (CPU clock selection) of clock control register (CLC: 00FE

) to "00" and

operating in high speed mode (1/2 frequency dividing clock).

Supply current

Input capacity

= 5.5V,

= 0.4V

= 5.5V,

= 0, 5.5V

= 5.5V

= 12V

I/O leakage
current

Open drain
output leakage
current (N-CH
Tr off state)

PA to PG,
PI, PJ, MP
AN0 to AN3,
CS0, SI0, SO0
SCK0, RST

1.1

100

µA

PC, PD,
PE0 to 1,
PF0 to 3, PG,
PI, PJ, AN,
SCK0, SI0,
CS0, EXTAL,
XTAL, TEX,
TX, RST, MP

16MHz crystal oscillation
(C

= C

= 15pF), V

= 5.5V

16MHz crystal oscillation
(C

= C

= 15pF), V

= 5.5V, SLEEP mode

32kHz crystal oscillation
(C

= C

= 47pF), V

= 3.3V

32kHz crystal oscillation
(C

= C

= 47pF), V

= 3.3V, SLEEP mode

= 5.5V, STOP mode (termination of

32kHz and 16MHz crystal oscillation)

CXP80712B/80716B/80720B/80724B

sys indicates three values according to the contents of the clock control register (CLC; 00FE

) upper 2 bits

(CPU clock selection).

sys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

EXTAL

0.4V

1/fc

External clock

EXTAL

XTAL

74HC04

Crystal oscillation
Ceramic oscillation

EXTAL

XTAL

32kHz clock applied condition
crystal oscillation

TEX

AC Characteristics

(1) Clock timing

System clock frequency

System clock input pulse
width

System clock input
rise and fall times

Event count clock input
pulse width

Event count clock input
rise and fall times

System clock frequency

Event count clock input
pulse width

Event count clock input
rise and fall times

XTAL
EXTAL

TEX
TX

TEX

MHz

kHz

µs

Item

Symbol

Pins

Conditions

Unit

Fig. 1,
Fig. 2

Fig. 1,
Fig. 2 (External clock drive)

Fig. 1, Fig. 2
(External clock drive)

Fig. 3

Fig. 2 V

= 2.7 to 5.5V

(32kHz clock applied condition)

Fig. 3

Min.

sys

Typ.

32.768

Max.

200

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V)

Fig. 1. Clock timing

Fig. 2. Clock applied condition

TEX
EC

0.2V

0.8V

Fig. 3. Event count clock timing

CXP80712B/80716B/80720B/80724B

Input mode

Output mode

Input mode

Output mode

SCK0 input mode

SCK0 output mode

SCK0 input mode

SCK0 output mode

SCK0 input mode

SCK0 output mode

Chip select transfer mode
(SCK0 = output mode)

Chip select transfer mode

Note 1)

sys indicates three values according to the contents of the clock control register (CLC; 00FE

) upper

2 bits (CPU clock selection).

sys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL.

(2) Serial transfer (CH0)

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V)

Item

CS0

SCK0

delay time

CS0

SCK0

float delay time

CS0

SO0

delay time

CS0

SO0

float delay time

CS0
High level width

SCK0
cycle time

SCK0
High and Low level widths

SI0 input setup time
(for SCK0

)

SI0 input hold time
(for SCK0

)

SCK0

SO0 delay time

DCSK

DCSKF

DCSO

DCSOF

WHCS

KCY

SIK

KSI

KSO

SCK0

SO0

CS0

SCK0

SI0

SO0

Symbol

Min.

sys + 200

16000/fc

sys + 100

8000/fc 50

100

200

sys + 200

100

sys + 200

100

Max.

Unit

Condition

CXP80712B/80716B/80720B/80724B

Fig. 5. Serial transfer timing (CH1)

SCK1

SI1

SO1

KCY

0.2V

0.8V

SIK

KSI

KSO

Input data

Output data

0.2V

0.8V

0.2V

0.8V

Serial transfer (CH1)

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V)

Item

Symbol

Pins

Min.

Max.

Unit

Conditions

SCK1 cycle time

SCK1 High and Low
level widths

SI1 input setup time
(for SCK1

)

SI1 input hold time
(for SCK1

)

SCK1

SO1 delay time

KCY

SIK

KSI

KSO

SCK1

SI1

SO1

Input mode

Output mode

Input mode

Output mode

SCK1 input mode

SCK1 output mode

SCK1 input mode

SCK1 output mode

SCK1 input mode

SCK1 output mode

1000

16000/fc

400

8000/fc 50

100

200

100

200

100

Note) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.

CXP80712B/80716B/80720B/80724B

Conversion time

Sampling time

Reference input voltage

Analog input voltage

CONV

SAMP

REF

IAN

REF

Ta = 25°C
V

= AV

REF

= 5.0V

= AV

= 0V

Operating mode

SLEEP mode
STOP mode
32kHz operating mode

Linearity error

Absolute error

Resolution

REF

current

REF

REFS

µs

REF

1.0

µA

0.6

160/f

ADC

12/f

ADC

0.5

Item

Symbol

Pins

Conditions

Min.

Typ.

Max.

Unit

Bits

(3) A/D converter characteristics

(Ta = 20 to +75°C, V

= AV

= 4.5 to 5.5V, AV

REF

= 4.0 to AV

, Vss = AV

= 0V)

±1

±2

LSB

Analog input

Linearity error

Digital conversion value

Fig. 6. Definitions of A/D converter terms

AN0 to AN11

REF

00 (

= f

/2)

01 (

= f

/4)

11 (

= f

/16)

ADC

= f

ADC

= f

ADC

= f

/16

ADC

= f

ADCCK

PCK1, PCK0

0 (

/2 selection)

1 (

selection)

ADC

= f

ADC

= f

ADC

indicates the below values due to the contents of bit

0 (ADCCK) of the ADC operation clock selection (MSC:

01FF

), bits 7 (PCK1) and 6 (PCK0) of the clock control

CXP80712B/80716B/80720B/80724B

External interruption
High and Low level widths

Reset input Low level width

INT0
INT1
INT2
NMI
PJ0 to PJ7

RST

32/fc

µs

Item

Symbol

Pins

Conditions

Min.

Max.

Unit

RSL

(4) Interruption, reset input

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V)

0.2V

0.8V

INT0

INT1

INT2

NMI

PJ0 to PJ7

(During standby release input)

(Falling edge)

Fig. 7. Interruption input timing

RSL

0.2V

RST

Fig. 8. Reset input timing

(5) Others

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V)

Item

CFG input
High and Low level widths

DFG input
High and Low level widths

DPG minimum pulse width

DPG minimum
removal time

PBCTL input
High and Low level widths

EXI input
High and Low level widths

CFH

CFL

DFH

DFL

DPW

rem

CTH

CTL

EIH

EIL

CFG

DFG

DPG

PBCTL

EXI0
EXI1

Symbol

Pins

Min.

FRC

24 + 200

FRC

8 + 200

FRC

8 + 200 +

sys

FRC

8 + 200 +

sys

Max.

Unit

sys = 2000/fc

Conditions

Note)

sys indicates three values according to the contents of the clock control register (CLC; 00FE

) upper 2

bits (CPU clock selection).

sys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

FRC

[ns] = 1000/fc

CXP80712B/80716B/80720B/80724B

Appendix

Fig. 10. Recommended oscillation circuit

EXTAL

XTAL

(i) (ii)

TEX

Manufacturer

RIVER
ELETEC
CO., LTD.

KINSEKI LTD.

Model

HC-49/U03

HC-49/U (-S)

fc (MHz)

8.00

10.00

12.00

8.00

10.00

12.00

470k

(ii)

32.768kHz

16.00

(pF)

Rd (

)

Circuit

example

(i)

The input circuit format can be selected for PG4/SYNC0 pin and PG5/SYNC1, respectively.

Item

Reset pin pull-up resistor

Input circuit format

Non-existent

C-MOS schmitt

Existent

TTL schmitt

Mask option table

16.00

Content

CXP80712B/80716B/80720B/80724B

Characteristics Curve

(100µA)

0.1

5.0

1.0

Supply voltage [V]

Supply current [mA]

vs. V

(fc = 16MHz, Ta = 25°C, Typical)

0.05

(50µA)

0.01

(10µA)

0.5

10.0

20.0

1/16 dividing mode

1/4 dividing mode

SLEEP mode

32kHz mode
(instruction)

32kHz
SLEEP mode

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode

SLEEP mode

System clock [MHz]

vs. f

= 5V, Ta = 25°C, Typical)

1/2 dividing mode

Supply current [mA]

CXP80712B/80716B/80720B/80724B

Package Outline

Unit: mm

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

EPOXY RESIN

SOLDER PLATING

COPPER / 42 ALLOY

PACKAGE STRUCTURE

23.9 ± 0.4

QFP-100P-L01

DETAIL A

100PIN QFP (PLASTIC)

20.0 0.1

+ 0.4

0° to 15°

0.15 0.05

+ 0.1

15.8 ±

0.4

17.9 ±

0.4

14.0 0.01

+ 0.4

2.75 0.15

+ 0.35

0.65

±0.12

0.15

0.8 ±

0.2

(16.3)

QFP100-P-1420-A

1.4g

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

EPOXY/PHENOL RESIN

SOLDER PLATING

42 ALLOY

PACKAGE STRUCTURE

DETAIL A

LQFP-100P-L01

QFP100-P-1414-A

100PIN LQFP (PLASTIC)

16.0 ± 0.2

14.0 ± 0.1

0.5 ± 0.08

0.18 0.03

+ 0.08

(0.22)

1.5 0.1

+ 0.2

0.127 0.02

+ 0.05

0.5 ±

0.2

(15.0)

0° to 10°

0.1 ± 0.1

0.5 ±

0.2

100

0.1

NOTE: Dimension "

" does not include mold protrusion.

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