Description

The CXP81120/81124 is a CMOS 8-bit micro-

computer which consists of A/D converter, serial

interface, timer/counter, time base timer, PWM

output, as well as basic configurations like 8-bit

CPU, ROM, RAM and I/O port. They are integrated

into a single chip.

Also the CXP81120/81124 provides power-on reset

function, sleep/stop function which enables to lower

power consumption.

Features

· A wide instruction set (213 instructions) which covers various types of data

-- 16-bit operation/multiplication and division/Boolean bit operation instructions

· Minimum instruction cycle

250ns at 16MHz operation (4.5 to 5.5V)

333ns at 12MHz operation (3.0 to 5.5V)

· Incorporated ROM capacity

20K bytes (CXP81120)

24K bytes (CXP81124)

· Incorporated RAM capacity

832 bytes

· Peripheral functions

-- A/D converter

8-bit, 8-channel, successive approximation system

(Conversion time: 20µs at 16MHz)

-- Serial interface

Incorporated buffer RAM (1 to 32 bytes auto transfer), 1 channel

Incorporated 8-bit and 8-stage FIFO

(1 to 8 bytes auto transfer), 1 channel

-- Timer

8-bit timer, 8-bit timer/counter, 19-bit time base timer

-- PWM output

12 bits, 2 channels

· Interruption

10 factors, 10 vectors, multi-interruption possible

· Standby mode

Sleep/stop

· Package

64-pin plastic QFP/LQFP

· Piggyback/evaluator

CXP81100 64-pin ceramic PQFP

Structure

Silicon gate CMOS IC

CXP81120/81124

E94414A69-PS

CMOS 8-bit Single Chip Microcomputer

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

64 pin LQFP (Plastic)

64 pin QFP (Plastic)

CXP81120/81124

Block Diagram

A/D CONVERTER

SERIAL

INTERFACE UNIT

(CH0)

BUFFER

RAM

INTERRUPT CONTROLLER

SPC700

CPU CORE

ROM

20K/24K BYTES

PRESCALER/

TIME BASE TIMER

RAM

832 BYTES

CLOCK

GENERATOR/

SYSTEM CONTROL

SI0

CS0

SI1

SCK0

PC0 to PC7

PD0 to PD7

PA0 to PA7

PE0 to PE1

PE2 to PE3

AN0 to AN7

PB0 to PB7

PORT C

PORT D

PORT G

PORT A

PORT E

PORT B

PORT F

PF0 to PF3

PF4 to PF7

REF

AVss

EXTAL

XTAL

RST

Vss

INT0

INT2

INT1

SERIAL

INTERFACE UNIT

(CH1)

FIFO

8BIT TIMER/COUNTER 0

8BIT TIMER 1

12BIT PWM GENERATOR CH0

12BIT PWM GENERATOR CH1

SO0

SO1

SCK1

PWM0

PWM1

PG3 to PG4

PG5 to PG7

CXP81120/81124

20 21 22 23 24 25 26 27 28 29 30 31 32

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

PG6/SO1

PG7/SI1/INT1

PE0/INT0

PE1/EC/INT2

PE2/PWM0

PE3/PWM1

PF0/AN0

PF1/AN1

PF2/AN2

PF3/AN3

PF4/AN4

PF5/AN5

PF6/AN6

PF7/AN7

REF

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PG3/TO

PG4

PG5/SCK1

PD4

PD3

PD2

PD1

PD0

XTAL

EXTAL

RST

CS0

SI0

SO0

SCK0

PD7

PD6

PD5

Pin Configuration (Top View) 64-pin QFP

Note) 1.

NC (Pin 58) is always connected to V

Vss (Pins 28 and 60) are both connected to GND.

MP (Pin 25) is always connected to GND.

CXP81120/81124

17 18 19 20 21 22 23 24 25 26 27 28 29 30

31 32

PB5

PB4

PB3

PB2

PB1

PB0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

PD7

PD6

PG6/SO1

PG7/SI1/INT1

PE0/INT0

PE1/EC/INT2

PE2/PWM0

PE3/PWM1

PF0/AN0

PF1/AN1

PF2/AN2

PF3/AN3

PF4/AN4

PF5/AN5

PF6/AN6

PF7/AN7

REF

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PG3/TO

PG4

PG5/SCK1

PD5

PD4

PD3

PD2

PD1

PD0

XTAL

EXTAL

RST

CS0

SI0

SO0

SCK0

Pin Configuration (Top View) 64-pin LQFP

Note) 1.

NC (Pin 56) is always connected to V

Vss (Pins 26 and 58) are both connected to GND.

MP (Pin 23) is always connected to GND.

CXP81120/81124

(Port A)
8-bit output port.
(8 pins)

(Port B)
8-bit output port.
(8 pins)

(Port C)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)

(Port D)
8-bit I/O port. I/O and function as standby release input can be set in a unit of
single bits.
(8 pins)

(Port E)
4-bit port. Lower 2 bits
are for input; upper 2 bits
are for output.
(4 pins)

(Port F)
8-bit port. Lower 4 bits are for input; upper
4 bits are for output.
Lower 4 bits also serve as standby release
input.
(8 pins)

Serial clock (CH0) I/O.

Serial data (CH0) output.

Serial data (CH0) input.

Serial interface (CH0) chip select input.

(Port G)
5-bit port. Lower 2 bits
are for output; upper
3 bits are for I/O.
I/O can be set in a unit
of single bits.
(5 pins)

Connects a crystal oscillator for system clock. When supplying the external
clock, input the external clock to EXTAL pin and input opposite phase
clock to XTAL pin.

System reset; active at Low level. RST pin is I/O pin, which outputs "Low"
level by incorporated power-on reset function when power turns on.
(Mask option)

Pin Description

Symbol

PA0 to PA7

PB0 to PB7

PC0 to PC7

PD0 to PD7

PE0/INT0

PE1/EC/INT2

PE2/PWM0

PE3/PWM1

PF0/AN0

PF3/AN3

PF4/AN4

PF7/AN7

SCK0

SO0

SI0

CS0

PG3/TO

PG4

PG5/SCK1

PG6/SO1

PG7/SI1/INT1

EXTAL

XTAL

RST

Output

I/O

Input/Input

Input/Input/
Input

Output/Output

Input/Input

Output/Input

I/O

Output

Input

Output/Output

Output

I/O/I/O

I/O/Output

I/O/Input
Input

Input

Output

I/O

Description

Input to request external interruption.
Active at the falling edge. (2 pins)

External event
input for
timer/counter.

12-bit PWM output. (2 pins)

Analog input to A/D
converter.
(8 pins)

Serial data (CH1)
input.

Timer/counter rectangular wave output.

Serial clock (CH1) I/O.

Serial data (CH1) output.

Input to request external
interruption. Active at the
falling edge.

CXP81120/81124

Port A

Port B

Port C

Port D

Port E

PA0 to PA7
PB0 to PB7

16 pins

Hi-Z

PC0 to PC7

8 pins

Hi-Z

PD0 to PD7

8 pins

Hi-Z

PE1/EC/INT2

1 pin

Hi-Z

PE0/INT0

1 pin

Hi-Z

Circuit format

When reset

Data bus

Output becomes active from high impedance
by data writing to port register.

Ports A, B data

RD (Ports A, B)

Data bus

RD (Port C)

Port C direction

Port C data

Input
protection
circuit

"0" when reset

Standby release

Port D data

Data bus

RD (Port D)

Port D direction

Edge detection

"0" when reset

RD (Port E)

Data bus

Schmitt input

EC/INT2

RD (Port E)

Data bus

Schmitt input

INT0

Input/Output Circuit Formats for Pins

CXP81120/81124

Port E

Port F

Port G

PE2/PWM0
PE3/PWM1

2 pins

Hi-Z

PF0/AN0

PF3/AN3

4 pins

Hi-Z

PF4/AN4

PF7/AN7

4 pins

Hi-Z

PG3/TO

1 pin

High level

Circuit format

When reset

Data bus

RD (Port E)

PWM

Hi-Z control

MPX

Port E data

Port E function selecton

"0" when reset

RD (Port F)

Data bus

input multiplexer

A/D converter

Standby release

Edge detection

Data bus

RD (Port F)

Port F function
selection

Port F data

A/D converter

Input multiplexer

"0" when reset

Timer/counter

MPX

Port G data

Port G function
selection

"0" when reset

"1" when reset

MPX

Port G data

Data bus

RD (Port G)

Port G direction

Port G function
selection

MPX

SCK1 in

SCK1 out, SO1

Serial clock 1/data 1
output enable

"0" when reset

PG6 is not Schmitt input

"0" when reset

CXP81120/81124

Port G

PG4

1 pin

H level

PG5/SCK1
PG6/SO1

2 pins

Hi-Z

PG7/SI1/INT1

1 pin

Hi-Z

CS0
SI0

2 pins

Hi-Z

SO0

1 pin

Hi-Z

Circuit format

When reset

Port G data

"1" when reset

INT1

SI1

Port G data

Data bus

RD (Port G)

Port G direction

Schmitt input

"0" when reset

Schmitt input

CS0
SI0

Serial data 0
output enable

SO0

CXP81120/81124

SCK0

1 pin

Hi-Z

EXTAL
XTAL

2 pins

Oscillation

RST

1 pin

Low level

1 pin

Hi-Z

Circuit format

When reset

Serial clock 0

output enable

SCK0 out

Schmitt input

SCK0 in

EXTAL

XTAL

· Diagram shows the
circuit composition
during oscillation.

· Feedback resistor is
removed during stop.
XTAL becomes "High"
level.

Schmitt input

Pull-up resistor

From power-on reset circuit
(Mask option)

Mask option

Test mode

CXP81120/81124

and V

OUT

should not exceed V

+ 0.3V. (CS0 and SI0 excluded.)

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

be conducted under the recommended operating conditions. Exceeding those conditions may adversely

affect the reliability of the LSI.

Supply voltage

Input voltage

Output voltage

High level output current

High level total output current

Low level output current

Low level total output current

Operating temperature

Storage temperature

Allowable power dissipation

REF

OUT

Topr

Tstg

0.3 to +7.0

to +7.0

0.3 to +0.3

to +7.0

0.3 to +7.0

130

20 to +75

55 to +150

600

380

°C

Total of output pins

QFP-64P-L01

LQFP-64P-L01

Item

Symbol

Rating

Unit

Remarks

Absolute Maximum Ratings

(Vss = 0V reference)

CXP81120/81124

High level
input voltage

Low level
input voltage

Operating temperature

Supply voltage

5.5

+ 0.3

0.3V

0.2V

0.4

+75

°C

Item

Symbol

Min.

Max.

Unit

Remarks

3.0

2.7

2.5

3.0

0.7V

0.8V

0.4

0.3

IHS

IHEX

ILS

ILEX

Topr

Guaranteed operation range for 1/2 and 1/4
frequency dividing mode

Guaranteed operation range for 1/16
frequency dividing mode

Guaranteed data hold range during stop
mode

CMOS Schmitt input

EXTAL pin

CMOS Schmitt input

EXTAL pin

Analog voltage

should be the same voltage as V

Normal input port (PC, PD, PF0 to PF3 and PG6 pins), MP pin.

SCK0, RST, INT0, EC/INT2, SCK1 and SI1/INT1 pins.

CS0 and SI0 pins.

Specified only when the external clock is input.

In case of 3.0 to 3.6V supply voltage (V

In case of 4.5 to 5.5V supply voltage (V

Recommended Operating Conditions

(Vss = 0V reference)

CXP81120/81124

= 4.5V, I

= 0.5mA

= 4.5V, I

= 1.2mA

= 4.5V, I

= 1.8mA

= 4.5V, I

= 3.6mA

= 5.5V, V

= 5.5V

= 5.5V, V

= 0.4V

= 5.5V, V

= 0.4V

High level
output voltage

4.0

3.5

0.5

1.5

µA

PA to PE,
PF4 to PF7,
SO0, SCK0,
RST

only)

PG3 to PG7

EXTAL

RST

Item

Symbol

Condition

Min.

Clock 1MHz
0V other than the measured pins

DD1

DDS1

DDS3

IHE

ILE

ILR

Low level
output voltage

Input current

Typ.

0.4

0.6

400

±10

Max.

Unit

DC Characteristics

Supply voltage (V

= 4.5 to 5.5V)

(Ta = 20 to +75°C, Vss = 0V reference)

RST pin is specified only when the power-on reset circuit is selected with mask option.

For RST pin, specifies the input current when the pull-up resistance is selected, and specifies leakage

current when non-resistance is selected.

When all output pins are open.

= 5V ± 0.5V,

16MHz crystal oscillation
(C

= C

= 15pF)

Sleep mode

= 5V ± 0.5V,

16MHz crystal oscillation
(C

= C

= 15pF)

= 5.5V,

termination of 16MHz oscillation

Supply
current

Input capacity

= 5.5V,

= 0, 5.5V

1/2 frequency dividing mode

Stop mode

I/O leakage
current

PA to PG, MP,
CS0, SI0, SO0,
SCK0, RST

µA

PC, PD,
PE0, PE1,
PF,
PG5 to PG7,
RST, CS0,
SI0, SCK0,
EXTAL

CXP81120/81124

= 3.0V, I

= 0.15mA

= 3.0V, I

= 0.5mA

= 3.0V, I

= 1.2mA

= 3.0V, I

= 1.6mA

= 3.6V, V

= 3.6V

= 3.6V, V

= 0.3V

= 3.6V, V

= 0.3V

High level
output voltage

2.7

2.3

0.3

0.9

µA

EXTAL

RST

Item

Symbol

Condition

Min.

Clock 1MHz
0V other than the measured pins

DD2

DDS2

DDS3

IHE

ILE

ILR

Low level
output voltage

Input current

Typ.

0.3

0.5

200

±10

Max.

Unit

DC Characteristics

Supply voltage (V

= 3.0 to 3.6V)

(Ta = 20 to +75°C, Vss = 0V reference)

RST pin is specified only when the power-on reset circuit is selected with mask option.

For RST pin, specifies the input current when the pull-up resistance is selected, and specifies leakage

current when non-resistance is selected.

When all output pins are open.

= 3.3V ± 0.3V,

12MHz crystal oscillation
(C

= C

= 15pF)

Sleep mode

= 3.3V ± 0.3V,

12MHz crystal oscillation
(C

= C

= 15pF)

= 5.5V,

termination of 12MHz oscillation

Supply
current

Input capacity

= 3.6V,

= 0, 3.6V

1/2 frequency dividing mode

Stop mode

I/O leakage
current

PA to PG, MP,
CS0, SI0, SO0,
SCK0, RST

0.5

2.5

µA

PA to PE,
PF4 to PF7,
SO0, SCK0,
RST

only)

PG3 to PG7

PC, PD,
PE0, PE1,
PF,
PG5 to PG7,
RST, CS0,
SI0, SCK0,
EXTAL

CXP81120/81124

sys indicates three values according to the contents of the clock control register (CLC; 00FE

) upper

2 bits (CPU clock selection).

sys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

EXTAL

0.4V (V

= 4.5 to 5.5V)

0.3V

0.4V (V

= 4.5 to 5.5V)

0.3V

1/fc

Crystal oscillation
Ceramic oscillation

EXTAL

XTAL

External clock

EXTAL

XTAL

74HC04

AC Characteristics

(1) Clock timing

System clock frequency

System clock
input pulse width

System clock input
rise and fall times

Event count input clock
pulse width

Event count input clock
rise and fall times

XTAL
EXTAL

EXTAL

MHz

Item

Symbol

Condition

Unit

Fig. 1,
Fig. 2

Fig. 1,
Fig. 2 (External clock drive)

Fig. 1, Fig. 2
(External clock drive)

Fig. 3

Min.

37.5

sys

Max.

200

(Ta = 20 to +75°C, V

= 3.0 to 5.5V, Vss = 0V reference)

Fig. 1. Clock timing

= 4.5 to 5.5V

Fig. 2. Clock applied condition

0.2V

0.8V

Fig. 3. Event count clock timing

CXP81120/81124

Input mode

Output mode

Input mode

Output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode

Note 1)

sys indicates three values according to the contents of the clock control register (CLC; 00FE

) upper

2 bits (CPU clock selection).

sys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2) CS, SCK, SI and SO represents CS0, SCK0, SI0, and SO0, respectively.

Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.

(2) Serial transfer (CH0)

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Item

SCK

delay time

SCK

floating delay time

delay time

floating delay time

CS
high level width

SCK
cycle time

SCK
high and low level widths

SI input setup time
(for SCK

)

SI input hold time
(for SCK

)

SCK

SO delay time

DCSK

DCSKF

DCSO

DCSOF

WHCS

KCY

SIK

KSI

KSO

SCK0

SO0

CS0

SCK0

SI0

SO0

Symbol

Min.

sys + 200

8000/fc

sys + 100

8000/fc 100

sys + 100

200

sys + 100

100

sys + 200

100

Max.

Unit

Condition

CXP81120/81124

Input mode

Output mode

Input mode

Output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode

Note 1)

sys indicates three values according to the contents of the clock control register (CLC; 00FE

) upper

2 bits (CPU clock selection).

sys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2) CS, SCK, SI and SO represents CS0, SCK0, SI0, and SO0, respectively.

Note 3) The load of SCK output mode and SO output delay time is 50pF.

Serial transfer (CH0)

(Ta = 20 to +75°C, V

= 3.0 to 3.6V, Vss = 0V reference)

Item

SCK

delay time

SCK

floating delay time

delay time

floating delay time

CS
high level width

SCK
cycle time

SCK
high and low level widths

SI input setup time
(for SCK

)

SI input hold time
(for SCK

)

SCK

SO delay time

DCSK

DCSKF

DCSO

DCSOF

WHCS

KCY

SIK

KSI

KSO

SCK0

SO0

CS0

SCK0

SI0

SO0

Symbol

Min.

sys + 250

sys + 200

sys + 250

sys + 200

8000/fc

sys + 100

8000/fc 150

sys + 100

200

sys + 100

100

sys + 250

125

Max.

Unit

Condition

CXP81120/81124

Serial transfer (CH1) (SIO mode)

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Item

Symbol

Min.

Max.

Unit

Condition

SCK1 cycle time

SCK1 high and low
level widths

SI1 input setup time
(for SCK1

)

SI1 input hold time
(for SCK1

)

SCK1

SO1 delay time

KCY

SIK

KSI

KSO

SCK1

SI1

SO1

Input mode

Output mode

Input mode

Output mode

SCK1 input mode

SCK1 output mode

SCK1 input mode

SCK1 output mode

SCK1 input mode

SCK1 output mode

sys + 200

16000/fc

sys + 100

8000/fc 50

100

200

sys + 200

100

sys + 200

100

Note 1)

sys indicates three values according to the contents of the clock control register (CLC; 00FE

) upper

2 bits (CPU clock selection).

sys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.

Serial transfer (CH1) (SIO mode)

(Ta = 20 to +75°C, V

= 3.0 to 3.6V, Vss = 0V reference)

Item

Symbol

Min.

Max.

Unit

Condition

SCK1 cycle time

SCK1 high and low
level widths

SI1 input setup time
(for SCK1

)

SI1 input hold time
(for SCK1

)

SCK1

SO1 delay time

KCY

SIK

KSI

KSO

SCK1

SI1

SO1

Input mode

Output mode

Input mode

Output mode

SCK1 input mode

SCK1 output mode

SCK1 input mode

SCK1 output mode

SCK1 input mode

SCK1 output mode

sys + 200

16000/fc

sys + 100

8000/fc 150

100

200

sys + 200

100

sys + 250

125

Note 1)

sys indicates three values according to the contents of the clock control register (CLC; 00FE

) upper

2 bits (CPU clock selection).

sys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF.

CXP81120/81124

SO1 cycle time

SI1 data setup time

SI1 data hold time

LCY

LSU

LHD

SO1
SI1

SI1

104

µs

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Serial transfer (CH1) (Special mode) (Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

LCY

is specified only when serial mode register (CH1) (SIOM1: 01FA

) lower 2 bits (SO1 clock selection) is

set at 104µs according to the system clock frequency.

Note) The load of SO1 pin is 50pF + 1TTL.

SO1 cycle time

SI1 data setup time

SI1 data hold time

LCY

LSU

LHD

SO1
SI1

SI1

104

µs

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Serial transfer (CH1) (Special mode) (Ta = 20 to +75°C, V

= 3.0 to 3.6V, Vss = 0V reference)

LCY

is specified only when serial mode register (CH1) (SIOM1: 01FA

) lower 2 bits (SO1 clock selection) is

set at 104µs according to the system clock frequency.

Note) The load of SO1 pin is 50pF.

Fig. 6. Serial transfer CH1 timing (Special mode)

SO1

SI1

LCY

Start bit

Output data bit

LCY

0.5V

0.8V

0.2V

LCY/2

LSU

LHD

Input

data bit

CXP81120/81124

Fig. 7. Definitions of A/D converter terms

Conversion time

Sampling time

Reference input voltage

Analog input voltage

CONV

SAMP

REF

IAN

REF

AN0 to AN7

REF

Only for A/D converter
operation
Ta = 25°C
V

= AV

REF

= 5.0V

= AV

= 0V

Operating mode
AV

REF

= 4.0 to 5.5V

= AV

= 4.5 to 5.5V

Sleep mode
Stop mode

Linearity error

Absolute error

Resolution

REF

current

REF

µs

REF

1.0

µA

0.6

160/f

ADC

12/f

ADC

0.5

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Bits

(3) A/D converter characteristics (Ta = 20 to +75°C, V

= AV

= 4.5 to 5.5V, AV

REF

= 4.0 to AV

, Vss = AV

= 0V reference)

±1

±2

LSB

Analog input

Linearity error

Digital conversion value

The value of f

ADC

is as follows by interruption selection/

ADC operation clock selection regeister (MSC: 01FF

)

bit 0 (ADCCK).

When PS2 is selected, f

ADC

= fc/2

When PS1 is selected, f

ADC

= fc

Conversion time

Sampling time

Reference input voltage

Analog input voltage

CONV

SAMP

REF

IAN

REF

AN0 to AN7

REF

Only for A/D converter
operation
Ta=25°C
V

= AV

REF

= 3.3V

= AV

= 0V

Operating mode
AV

REF

= 2.7 to 3.6V

Sleep mode
Stop mode

Linearity error

Absolute error

Resolution

REF

current

REF

µs

REF

0.7

µA

0.4

160/f

ADC

12/f

ADC

0.3

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Bits

(Ta = 20 to +75°C, V

= AV

= 3.0 to 3.6V, AV

REF

= 2.7 to AV

, Vss = AV

= 0V reference)

±1

±2

LSB

A/D converter characteristics

= AV

= 3.0 to 3.6V

CXP81120/81124

External interruption
high and low level widths

Reset input low level width

INT0
INT1
INT2
PJ0 to PJ7

RST

32/fc

µs

Item

Symbol

Condition

Min.

Max.

Unit

RSL

(4) Interruption, reset input

(Ta = 20 to +75°C, V

= 3.0 to 5.5V, Vss = 0V reference)

0.2V

0.8V

INT0

INT1

INT2

PD0 to PD7

(During standby release input)

(Falling edge)

Fig. 8. Interruption input timing

RSL

0.2V

RST

Fig. 9. Reset input timing

Power supply rising time

Power supply cut-off time

OFF

Power-on reset

Repetitive power-on reset

0.05

Item

Symbol Pin

Condition

Min.

Max.

Unit

(5) Power-on reset

(Ta = 20 to +75°C, V

= 3.0 to 5.5V, Vss = 0V reference)

0.2V

3.0V

OFF

The power supply should be turned on smoothly.

Fig. 10. Power-on reset

Specifies only when power-on reset function is selected.

CXP81120/81124

Appendix

Fig. 11. SPC 700 Series recommended oscillation circuit

EXTAL

XTAL

Main clock

Manufacturer

Model

fc (MHz)

(pF)

Rd (

)

Circuit

example

RIVER ELETEC
CO., LTD.

HC-49/U03

KINSEKI LTD.

HC-49/U (-S)

8.00

10.00

12.00

16.00

8.00

10.00

12.00

16.00

22 (15)

(i)

Mask Option Table

Reset pin pull-up resistor

Power-on reset circuit

Non-existent

Item

Content

Existent

CXP81120/81124

0.1

1.0

0.1

1.0

vs. V

(fc = 16MHz, Ta = 25°C, Typical)

vs. V

(fc = 12MHz, Ta = 25°C, Typical)

Supply current [mA]

Supply voltage [V]

fc System clock [MHz]

vs. fc

= 3.3V, Ta = 25°C, Typical)

fc System clock [MHz]

vs. fc

= 5V, Ta = 25°C, Typical)

1/2 dividing mode

1/16 dividing mode

1/4 dividing mode

Sleep mode

1/2 dividing mode

1/16 dividing mode

1/4 dividing mode

Sleep mode

1/2 dividing mode

1/16 dividing mode

1/4 dividing mode

1/2 dividing mode

1/16 dividing mode

1/4 dividing mode

Sleep mode

Supply current [mA]

Sleep mode

Characteristics Curve

CXP81120/81124

Package Outline

Unit: mm

SONY CODE

EIAJ CODE

JEDEC CODE

23.9 ± 0.4

20.0 0.1

0.4 0.1

+ 0.15

14.

0.15 0.05

+ 0.1

2.75 0.15

16.

0.1 0.05

+ 0.2

8 ±

± 0.12

0.15

+ 0.4

17.9 ±

0.4

+ 0.35

64PIN QFP(PLASTIC)

QFP64PL01

QFP064P1420

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN

SOLDER/PALLADIUM

42/COPPER ALLOY

PACKAGE STRUCTURE

PLATING

1.5g

1.0

CXP81120/81124

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN

PLATING

42/COPPER ALLOY

PACKAGE STRUCTURE

12.0 ± 0.2

10.0 ± 0.1

(0.22)

0.18 0.03

+ 0.08

0.5 ± 0.08

0.5 ±

0.2

(11.0)

0.127 0.02

+ 0.05

1.5 0.1

+ 0.2

0.1 ± 0.1

0.5 ±

0.2

0° to 10°

64PIN LQFP (PLASTIC)

LQFP-64P-L01

LQFP064-P-1010

0.3g

DETAIL A

0.1

SOLDER/PALLADIUM

NOTE: Dimension "

" does not include mold protrusion.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXP81124

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXP81124