CMOS 8-bit Single Chip Microcomputer
Description
The CXP826P16 microcomputer is composed of a
CPU, ROM, RAM, and I/O ports. These chips feature
many other high-performance circuits in a single-chip
CMOS design, including an A/D converter, serial
interface, timer/counter, time-base timer, fluorescent
display controller/driver, remote control receiver and
32kHz timer/counter.
This device also includes a power-on reset function
and sleep/stop functions which can be used to
achieve low power consumption.
The CXP826P16 is the PROM-incorporated version of
the CXP82616 with built-in mask ROM, and it is able to
write directly into the program. Thus, it is most suitable
for evaluation use during system development and for
small-quantity production.
Features
Instruction set which supports a wide array of data types
-- 213 types of instructions which include 16-bit calculations, multiplication and division arithmetic, and
boolean bit operations.
Minimum instruction cycle
400ns for 10MHz, 122s for 32kHz operation
On-chip PROM
16K bytes
On-chip RAM
448 bytes (Including fluorescent display data area)
Peripheral functions
-- A/D converter
8-bit, 8-channel, successive approximation system
(conversion rate 32s/10MHz)
-- Serial interface
On-chip 8-bit, 8-stage FIFO (1 to 8 bytes auto transfer),
1 circuit 2-channel
-- Timers
8-bit timer
8-bit timer/counter
19-bit time base timer
32kHz timer/counter
-- Fluorescent display controller/driver
Maximum of 336 segments display available
1 to 16 digits dynamic display
Dimmer function
High voltage tolerance output (40V)
On-chip pull-down resistor (Mask option)
Hardware key scan function (Maximum of 8 x 16 key matrix available)
-- Remote control receiver circuit
On-chip 6-stage FIFO 8-bit pulse measurement counter
Interrupts
13 factors, 13 vectors, multi-interruption possible
Standby mode
Sleep/stop
Package
80-pin plastic QFP
Structure
Silicon gate CMOS IC
1
E94413A79-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXP826P16
80 pin QFP (Plastic)
A
/
D
C
O
N
V
E
R
T
E
R
F
D
P
C
O
N
T
R
O
L
L
E
R
/
D
R
I
V
E
R
R
E
M
O
C
O
N
S
E
R
I
A
L
I
N
T
E
R
F
A
C
E
U
N
I
T
8
B
I
T
T
I
M
E
R
/
C
O
U
N
T
E
R
0
F
I
F
O
F
I
F
O
IN
TE
RR
UP
T C
ON
TR
OL
LE
R
S
P
C
7
0
0
C
P
U
C
O
R
E
P
R
O
M
1
6
K
B
Y
T
E
S
P
R
E
S
C
A
L
E
R
/
T
I
M
E
B
A
S
E
T
I
M
E
R
3
2
k
H
z
T
I
M
E
R
/
C
O
U
N
T
E
R
R
A
M
4
4
8
B
Y
T
E
S
8
P
A
0
/
A
N
0
t
o
P
A
7
/
A
N
7
T
0
t
o
T
7
P
E
4
/
R
M
C
P
B
1
/
C
S
0
P
B
3
/
S
I
0
P
B
4
/
S
O
0
P
B
2
/
S
C
K
0
P
B
6
/
S
I
1
P
B
7
/
S
O
1
P
B
5
/
S
C
K
1
P
E
0
/
E
C
PE
0/I
NT
0
PE
1/I
NT
1
PE
2/I
NT
2
PE
3/I
NT
3
PO
RT
C
8
P
C
0
t
o
P
C
7
PO
RT
F
8
P
F
0
t
o
P
F
7
PO
RT
B
8
P
B
0
t
o
P
B
7
PO
RT
E
6
2
P
E
0
t
o
P
E
5
P
E
6
t
o
P
E
7
8
8
2
1
T
8
/
S
2
8
t
o
T
1
5
/
S
2
1
S
0
t
o
S
2
0
V
F
D
P
8
B
I
T
T
I
M
E
R
1
R
A
M
8
0
B
Y
T
E
S
PO
RT
A
8
P
A
0
t
o
P
A
7
P
B
0
/
C
S
1
2
P
E
7
/
A
D
J
P
E
7
/
T
O
2
PE
3/N
MI
2
8
P
D
0
t
o
P
D
7
PO
RT
D
2
P
H
0
t
o
P
H
1
PO
RT
H
2
P
H
2
t
o
P
H
3
PH
2/T
EX
PH
3/T
X
EX
TA
L
XT
AL
V
DD
Vs
s
RS
T
Vp
p
C
L
O
C
K
G
E
N
.
/
S
Y
S
T
E
M
C
O
N
T
R
O
L
2
CXP826P16
Block Diagram
PE3/INT3/NMI
PE4/RMC
PE5
PE6
PE7/TO/ADJ
PB0/CS1
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
PC0/KR0
PC1/KR1
PC2/KR2
PC3/KR3
PC4/KR4
PC5/KR5
PC6/KR6
PC7/KR7
PA0/AN0
PA1/AN1
PA2/AN2
T6
T7
T8/S28
T9/S27
T10/S26
T11/S25
T12/S24
T13/S23
T14/S22
T15/S21
S20
S19
S18
S17
S16
PF7/S15
PF6/S14
PF5/S13
PF4/S12
PF3/S11
PF2/S10
PF1/S9
PF0/S8
PD7/S7
P
A
3
/
A
N
3
P
A
4
/
A
N
4
P
A
5
/
A
N
5
P
A
6
/
A
N
6
P
A
7
/
A
N
7
R
S
T
E
X
T
A
L
X
T
A
L
V
s
s
P
D
0
/
S
0
P
D
1
/
S
1
P
D
2
/
S
2
P
D
3
/
S
3
P
D
4
/
S
4
P
D
5
/
S
5
P
D
6
/
S
6
P
E
2
/
I
N
T
2
P
E
1
/
I
N
T
1
P
E
0
/
E
C
/
I
N
T
0
P
H
0
P
H
1
V
p
p
P
H
2
/
T
E
X
P
H
3
/
T
X
V
D
D
V
F
D
P
T
0
T
1
T
2
T
3
T
4
T
5
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 26 27 28 29 30
40
39
38
37
36
35
34
31 32 33
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
70 69 68 67
63
64
65
66
61
62
71
72
73
74
75
76
77
78
79
80
1
3
CXP826P16
Pin Assignment (Top View)
Note) 1. Vpp (Pin 75) is always connected to V
DD
.
2. PH3/TX (Pin 73) is input port during port selection;
oscillation output during oscillation selection
4
CXP826P16
Pin Description
Symbol
I/O
Functions
I/O/Analog input
PA0/AN0
to
PA7/AN7
(Port A)
8-bit I/O port. I/O can
be set in a bit unit.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)
Analog inputs to A/D converter.
(8 pins)
I/O/Input
PC0/KR0
to
PC7/KR7
PE0/INT0/
EC0
PE1/INT1
PE2/INT2
PE3/INT3/
NMI
PE4/RMC
PE5
PE6
PE7/TO/
ADJ
Input/Input/
Input
Input/Input
Input/Input
Input/Input/
Input
Input/Input
Input
Input
Output/Output
(Port C)
8-bit I/O port. I/O can
be set in a bit unit.
Capable of driving
12mA sync current.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)
(Port E)
8-bit port.
Upper 6 bits are for
inputs; lower 2 bits are
for outputs.
(8 pins)
Key return input for FDP segment signal which
performs key scanning.
External event input to
timer/counter. (1 pin)
External interrupt
request inputs.
(4 pins)
Non-maskable interruption request input.
Input for remote control receiver circuit.
Output for timer/counter rectangular waveform
and 32kHz oscillation frequency division.
I/O/Input
I/O/Input
I/O/I/O
I/O/Input
I/O/Output
I/O/I/O
I/O/Input
I/O/Output
PB0/CS1
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
(Port B)
8-bit I/O port. I/O can
be set in a bit unit.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)
Chip select input for serial interface (CH1).
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).
5
CXP826P16
Symbol
I/O
Functions
I/O
PH0 to PH1
(Port H)
2-bit I/O port. I/O can be set in a bit unit. Incorporation of pull-up resistor
can be set through the software in a unit of 2 bits.
(2 pins)
Output/Output
T8/S28
to
T15/S21
Output for FDP timing and segment signals.
Output/Output
PF0/S8
to
PF7/S15
(Port F)
8-bit output port.
(8 pins)
Output
S16 to S20
Segment signal output for FDP.
Output
T0 to T7
Timing signal output for FDP.
Output/Output
PD0/S0
to
PD7/S7
Input
Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
input to XTAL.
EXTAL
Provides voltage for FDP when on-chip resistor is selected under mask option.
V
FDP
Output
XTAL
Input/Input
Crystal connectors for 32kHz timer/counter clock
oscillation circuit. Connect a 32kHz crystal oscillator
between TEX and TX. For usage as event input, connect
clock oscillation source to TEX, and leave TX open.
PH2/TEX
Input/Output
PH3/TX
Input
Low-level active. System reset. RST is input pin.
RST
Positive power supply pin for writing of built-in PROM.
Under normal operating conditions, connect to V
DD
.
Vpp
Vcc supply.
V
DD
GND
Vss
(Port D)
8-bit output port.
(8 pins)
(Port H)
2-bit input
port.
(2 pins)
Segment signal output for FDP.
Segment signal output for FDP.
6
CXP826P16
Port B
Data bus
RD (Port B)
Port B direction
IP
Port B data
"0" when reset
"0" when reset
Schmitt input
CS0
CS1
SI0
SI1
Pull-up transistors
approx. 100k
Pull-up resistor
SI0 and SI1 are not schmitt input.
8 pins
Hi-Z
Hi-Z
When reset
PA0/AN0
to
PA7/AN7
PB0/CS1
PB1/CS0
PB3/SI0
PB6/SI1
Port B
Data bus
RD (Port B)
IP
Port B output
selection
"0" when reset
Schmitt input
SCK in
Port B data
Port B direction
"0" when reset
"0" when reset
SCK OUT
Output enable
Pull-up transistors
approx. 100k
Pull-up resistor
4 pins
2 pins
Hi-Z
PB2/SCK0
PB5/SCK1
Data bus
RD (Port A)
Port A direction
IP
Port A data
Pull-up resistor
Port A input
selection
Input protection
circuit
"0" when reset
"0" when reset
"0" when reset
Input multiplexer
A/D converter
Pull-up transistors
approx. 100k
I/O Circuit Format for Pins
Port A
Pin
Circuit format
7
CXP826P16
2 pins
Hi-Z
Hi-Z
Pin
When reset
Circuit format
PB4/SO0
PB7/SO1
PC0/KR0
to
PC7/KR7
8 pins
5 pins
1 pin
Hi-Z
High level
Hi-Z
PE0/EC/INT0
PE1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
IP
Schmitt input
RD (Port E)
Data bus
EC/INT0
INT1
INT2
INT3/NMI
RMC
Data bus
RD (Port C)
Port C direction
IP
Port C data
"0" when reset
"0" when reset
2
1
2
Pull-up transistors approx. 100k
1
Large current drive of 12mA possible
Pull-up resistor
Key input signal
Data bus
RD (Port B)
IP
Port B output
selection
"0" when reset
Port B data
Port B direction
"0" when reset
SO
Output enable
Pull-up transistors
approx. 100k
Pull-up resistor
"0" when reset
Port E
PE5
1 pin
PE6
IP
RD (Port E)
Data bus
Port E
Data bus
RD (Port E)
*
Port E data
"1" when reset
Port E
Port C
Port B
8
CXP826P16
1 pin
PE7/TO/ADJ
Data bus
Port E output
selection
"0" when reset
Port E data
"1" when reset
RD (Port E)
ADJ signals are frequency division
outputs for 32kHz oscillation frequency
adjustment. ADJ2K provides usage as
buzzer output.
Port E output
selection
"00" when reset
Port E output
selection
Output enable
TO
ADJ16K
ADJ2K
MPX
Port E
2 pins
Hi-Z
PH0 to PH1
Data bus
RD
IP
Port data
"0" when reset
Port direction
"0" when reset
Pull-up transistors
approx. 100k
Pull-up resistor
Port H
16 pins
Hi-Z or
Low level
(When PD
resistor is
connected)
PD0/S0
to
PD7/S7
PF0/S8
to
PF7/S15
Data bus
RD (Port D or Port F)
Port D data or
Port F data
("0" when reset)
Segment output data
Output selection control signal
OP
Mask option
Pull-down
resistor
V
FDP
High voltage tolerance transistor
Port D
Port F
High level
High level with
150k
resistor
when reset
(
)
When reset
Pin
Circuit format
9
CXP826P16
21 pins
Hi-Z or
Low level
(When PD
resistor is
connected)
S16 to S20
T15/S21
to
T8/S28
T0 to T7
Segment output data
Output selection control signal
("0" when reset)
OP
Mask option
Pull-down
resistor
V
FDP
High voltage tolerance transistor
2 pins
Oscillation
EXTAL
XTAL
IP
EXTAL
XTAL
Diagram shows circuit
construction for oscillation.
During STOP feedback
resistor is disconnected,
and XTAL becomes "H"
level.
IP
2 pins
Oscillation
halted
port input
PH2/TEX
PH3/TX
IP
PH2/TEX
PH3/TX
IP
32kHz oscillation
circuit control
"1" when reset
Data
bus
RD
Data
bus
RD
Clock
input
1 pin
Low level
RST
Schmitt input
Pull-up resistor
Mask option
OP
IP
When reset
Pin
Circuit format
10
CXP826P16
1
V
IN
and V
OUT
must not exceed V
DD
+ 0.3V.
2
Specifies output current of general-purpose I/O ports.
3
The large current drive transistor is an N-ch transistor of Port C (PC).
Note) If the absolute maximum ratings are exceeded, the LSI could reach permanent breakdown. Also,
observing recommended operating conditions is desirable; otherwise, the LSI's reliability could be
affected.
Supply voltage
Input voltage
Output voltage
V
DD
Vpp
V
IN
V
OUT
V
OD
I
OH
I
ODH1
I
ODH2
I
OH
I
ODH
I
OL
I
OLC
I
OL
Topr
Tstg
P
D
V
DD
40 to V
DD
+ 0.3
5
15
35
40
100
15
20
100
10 to +75
55 to +150
600
Display output voltage
High level output current
High level
total output current
Low level output current
Low level total output current
Operating temperature
Storage temperature
Allowable power dissipation
0.3 to +7.0
0.3 to +13.0
0.3 to +7.0
1
0.3 to +7.0
1
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
C
C
mW
Other than display output pins
2
: per pin
Display output S0 to S20: per pin
Display output T0 to T7
,
T8/S28 to T15/S21: per pin
Total of other than display output pins
Total of display output pins
Port 1 pin
Large current port pin
3
Entire pin toral
As P channel transistor is open drain,
V
DD
voltage is determined as standard.
Item
Symbol
Rating
Unit
Remarks
Absolute Maximum Ratings
(Vss = 0V)
Incorporated PROM
11
CXP826P16
High level
input voltage
Low level
input voltage
Operating temperature
Supply voltage
5.5
5.5
5.5
5.5
V
DD
V
DD
V
DD
+ 0.3
0.3V
DD
0.2V
DD
0.4
+75
V
V
V
V
V
V
V
V
V
V
V
C
Item
Symbol
Min.
Max.
Unit
Remarks
4.5
3.5
2.7
2.5
0.7V
DD
0.8V
DD
V
DD
0.4
0
0
0.3
10
V
IH
V
IHS
V
IHEX
V
IL
V
ILS
V
ILEX
Topr
High speed mode (1/2, 1/4 clock)
guaranteed operation range
Low speed mode (1/16 clock)
guaranteed operation range
Guaranteed operation range with TEX clock
Guaranteed data hold operation range
during STOP
4
1
Hysteresis input
2
EXTAL pin
3
1
Hysteresis input
2
EXTAL pin
3
V
DD
1
All regular input port (PA, PB3, PB4, PB6, PB7, PC, PE5, PH).
2
For pins RST, CS0, CS1, SCK0, SCK1, EC/INT0, INT1, INT2, INT3/NMI, RMC.
3
Specifies only for external clock input.
4
Vpp should be the same voltage as V
DD
.
Recommended Operating Conditions
(Vss = 0V)
Vpp
Vpp = V
DD
12
CXP826P16
V
DD
= 4.5V, I
OH
= 0.5mA
V
DD
= 4.5V, I
OH
= 1.2mA
V
DD
= 4.5V, I
OL
= 1.8mA
V
DD
= 4.5V, I
OL
= 3.6mA
V
DD
= 4.5V, I
OL
= 12.0mA
V
DD
= 5.5V, V
IH
= 5.5V
V
DD
= 5.5V, V
IL
= 0.4V
V
DD
= 5.5V, V
IL
= 5.5V
V
DD
= 5.5V, V
IL
= 0.4V
V
DD
= 5.5V, V
IL
= 0.4V
V
DD
= 4.5V, V
IL
= 4.0V
V
DD
= 4.5V
V
OH
= V
DD
2.5V
V
DD
= 5.5V
V
OL
= V
DD
35V
V
FDP
= V
DD
35V
V
DD
= 5V
V
OD
V
FDP
= 30V
V
DD
= 5.5V
V
I
= 0, 5.5V
High level
output voltage
Display
output current
Open drain
output leak
current (P-CH
Tr off state)
Pull down
resistor
3
Input/Output
leak current
4.0
3.5
0.5
0.5
0.1
0.1
1.5
3.3
8
20
60
V
V
V
V
V
A
A
A
A
A
A
A
mA
mA
A
k
A
PC
PA, PB,
PC, PE6,
PE7, PH0,
PH1
EXTAL
TEX
RST
1
PA to PC
2
PH0
2
, PH1
2
Item
Symbol
Pin
Condition
Min.
PA to PC
2
,
PH0
2
, PH1
2
,
RST
2
S0 to S20
S21/T15 to
S28/T8
T0 to T7
I
IZ
I
IL
I
OH
I
LOL
R
L
V
OH
V
OL
I
IHE
I
ILE
I
IHT
I
ILT
I
ILR
Low level
output voltage
Input current
100
Typ.
0.4
0.6
1.5
40
40
10
10
400
50
20
270
10
Max.
Unit
DC Characteristics
Electrical Characteristics
(Ta = 10 to +75C, Vss = 0V)
S0 to S20
S21/T15 to
S28/T8
T0 to T7
S21/T15 to
S28/T8
T0 to T7
S0 to S20
13
CXP826P16
Supply
current
4
Item
Symbol
Pin
Codition
Min.
20
400
9
1000
30
A
A
40
mA
mA
A
1.2
8
30
For pins
other than
S0 to S28,
T0 to T7,
PE6, PE7,
V
DD
, Vss,
V
FDP
1MHz clock
0V other than the measured pins
V
DD
= 5.5V, 10MHz crystal oscillation
(C
1
= C
2
= 15pF)
V
DD
= 3V, 32kHz crystal oscillation
(C
1
= C
2
= 47pF)
High-speed mode operation
(1/2 frequency divider clock)
V
DD
I
DD1
I
DD2
I
DDS1
I
DDS2
I
DDS3
C
IN
Typ.
Max.
Unit
1
RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor
has been selected.
2
Pins PA to PC, PH0, and PH1 specifies the input current when pull-up resistor has been selected; leakage
current when no resistor has been selected.
3
Applies when the on-chip pull-down resistor is selected under the mask option.
4
All output pins are left open.
V
DD
= 5.5V, 10MHz crystal oscillation
(C
1
= C
2
= 15pF)
V
DD
= 3V, 32kHz crystal oscillation
(C
1
= C
2
= 47pF)
Sleep mode
Stop mode, V
DD
= 5.5V,
Termination of 10MHz and 32kHz
crystal oscillation.
Input
capacitance
pF
20
10
14
CXP826P16
t
sys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control registor (address: 00FE
H
).
t
sys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
EXTAL
t
XH
t
XL
t
CF
t
CR
0.4V
V
DD
0.4V
1/fc
Crystal oscillation
Ceramic oscillation
EXTAL
XTAL
External clock
EXTAL
XTAL
74HC04
C
1
C
2
32kHz clock applied condition
Crystal oscillation
TEX
TX
C
1
C
2
AC Characteristics
(1) Clock timing
System clock frequency
System clock input pulse width
System clock input
rise and fall time
Event count input clock
pulse width
Event count input clock
rise and fall time
System clock frequency
Event count input clock
input pulse width
Event count input clock
rise and fall time
f
C
t
XL
,
t
XH
t
CR
,
t
CF
t
EH
,
t
EL
t
ER
,
t
EF
f
C
t
TL
,
t
TH
t
TR
,
t
TF
XTAL
EXTAL
EXTAL
EXTAL
EC
EC
TEX
TX
TEX
TEX
MHz
ns
ns
ns
ms
kHz
s
ms
Item
Symbol
Pins
Conditions
Min.
Unit
Fig. 1, Fig. 2
Fig. 1, Fig. 2
External clock drive
Fig. 1, Fig. 2
External clock drive
Fig. 3
Fig. 3
V
DD
= 2.7 to 5.5V
Fig. 2 (32kHz clock
application condition)
Fig. 3
Fig. 3
1
37.5
t
sys + 50
10
Typ.
32.768
Max.
10
200
20
20
(Ta = 10 to +75C, V
DD
= 4.5 to 5.5V, Vss = 0V)
Fig. 2. Clock applied conditions
Fig. 1. Clock timing
TEX
EC
t
EH
t
EL
t
EF
t
ER
0.2V
DD
0.8V
DD
t
TH
t
TL
t
TF
t
TR
Fig. 3. Event count clock timing
15
CXP826P16
(2) Serial transfer
(Ta = 10 to +75C, V
DD
= 4.5 to 5.5V, Vss = 0V)
Item
CS0
SCK0 (CS1
SCK1)
delay time
CS0
SCK0 (CS1
SCK1)
float delay time
CS0
SO0 (CS1
SO1)
delay time
CS0
SO0 (CS1
SO1)
float delay time
CS0 (CS1) high level width
SCK0 (SCK1) cycle time
SCK0 (SCK1)
high and low level widths
SI0 (SI1) input setup time
(for SCK0
(SCK1
) )
SI0 (SI1) input hold time
(for SCK0
(SCK1
) )
SCK0
SO0 (SCK1
SO1)
delay time
t
DCSK
t
DCSKF
t
DCSO
t
DCSOF
t
WHCS
t
KCY
t
KH
t
KL
t
SIK
t
KSI
t
KSO
SCK0
(SCK1)
SCK0
(SCK1)
SO0
(SO1)
SO0
(SO1)
CS0
(CS1)
SCK0
(SCK1)
SCK0
(SCK1)
SI0
(SI1)
SI0
(SI1)
SO0
(SO1)
Input mode
Output mode
Input mode
Output mode
SCK0 (SCK1) input mode
SCK0 (SCK1) output mode
SCK0 (SCK1) input mode
SCK0 (SCK1) output mode
SCK0 (SCK1) input mode
SCK0 (SCK1) output mode
ns
ns
ns
ns
ns
Symbol
Pin
Min.
t
sys + 200
t
sys + 200
t
sys + 200
t
sys + 200
t
sys + 200
2
t
sys + 200
16000/fc
t
sys + 100
8000/fc 50
100
200
t
sys + 200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
sys + 200
100
Max.
Unit
Chip select transfer mode
(SCK0 (SCK1) = output mode)
Chip select transfer mode
(SCK0 (SCK1) = output mode)
Chip select transfer mode
Chip select transfer mode
Chip select transfer mode
Condition
Note 1)
t
sys indicates the three values below according to the upper two bits (CPU clock selection) of the
control clock registor (address: 00FE
H
).
t
sys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits =
"11")
Note 2) The load condition for the SCK0 (SCK1) output mode, SO0 (SO1) output delay time is 50pF + 1TTL.
16
CXP826P16
Fig. 4. Serial transfer CH0 timing
CS0
(CS1)
SCK0
(SCK1)
0.2V
DD
0.8V
DD
t
WHCS
t
DCSK
t
DCSKF
0.8V
DD
0.2V
DD
0.8V
DD
t
KCY
t
KL
t
KH
0.8V
DD
0.2V
DD
SI0
(SI1)
t
SIK
t
KSI
Input
data
t
DCSO
t
KSO
t
DCSOF
Output data
0.8V
DD
0.2V
DD
SO0
(SO1)
17
CXP826P16
t
CONV
t
SAMP
V
IAN
V
ZT
1
V
FT
2
Ta = 25C
V
DD
= 5.0V
V
SS
= 0V
s
s
V
V
DD
+ 0.3
AN0 to AN7
160/f
ADC
3
12/f
ADC
3
0.3
Item
Symbol
Pin
Condition
Min.
Typ.
Max.
Unit
Bits
(3) A/D converter characteristics
(Ta = 10 to +75C, V
DD
= 4.5 to 5.5V, Vss = 0V)
8
3
LSB
70
mV
5030
10
4970
10
4910
mV
Analog input
Linearity error
V
FT
V
ZT
00
H
01
H
FE
H
FF
H
D
i
g
i
t
a
l
c
o
n
v
e
r
s
i
o
n
v
a
l
u
e
1
V
ZT :
Value at which the digital conversion value changes
from 00
H
to 01
H
and vice versa.
2
V
FT :
Value at which the digital conversion value changes
from FE
H
to FF
H
and vice versa.
3
f
ADC
indicates the below values due to the Bit6 (CKS) of
A/D control register (address: 00F9
H
) and the Bit7 (PCK1)
and Bit6 (PCK0) of clock control register (address: 00FE
H
)
00 (
= f
EX
/2)
01 (
= f
EX
/4)
11 (
= f
EX
/16)
f
ADC
= f
C
/2
f
ADC
= f
C
/4
f
ADC
= f
C
/16
f
ADC
= f
C
CKS
PCK1, 0
0 (
/2 selection)
1 (
selection)
f
ADC
= f
C
/2
f
ADC
= f
C
/8
Conversion time
Sampling time
Analog input voltage
Linearity error
Zero transition
voltage
Full-scale transition
voltage
Resolution
Fig. 5. Definition of A/D converter terms
18
CXP826P16
External interruption
high and low level widths
Reset input low level width
INT0
INT1
INT2
INT3
NMI
RST
1
32/fc
s
s
Item
Symbol
Pin
Condition
Min.
Max.
Unit
t
IH
t
IL
t
RSL
(4) Interruption, reset input
(Ta = 10 to +75C, V
DD
= 4.5 to 5.5V, Vss = 0V)
0.2V
DD
0.8V
DD
t
IH
t
IL
INT0
INT1
INT2
INT3
NMI
(NMI specifies only for
the falling edge)
t
IL
t
IH
Fig 6. Interruption input timing
t
RSL
0.2V
DD
RST
Fig. 7. RST input timing
19
CXP826P16
Appendix
Fig. 8. Recommended oscillation circuit
C
1
EXTAL
XTAL
C
2
Rd
EXTAL
XTAL
Rd
(i) Main clock
EXTAL
XTAL
C
1
C
2
Rd
XTAL
(ii) Main clock
EXTAL
XTAL
C
1
C
2
Rd
TEX
TX
(iii) Sub clock
Manufacturer
MURATA
MFG
CO., LTD.
RIVER
ELETEC
CORPORATION
KINSEKI
LTD.
Model
CSA4.19MG
CSA8.00MTZ
CST4.19MGW
CST8.00MTW
HC-49/U03
HC-49/U (-S)
P3
fc (MHz)
4.19
8.00
10.00
4.19
8.00
10.00
4.19
8.00
10.00
4.19
8.00
10.00
20
20
50
22
1M
(iii)
32.768kHz
30
12
27
30
12
27
0
0
0
C
1
(pF)
C
2
(pF)
Rd (
)
Circuit
example
(i)
CSA10.0MTZ
(ii)
CST10.0MTW
(i)
Those marked with an asterisk (
) signify types with built-in ground capacitance (C
1
, C
2
).
Option Item
Mask Product
Package
ROM capacitance
Reset pin pull-up resistor
High voltage drive output pin
pull-down resistor
80-pin plastic QFP
12Kbyte/16Kbyte
Existent/Non-Existent
Existent/Non-Existent
80-pin plastic QFP
PROM 16Kbyte
Existent
Non-Existent (PD0/S0 to PF7/S15)
Existent (T0 to S16)
Selection Guide
CXP826P16Q-1-
20
CXP826P16
0
15
10
5
5
10
15
20
(100A)
3
4
5
6
0.1
5.0
1.0
7
2
0.05
(50A)
0.01
(10A)
0.5
10.0
20.0
V
DD
Supply voltage [V]
I
D
D
S
u
p
p
l
y
c
u
r
r
e
n
t
[
m
A
]
I
DD
vs. V
DD
(fc = 10MHz, Ta = 25C, Typical)
fc System clock [MHz]
I
D
D
S
u
p
p
l
y
c
u
r
r
e
n
t
[
m
A
]
I
DD
vs. fc
(V
DD
= 5V, Ta = 25C, Typical)
32kHz
Sleep mode
Sleep mode
32kHz mode
(instruction)
1/16 dividing mode
1/2 dividing mode
1/16 dividing mode
sleep mode
1/2 dividing mode
0
Charactreistics Curves
21
CXP826P16
Package Outline
Unit : mm
PACKAGE STRUCTURE
SONY CODE
EIAJ CODE
JEDEC CODE
QFP-80P-L01
QFP080-P-1420
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
42/COPPER ALLOY
1.6g
23.9 0.4
20.0 0.1
+ 0.4
1
80
65
64
41
40
25
24
0.8
0.35 0.1
+ 0.15
1
4
.
0
0
.
1
+
0
.
4
1
7
.
9
0
.
4
1
6
.
3
0.1 0.05
+ 0.2
2.75 0.15
+ 0.35
0
.
8
0
.
2
0.15 0.05
+ 0.1
80PIN QFP (PLASTIC)
M
0.2
0.15
0 to 10
DETAIL A
A
PDF 
ZIP