Description

The CXP82712/82716 microcomputer is composed

of a 8-bit CPU, ROM, RAM, and I/O ports. These

chips feature many other high-performance circuits

in a single-chip CMOS design, including an A/D

converter, serial interface, timer/counter, time base

timer, fluorescent display controller/driver, remote

control receiver, PWM output circuit and 32kHz

timer/counter.

This device also includes sleep/stop functions which

can be used to achieve low power consumption.

Features

· Instruction set which supports a wide array of data types

-- 213 types of instructions which include 16-bit calculations, multiplication and division arithmetic, and

boolean bit operations.

· Minimum instruction cycle

400ns for 10MHz, 122µs for 32kHz operation

· On-chip ROM

12K bytes (CXP82712)

16K bytes (CXP82716)

· On-chip RAM

448 bytes (Including fluorescent display data area)

· Peripheral functions

-- A/D converter

8-bit, 8-channel, successive approximation system

(conversion rate 32µs/10MHz)

-- Serial interface

On-chip 8-bit, 8-stage FIFO (1 to 8 bytes auto transfer),

1 circuit 2-channel

-- Timers

8-bit timer

8-bit timer/counter

19-bit time base timer

32kHz timer/counter

-- Fluorescent display controller/driver

24 high voltage tolerance output ports

Maximum of 144 segments display available

1 to 16 digits dynamic display

Dimmer function

High voltage tolerance output (40V)

On-chip pull-down resistor (Mask option)

Hardware key scan function (Maximum of 8

8 key matrix available)

-- Remote control receiver circuit

On-chip 6-stage FIFO 8-bit pulse measurement counter

-- PWM output

8-bit, 1-channel

· Interruption

13 factors, 13 vectors, multi-interruption possible

· Standby mode

Sleep/stop

· Package

64-pin plastic SDIP

· Piggyback/evaluator

CXP82700 64-pin ceramic SDIP

CMOS 8-bit Single Chip Microcomputer

E93Y23B16-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXP82712/82716

64 pin SDIP (Plastic)

Structure

Silicon gate CMOS IC

CXP82712/82716

A/D CONVERTER

FDP

CONTROLLER/

DRIVER

REMOCON

SERIAL

INTERFACE

UNIT

8 BIT TIMER/COUNTER 0

FIFO

INTERRUPT CONTROLLER

SPC700

CPU CORE

ROM

12K/16K BYTES

PRESCALER/

TIME BASE TIMER

32kHz

TIMER/COUNTER

RAM

448 BYTES

CLOCK GEN./

SYSTEM CONTROL

PA0/AN0

PA7/AN7

T0 to T7

PE4/RMC

PB1/CS0

PB3/SI0

PB4/SO0

PB2/SCK0

PB6/SI1

PB7/SO1

PB5/SCK1

PE0/EC

PE0/INT0

PE1/INT1

PE2/INT2

PE3/INT3

PH1/TEX

PH0/TX

EXTAL

XTAL

RST

Vss

PORT C

PC0 to PC7

PORT F

PF5 to PF7

PORT B

PB0 to PB7

PORT E

PE0 to PE4

PE5 to PE6

T8/S28

T15/S21

S13 to S20

FDP

8 BIT TIMER 1

RAM

80 BYTES

PORT A

PA0 to PA7

PB0/CS1

PE6/ADJ

PE6/TO

PE3/NMI

PORT H

PH0 to PH1

8 BIT PWM

PE5/PWM

Block Diagram

CXP82712/82716

Pin Assignment (Top View)

PH0/TX

PH1/TEX

PE6/ADJ/TO

PB0/CS1

PB1/CS0

PB2/SCK0

PB3/SI0

PB4/SO0

PB5/SCK1

PB6/SI1

PB7/SO1

PC0/KR0

PC1/KR1

PC2/KR2

PC3/KR3

PC4/KR4

PC5/KR5

PC6/KR6

PC7/KR7

PA0/AN0

PA1/AN1

PA2/AN2

PA3/AN3

PA4/AN4

PA5/AN5

PA6/AN6

PA7/AN7

RST

EXTAL

XTAL

Vss

PE5/PWM

PE4/RMC

PE3/INT3/NMI

PE2/INT2

PE1/INT1

PE0/EC/INT0

FDP

T8/S28

T9/S27

T10/S26

T11/S25

T12/S24

T13/S23

T14/S22

T15/S21

S20

S19

S18

S17

S16

PF7/S15

PF6/S14

PF5/S13

Note) 1. NC (Pin 3) is always connected to V

2. PH0/TX (Pin 1) is input port during port selection;

oscillation output during oscillation selection

CXP82712/82716

Pin Description

Symbol

I/O

Functions

I/O/Analog Input

PA0/AN0

PA7/AN7

(Port A)
8-bit I/O port. I/O can
be set in a bit unit.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)

Analog inputs to A/D converter.
(8 pins)

I/O/Input

PC0/KR0

PC7/KR7

PE0/INT0/
EC0

PE1/INT1

PE2/INT2

PE3/INT3/
NMI

PE4/RMC

PE5/PWM

PE6/ADJ/TO

Input/Input/
Input

Input/Input

Input/Input/
Input

Input/Input

Output/Output

Output

(Port C)
8-bit I/O port. I/O can
be set in a bit unit.
Capable of driving
12mA sink current.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)

(Port E)
Lower 5 bits are for
inputs; upper 2 bits are
for outputs.
(7 pins)

Key return input for FDP segment signal which
performs key scanning.

External event input to
timer/counter. (1 pin)

External interrupt
requests.
(4 pins)

Non-maskable interruption request input.

Input for remote control receiver circuit.

8-bit PWM output.

Output for timer/counter rectangular waveform
and 32kHz oscillation frequency division.

I/O/Input

I/O/I/O

I/O/Input

I/O/Output

I/O/I/O

I/O/Input

I/O/Output

PB0/CS1

PB1/CS0

PB2/SCK0

PB3/SI0

PB4/SO0

PB5/SCK1

PB6/SI1

PB7/SO1

(Port B)
8-bit I/O port. I/O can
be set in a bit unit.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)

Chip select input for serial interface (CH1).

Chip select input for serial interface (CH0).

Serial clock I/O (CH0).

Serial data input (CH0).

Serial data output (CH0).

Serial clock I/O (CH1).

Serial data input (CH1).

Serial data output (CH1).

CXP82712/82716

Symbol

I/O

Functions

Output/Output

T8/S28

T15/S21

Dual purpose output for FDP timing and segment signals.

Output/Output

PF5/S13

PF7/S15

(Port F)
3-bit output port.
(3 pins)

Output

S16 to S20

Segment signal output for FDP.

Output

T0 to T7

Timing signal output for FDP.

Input

Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
input to XTAL.

EXTAL

Provides voltage for FDP when on-chip resistor is selected under mask option.

FDP

Output

XTAL

Input/Input

Crystal connectors for 32kHz timer/counter clock
oscillation circuit. Connect a 32kHz crystal oscillator
between TEX and TX. For usage as event input, connect
clock oscillation source to TEX, and leave TX open.

PH1/TEX

Input/Output

PH0/TX

Input

System reset pin of active "L" level. RST is input pin.

RST

NC.
Under normal operating conditions, connect to V

Vcc supply.

GND

Vss

(Port H)
2-bit input
port.
(2 pins)

Segment signal output for FDP.

CXP82712/82716

Port B

Data bus

RD (Port B)

Port B direction

Port B data

"0" when reset

Schmitt input

CS0
CS1
SI0
SI1

Pull-up transistors

approx. 100k

Pull-up resistor

8 pins

Hi-Z

When reset

PA0/AN0

PA7/AN7

PB0/CS1
PB1/CS0
PB3/SI0
PB6/SI1

Port B

Data bus

RD (Port B)

Port B output
selection

"0" when reset

Schmitt input

SCK in

Port B data

Port B direction

"0" when reset

SCK OUT

Output enable

Pull-up transistors

approx. 100k

Pull-up resistor

4 pins

2 pins

Hi-Z

PB2/SCK0
PB5/SCK1

Data bus

RD (Port A)

Port A direction

Port A data

Pull-up resistor

Port A input
selection

Input protection
circuit

"0" when reset

Input multiplexer

A/D converter

Pull-up transistors

approx. 100k

I/O Circuit Format for Pins

Port A

Circuit format

CXP82712/82716

2 pins

Hi-Z

When reset

Circuit format

PB4/SO0
PB7/SO1

PC0/KR0

PC7/KR7

8 pins

5 pins

Hi-Z

PE0/EC/INT0
PE1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC

Schmitt input

RD (Port E)

Data bus

EC/INT0
INT1
INT2
INT3/NMI
RMC

Data bus

RD (Port C)

Port C direction

Port C data

"0" when reset

Pull-up transistors approx. 100k

Large current drive of 12mA possible

Pull-up resistor

Key input signal

Data bus

RD (Port B)

Port B output
selection

"0" when reset

Port B data

Port B direction

"0" when reset

Output enable

Pull-up transistors

approx. 100k

Pull-up resistor

"0" when reset

Port E

Port C

Port B

CXP82712/82716

1 pin

PE5/PWM

Data bus

RD (Port E)

Port E output
selection

"0" when reset

Port E data

PWM

Output enable

"1" when reset

Port E

1 pin

High level

PE6/TO/ADJ

Data bus

Port E output
selection

"0" when reset

Port E data

"1" when reset

RD (Port E)

ADJ signals are frequency division outputs

for 32kHz oscillation frequency adjustment.
ADJ2K provides usage as buzzer output.

Port E output
selection

"00" when reset

Port E output
selection

Output enable

ADJ16K

ADJ2K

MPX

Port H

3 pins

Hi-Z or

Low level

When PD
resistor is

connected

PF5/S13

PF7/S15

Data bus

RD (Port F)

Port F data

("0" when reset)

Segment output data

Output selection control signal

Mask option

Pull-down
resistor

FDP

High voltage tolerance transistor

Port F

High level

High level with

150k

resistor

when reset

(

)

(

)

When reset

Circuit format

CXP82712/82716

21 pins

Hi-Z or

Low level

When PD
resistor is

connected

S16 to S20
T15/S21

T8/S28
T0 to T7

Segment output data

Output selection control signal
("0" when reset)

Mask option

Pull-down
resistor

FDP

High voltage tolerance transistor

2 pins

Oscillation

EXTAL
XTAL

EXTAL

XTAL

· Diagram shows circuit
construction for oscillation.

· During stop feedback
resistor is disconnected.
At this time XTAL pin
outputs "H" level.

2 pins

Oscillation

halted

port input

PH1/TEX
PH0/TX

PH2/TEX

PH0/TX

32kHz oscillation
circuit control

"1" when reset

Data
bus

Clock
input

1 pin

Low level

RST

Schmitt input

Pull-up resistor

Mask option

When reset

Circuit format

(

)

CXP82712/82716

and V

OUT

must not exceed V

+ 0.3V.

Specifies output current of general-purpose I/O ports.

The large current drive transistor is an N-ch transistor of Port C (PC).

Note) If the absolute maximum ratings are exceeded, the LSI could reach permanent breakdown. Also, observing

recommended operating conditions is desirable; otherwise, the LSI's reliability could be affected.

Supply voltage

Input voltage

Output voltage

OUT

ODH1

ODH2

ODH

OLC

Topr

Tstg

40 to V

+ 0.3

100

20 to +75

55 to +150

1000

Display output voltage

High level output current

High level
total output current

Low level output current

Low level total output current

Operating temperature

Storage temperature

Allowable power dissipation

0.3 to +7.0

°C

Other than display output pins

: per pin

Display output S13 to S20: per pin

Display output T0 to T7,
T8/S28 to T15/S21: per pin

Total of pins other than display output pins

Total of display output pins

Port 1 pin

Large current port

: per pin

Entire pin total

As P channel transistor is open drain,
V

voltage is determined as standard.

Item

Symbol

Rating

Unit

Remarks

Absolute Maximum Ratings

(Vss = 0V)

CXP82712/82716

High level
input voltage

Low level
input voltage

Operating temperature

Supply voltage

5.5

+ 0.3

0.3V

0.2V

0.4

+75

°C

Item

Symbol

Min.

Max.

Unit

Remarks

4.5

3.5

2.7

2.5

0.7V

0.8V

0.4

0.3

IHS

IHEX

ILS

ILEX

Topr

High speed mode (1/2, 1/4 dividing clock)
guaranteed operation range

Low speed mode (1/16 dividing clock)
guaranteed operation range

Guaranteed operation range with TEX clock

Guaranteed data hold operation range
during stop

Hysteresis input

EXTAL pin

Hysteresis input

EXTAL pin

All regular input port (PA, PB4, PB7, PC, PH).

For pins RST, CS0, CS1, SCK0, SI0, SI1, SCK1, EC/INT0, INT1, INT2, INT3/NMI, RMC.

Specifies only for external clock input.

Recommended Operating Conditions

(Vss = 0V)

CXP82712/82716

= 4.5V, I

= 0.5mA

= 4.5V, I

= 1.2mA

= 4.5V, I

= 1.8mA

= 4.5V, I

= 3.6mA

= 4.5V, I

= 12.0mA

= 5.5V, V

= 5.5V

= 5.5V, V

= 0.4V

= 5.5V, V

= 5.5V

= 5.5V, V

= 0.4V

= 5.5V, V

= 0.4V

= 4.5V, V

= 4.0V

= 5.5V, V

= 0.4V

= 4.5V

= V

2.5V

= 5.5V

= V

35V

FDP

= V

35V

= 5V

FDP

= V

35V

= 5.5V

= 0, 5.5V

High level
output voltage

Display
output current

Open drain
output leak
current (P-CH
Tr off state)

Pull-down
resistor

Input/Output
leak current

4.0

3.5

0.5

0.1

1.5

3.3

µA

PA, PB,
PC, PE5,
PE6

EXTAL

TEX

RST

PA to PC

Item

Symbol

Condition

Min.

PA to PC

PE0 to PE4
RST

S13 to S20
S21/T15 to
S28/T8
T0 to T7

LOL

IHE

ILE

IHT

ILT

ILR

Low level
output voltage

Input current

100

Typ.

0.4

0.6

1.5

400

270

±10

Max.

Unit

DC Characteristics

Electrical Characteristics

(Ta = 20 to +75°C, Vss = 0V)

S13 to S20
S21/T15 to
S28/T8
T0 to T7

S21/T15 to
S28/T8
T0 to T7

S13 to S20

Supply
current

100

µA

1.2

= 5.5V, 10MHz crystal oscillation

= C

= 15pF)

= 3V, 32kHz crystal oscillation

= C

= 47pF)

High-speed mode operation
(1/2 frequency dividing clock)

DD1

DD2

DDS1

DDS2

DDS3

= 5.5V, 10MHz crystal oscillation

= C

= 15pF)

= 3V, 32kHz crystal oscillation

= C

= 47pF)

Sleep mode

Stop mode
V

= 5.5V, 10MHz termination of

10MHz and 32kHz crystal oscillation.

CXP82712/82716

Item

Symbol

Codition

Min.

Pins other
than
S13 to S28,
T0 to T7,
PE5, PE6,
V

, Vss,

FDP

1MHz clock
0V for pins other than the
measured pins

Typ.

Max.

Unit

RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor

has been selected.

Pins PA to PC specify the input current when pull-up resistor has been selected; leakage current when no

resistor has been selected.

Applies when the on-chip pull-down resistor is selected under the mask option.

All output pins are left open.

Input
capacitance

CXP82712/82716

sys indicates the three values below according to the upper two bits (CPU clock selection) of the clock

control register (address: 00FE

sys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")

EXTAL

0.4V

1/fc

Crystal oscillation
Ceramic oscillation

EXTAL

XTAL

External clock

EXTAL

XTAL

74HC04

32kHz clock applied condition
Crystal oscillation

TEX

AC Characteristics

(1) Clock timing

System clock frequency

System clock input pulse width

System clock input
rise and fall time

Event count input clock
pulse width

Event count input clock
rise and fall time

System clock frequency

Event count input clock
input pulse width

Event count input clock
rise and fall time

XTAL
EXTAL

EXTAL

TEX
TX

TEX

MHz

kHz

µs

Item

Symbol

Pins

Conditions

Min.

Unit

Fig. 1, Fig. 2

Fig. 1, Fig. 2
External clock drive

Fig. 3

= 2.7 to 5.5V

Fig. 2 (32kHz clock
applied condition)

Fig. 3

37.5

sys + 50

Typ.

32.768

Max.

200

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V)

Fig. 2. Clock applied conditions

Fig. 1. Clock timing

TEX
EC

0.2V

0.8V

Fig. 3. Event count clock timing

CXP82712/82716

(2) Serial transfer

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V)

Item

CS0

SCK0 (CS1

SCK1)

delay time

CS0

SCK0 (CS1

SCK1)

float delay time

CS0

SO0 (CS1

SO1)

delay time

CS0

SO0 (CS1

SO1)

float delay time

CS0 (CS1) high level width

SCK0 (SCK1) cycle time

SCK0 (SCK1)
high and low level widths

SI0 (SI1) input seup time
(for SCK0

(SCK1

) )

SI0 (SI1) input hold time
(for SCK0

(SCK1

) )

SCK0

SO0

(SCK1

SO1) delay time

DCSK

DCSKF

DCSO

DCSOF

WHCS

KCY

SIK

KSI

KSO

SCK0
(SCK1)

SO0
(SO1)

CS0
(CS1)

SCK0
(SCK1)

SI0
(SI1)

SO0
(SO1)

Input mode

Output mode

Input mode

Output mode

SCK0 (SCK1) input mode

SCK0 (SCK1) output mode

SCK0 (SCK1) input mode

SCK0 (SCK1) output mode

SCK0 (SCK1) input mode

SCK0 (SCK1) output mode

Symbol

Min.

1.5

sys + 200

1.5

sys + 200

1.5

sys + 200

1.5

sys + 200

16000/fc

sys+100

8000/fc 50

100

200

sys + 200

100

sys + 200

100

Max.

Unit

Chip select transfer mode
(SCK0 (SCK1) = output mode)

Chip select transfer mode

Condition

Note 1)

sys indicates the three values below according to the upper two bits (CPU clock selection) of the

clock control register (address: 00FE

sys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")

Note 2) The load condition for the SCK0 (SCK1) output mode, SO0 (SO1) output delay time is 50pF + 1TTL.

CXP82712/82716

CONV

SAMP

IAN

Ta = 25°C
V

= 5.0V

= AV

= 0V

µs

AN0 to AN7

160/f

ADC

12/f

ADC

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Bits

(3) A/D converter characteristics (Ta = 20 to +75°C, V

= 4.5 to 5.5V, AV

REF

= 4.0 to AV

, Vss = AVss = 0V)

±3

LSB

150

5120

5050

4930

Analog input

Linearity error

Digital conversion value

ZT :

Value at which the digital conversion value changes

from 00

to 01

and vice versa.

FT :

Value at which the digital conversion value changes

from FE

to FF

and vice versa.

ADC

indicates the below values due to the Bit6 (CKS) of

A/D control register (address: 00F9

) and the Bit7 (PCK1)

and Bit6 (PCK0) of clock control register (address: 00FE

)

00 (

= f

/2)

01 (

= f

/4)

11 (

= f

/16)

ADC

= f

ADC

= f

ADC

= f

/16

ADC

= f

CSK

PCK1, 0

0 (

/2 selection)

1 (

selection)

ADC

= f

ADC

= f

Conversion time

Sampling time

Analog input voltage

Linearity error

Zero transition
voltage

Full-scale transition
voltage

Resolution

Fig. 5. Definition of A/D converter terms

CXP82712/82716

External interruption
high and low level widths

Reset input low level width

INT0
INT1
INT2
INT3
NMI

RST

32/fc

µs

Item

Symbol

Condition

Min.

Max.

Unit

RSL

(4) Interruption, reset input

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V)

0.2V

0.8V

INT0

INT1

INT2

INT3

NMI

(NMI is specified only for

the falling edge)

Fig 6. Interruption input timing

RSL

0.2V

RST

Fig. 7. RST input timing

Fig. 8. Recommended oscillation circuit

CXP82712/82716

Appendix

EXTAL

XTAL

EXTAL

XTAL

(i) Main clock

EXTAL

XTAL

(ii) Main clock

EXTAL

XTAL

TEX

(iii) Sub clock

Manufacturer

MURATA
MFG
CO., LTD.

RIVER
ELETEC
CORPORATION
.

KINSEKI
LTD.

Model

CSA4.19MG

CSA8.00MTZ

CST4.19MGW

CST8.00MTW

HC-49/U03

HC-49/U (-S)

fc (MHz)

4.19

8.00

10.00

4.19

8.00

10.00

4.19

8.00

10.00

4.19

8.00

10.00

(iii)

32.768kHz

(pF)

Rd (

)

Circuit

example

(i)

CSA10.0MTZ

(ii)

CST10.0MTW

(i)

Those marked with an asterisk (

) signify types with built-in ground capacitance (C

, C

Item

Content

Reset pin pull-up resistor

High tension proof pull-down resistor

Non-existent

Existent

Existent (selected every pin)

Mask Option Table

CXP82712/82716

Characteristics Curves

(100µA)

0.1

5.0

1.0

0.05

(50µA)

0.01

(10µA)

0.5

10.0

20.0

Supply voltage [V]

Supply current [mA]

vs. V

(fc = 10MHz, Ta = 25°C, Typical)

Sleep mode

32kHz mode
(instruction)

32kHz
Sleep mode

fc System clock [MHz]

Supply current [mA]

vs. fc

= 5V, Ta = 25°C, Typical)

1/2 dividing mode

1/16 dividing mode

Sleep mode

1/4 dividing mode

CXP82712/82716

Package Outline

Unit: mm

64PIN

SDIP (PLASTIC)

75 0.

0.9

0.15

0.5

0.1

25 0.

+ 0.

17.

19.

1.778

57.6 0.1

+ 0.4

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN

42/COPPER ALLOY

SONY CODE

EIAJ CODE

JEDEC CODE

SDIP-64P-01

P-SDIP64-17.1x57.6-1.778

SOLDER PLATING

8.6g

+ 0.

0° to 15°

PACKAGE STRUCTURE

64PIN

SDIP (PLASTIC)

0.9

0.15

0.5

0.1

+ 0.

17.

19.

1.778

57.6 0.1

+ 0.4

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN

42/COPPER ALLOY

SONY CODE

EIAJ CODE

JEDEC CODE

SDIP-64P-01

P-SDIP64-17.1x57.6-1.778

SOLDER PLATING

8.6g

+ 0.

0° to 15°

PACKAGE STRUCTURE

LEAD SPECIFICATIONS

ITEM

LEAD MATERIAL

ALLOY 42

LEAD TREATMENT

Sn-Bi 2.5%

LEAD TREATMENT THICKNESS

5-18

SPEC.

Sony Corporation

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXP82712/82716

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXP82712/82716