CXP82940/82948/82952/82960

E95130-PK

CMOS 8-bit Single Chip Microcomputer

Description

The CXP82940/82948/82952/82960 is a CMOS 8-bit

single chip microcomputer integrating on a single
chip an A/D converter, serial interface, timer/counter,
time base timer, fluorescent display panel
controller/driver, I

C bus interface, remote control

transmission circuit, remote control reception circuit,
and 32kHz timer/counter besides the basic
configurations of 8-bit CPU, ROM, RAM, and I/O
port.

Features1
· Wide-range instruction system (213 instructions)

to cover various types of data

-- 16-bit arithmetic/multiplication and division/boolean bit operation instructions

· Minimum instruction cycle

250ns at 16MHz operation
(122µs at 32kHz operation)

· Incorporated ROM capacity

40K bytes (CXP82940)
48K bytes (CXP82948)
52K bytes (CXP82952)
60K bytes (CXP82960)

· Incorporated RAM capacity

2048 bytes (including fluorescent display area)

· Periphera; functions

-- A/D converter

8-bit, 8-channel, successive approximation method
(Conversion time of 20µs/16MHz)

-- Serial interface

Buffer RAM incorporated (Auto transfer for 1 to 32 bytes), 1 channel
8-bit, 8-stage FIFO incorporated
(Auto transfer for 1 to 8 bytes), 1 channel

-- Timers

8-bit timer, 8-bit timer/counter, 19-bit time base timer
32kHz timer/counter

-- Fluorescent display panel controller/driver

Maximum of 196 segments display possible
1 to 16-digit dynamic display
Dimmer function
High voltage drive output (40V)
Incorporated pull-down resistor (Mask option)
Hardware key scan function
Maximum of 12

8 key matrix supportable

-- I

C bus interface

-- Remote control transmission circuit

Auto transmission for 1 to 32 bytes,
restart function, carrier output function

-- Remote control reception circuit

8-bit pulse measurement counter, 6-stage FIFO

· Interruption

16 factors, 15 vectors, multi-interruption possible

· Standby mode

SLEEP/STOP

· Package

80-pin plastic QFP

· Piggyback/evaluation chip

CXP82900 80-pin ceramic QFP

Perchase of Sony's I

C components conveys a licence under the Philips I

C Patent Rights to use these components

in an I

C system, provided that the system conforms to the I

C Standard Specifications as defined by Philips.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

80 pin QFP (Plastic)

Structure

Silicon gate CMOS IC

CXP82940/82948/82952/82960

RAM

2048 BYTES

SPC 700

CPU CORE

INTERRUPT CONTROLLER

A/D CONVERTER

SERIAL

INTERFACE

UNIT (CH0)

SERIAL

INTERFACE

UNIT (CH1)

8 BIT TIMER/COUNTER 0

8 BIT TIMER 1

C BUS

INTERFACE UNIT

INT3/NMI

INT1

INT0

INT2

AN0 to AN7

PA0 to PA7

BUFFER

RAM

REMOCON IN

FDP

CONTROLLER/

DRIVER

32KHz

TIMER/COUNTER

PRESCALER/

TIME BASE TIMER

RST

PORT A

PORT B

PORT C

PORT D

PORT E

PORT F

PORT G

PB0 to PB7

PC0 to PC7

PD0 to PD7

PE0 to PE5

PF0 to PF3

PG0 to PG3

PE6 to PE7

TEX

EXTAL

XTAL

REF

T0 to T7

T8/S19 to T15/S12

S0 to S11

FDP

KR0 to KR7

RMCO

RMC

CS0

SI0

SO0

SCK0

SI1

SO1

SCK1

SCL0

SCL1

SDA0

ROM

40K/48K/52K/60K

BYTES

RAM

KEY SCAN

CLOCK

GENERATOR

SYSTEM CONTROL

BUFFER

RAM

REMOCON OUT

SDA1

FIFO

ADJ

Block Diagram

CXP82940/82948/82952/82960

Pin Assignment (Top View)

PE0/EC/INT0

25 26 27 28 29 30

31 32 33

70 69 68 67

PB5/SCK1

PB3/SI0

PB4/SO0

PB6/SI1

PB7/SO1

PA7/AN7

PA0/AN0

PA1/AN1

PA2/AN2

PA3/AN3

PA4/AN4

PA5/AN5

PA6/AN6

T10/S17

T11/S16

T12/S15

T13/S14

T14/S13

T15/S12

S11

S10

PD7/S7

PD6/S6

T8/S19

T9/S18

PC6/KR6

PC7/KR7

PD5/S5

PD4/S4

PD3/S3

PD2/S2

PD1/S1

PD0/S0

FDP

TEX

PG3

PG2

PG1

PG0

PE1/INT1

PE2/INT2

PE3/INT3/NMI

PE4/RMC

PE5

PE6/RMCO

PE7/TO/ADJ

PB0

PB1/CS0

PB2/SCK0

PC0/KR0

PC1/KR1

PC2/KR2

PC3/KR3

PC4/KR4

PC5/KR5

REF

PF0/SCL0

PF1/SCL1

PF2/SDA0

PF3/SDA1

EXTAL

XTAL

RST

Note) NC (Pin 75) must be connected to V

CXP82940/82948/82952/82960

Pin Description

Pin code

I/O

Functions

I/O/
Analog input

PA0/AN0

PA7/AN7

Analog inputs to A/D converter. (8 pins)

I/O/Input

PC0/KR0

PC7/KR7

PE0/INT0/EC

PE1/INT1

PE2/INT2

PE3/INT3/
NMI

PE4/RMC

PE5

PE6/RMCO

PE7/TO/ADJ

PF0/SCL0
PF1/SCL1

PF2/SDA0
PF3/SDA1

Input/Input/Input

Input/Input

Input/Input/Input

Input/Input

Input

Output/Output

Output/Output/
Output

Output/I/O

Serves as key return inputs when operating
key scan with fluorescent display panel (FDP)
segment signal (8 pins).

(Port E)
8-bit port. Lower 6 bits
are for inputs; upper
2 bits are for outputs.
(8 pins)

(Port F)
4-bit output port,
operating as N-ch open
drain output for large
current (12mA).
(4 pins)

External event inputs for
timer/counter.

Inputs for
external
interruption
request.
(4 pins)

Non-maskable interruption
request input.

Remote control reception circuit input.

Carrier output of remote control transmission
circuit.

Output for the timer/counter rectangular waves,
and 32kHz oscillation dividing frequency.

Transfer clock I/Os for I

C bus interface.

Transfer data I/Os for I

C bus interface.

I/O

I/O/Input

I/O/I/O

I/O/Input

I/O/Output

I/O/I/O

I/O/Input

I/O/Output

PB0

PB1/CS0

PB2/SCK0

PB3/SI0

PB4/SO0

PB5/SCK1

PB6/SI1

PB7/SO1

(Port B)
8-bit I/O port. I/O can
be set in a unit of
single bits.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)

Chip select input for serial interface (CH0).

Serial clock I/O (CH0).

Serial data input (CH0).

Serial data output (CH0).

Serial clock I/O (CH1).

Serial data input (CH1).

Serial data output (CH1).

(Port A)
8-bit I/O port. I/O can
be set in a unit of
single bits.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)

(Port C)
8-bit I/O port. I/O can
be set in a unit of single
bits. Capable of driving
12mA sync current.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)

CXP82940/82948/82952/82960

Pin code

I/O

Functions

Output/Output

PD0/S0

PD7/S7

(Port D)
8-bit output ports.
(8 pins)

FDP segment signal outputs.
(8 pins)

Output

S8 to S11

FDP segment signal outputs. (4 pins)

Output/Output

T8/S12

T15/S19

Outputs for FDP timing signals/segment signals.
(8 pins)

I/O

PG0 to PG3

(Port G)
8-bit I/O port. I/O can be set in a unit of single bits.
Incorporation of pull-up resistor can be set through the software in a unit
of 4 bits.
(4 pins)

FDP

EXTAL

XTAL

TEX

RST

REF

Input

Output

Input

Output

Input

FDP voltage supply when incorporated resistor is set by mask option.

T0 to T7

FDP timing signal outputs.

Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
input to XTAL.

Crystal connectors for 32kHz timer/counter clock oscillation. Set 32kHz
crystal oscillator between TEX and TX. For usage as event input, attach
clock source to TEX, and open TX.

Low-level active, system reset.

NC. Under normal operation, connect to V

Positive power supply for A/D converter.

Reference voltage input for A/D converter.

A/D converter GND.

Positive power supply.

GND.

Output

CXP82940/82948/82952/82960

Port B

Data bus

RD (Port B)

Port B direction

Port B data

Pull-up resistor

"0" when reset

Pull-up transistor approx. 100k

Schmitt input

CS0
SI0
SI1

Not Schmitt input for SI0 and SI1.

8 pins

Hi-Z

When reset

PA0/AN0

PA7/AN7

PB1/CS0
PB3/SI0
PB6/SI1

Port B

Data bus

RD (Port B)

Port B output
selection

"0" when reset

Pull-up transistor approx. 100k

Schmitt input

SCK in

Port B data

Port B direction

"0" when reset

Pull-up resistor

"0" when reset

SCK OUT

Output enable

3 pins

2 pins

Hi-Z

PB2/SCK0
PB5/SCK1

Data bus

RD (Port A)

Port A direction

Port A data

Pull-up resistor

Port A input
selection

Input
protection
circuit

"0" when reset

Input multiplexer

A/D converter

Pull-up transistor approx. 100k

Port A

Circuit format

I/O Circuit Format for Pins

CXP82940/82948/82952/82960

2 pins

Hi-Z

PB4/SO0
PB7/SO1

PC0/KR0

PC7/KR7

8 pins

5 pins

1 pin

Hi-Z

High level

Hi-Z

PE0/EC/INT0
PE1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC

Schmitt input

RD (Port E)

Data bus

EC/INT0
INT1
INT2
INT3/NMI
RMC

Data bus

RD (Port C)

Port C direction

Port C data

Pull-up resistor

"0" when reset

Large current 12mA

Pull-up transistor approx. 100k

Key input signal

Data bus

RD (Port B)

Port B output
selection

"0" when reset

Pull-up transistor approx. 100k

Port B data

Port B direction

"0" when reset

Pull-up resistor

Output enable

"0" when reset

Port E

PE5

1 pin

PE6/RMCO

RD (Port E)

Data bus

Port E

Port E output selection

RD (Port E)

Data bus

"0" when reset

Reset E data

"1" when reset

Remote control
transmission circuit

Output enable

Port E

Port C

Port B

When reset

Circuit format

CXP82940/82948/82952/82960

1 pin

PE7/TO/ADJ

Port E data

ADJ signal is a frequency dividing output for

32kHz oscillation frequency adjustment.
ADJ2 can be used for buzzer output.

Pull-up transistor approx. 150k

Port E output selection (lower)

"00" when reset

Port E output selection (upper)

ADJ16K

ADJ2K

TO output enable

MPX

Internal reset signal

"1" when reset

Port E

4 pins

Hi-Z

PF0/SCL0
PF1/SCL1
PF2/SDA0
PF3/SDA1

SCL, SDA
(I

C circuit)

Port F data

SCL, SDA

C output enable

("0" when reset)

Large current
12mA

To internal I

C pin

(to SCL1 for SCL0)

BUS SW

"1" when reset

Schmitt input

Port F

5 pins

Hi-Z

PB0
PG0 to PG3

Data bus

RD (Port B or Port G)

Port B data or
Port G data

"0" when reset

Pull-up transistor approx. 100k

Pull-up resistor

"0" when reset

Port B direction or
Port G direction

Port B

Port G

High level
(with approx.
150k

resistor when
reset)

When reset

Circuit format

CXP82940/82948/82952/82960

20 pins

Hi-Z or
Low level
(when PD
resistor is
connected)

S8 to S11
T15/S12

T8/S19
T0 to T7

Segment output data
Timing output data

Output selection
control signal
("0" when reset)

Mask option

Pull-down
resistor

FDP

High voltage drive transistor

2 pins

Oscillation

EXTAL
XTAL

EXTAL

XTAL

· Diagram shows circuit

composition during oscillation.

· Feedback resistor is removed

during stop, and XTAL
becomes High.

2 pins

Oscillation

TEX
TX

TEX

·Diagram shows circuit

composition during oscillation.

·When the operation of the oscillation

circuit is stopped by the software,
the feedback resistor is removed,
and TEX becomes Low level and TX
becomes High level.

1 pin

Low level

RST

Schmitt input

Pull-up resistor

Mask option

8 pins

Hi-Z or
Low level
(when PD
resistor is
connected)

PD0/S0

PD7/S7

Data bus

RD (Port D)

Port D data

Segment output data

Output selection
control signal
("0" when reset)

Mask option

Pull-down
transistor

FDP

High voltage drive transistor

Port D

When reset

Circuit format

CXP82940/82948/82952/82960

and V

OUT

must not exceed V

+ 0.3V.

Specifies output current of general-purpose I/O ports.

The large current drive transistor is the N-CH transistor of Port C (PC) and Port F (PF).

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be

conducted under the recommended operating conditions. Exceeding these conditions may adversely affect

the reliability of the LSI.

Supply voltage

Input voltage

Output voltage

Display output voltage

High level output current

High level total output
current

Low level output current

Low level total output current

Operating temperature

Storage temperature

Allowable power dissipation

OUT

ODH1

ODH2

ODH

OLC

Topr

Tstg

0.3 to +7.0

40 to V

+ 0.3

100

20 to +75

55 to +150

600

°C

As P channel transistor is open drain,
V

is reference.

All pins excluding outputs

(value per pin)

Display outputs S0 to S11 (value per pin)

Display outputs T0 to T7, and T8/S19 to
T15/S12 (value per pin)

Total for all pins excluding display outputs

Total for all display outputs

Port (value per pin)

Large current Port (value per pin)

Total for all output pins

Item

Symbol

Rating

Unit

Remarks

Absolute Maximum Ratings

(Vss = 0V reference)

CXP82940/82948/82952/82960

High level input
voltage

Low level input
voltage

Operating temperature

Supply voltage

5.5

+ 0.3

0.3V

0.2V

0.4

+75

°C

Item

Symbol

Min.

Max.

Unit

Remarks

4.5

3.5

2.7

2.5

0.7V

0.8V

0.4

0.3

IHS

IHEX

ILS

ILEX

Topr

Guaranteed operation range for high-speed
mode (1/2, 1/4 frequency dividing clock)

Guaranteed operation range for low-speed
mode (1/16 frequency dividing clock) or
SLEEP mode

Guaranteed operation range with TEX
clock

Guaranteed data hold range during STOP

Hysteresis input

EXTAL

Hysteresis input

EXTAL

Value for each pin of normal input port (PA, PB0, PB3, PB4, PB6, PB7, PC, PE5, PG).

Value of the following pins: RST, CS0, SCK0, SCK1, EC/INT0, INT1, INT2, INT3/NMI, RMC, SCL0, SCL1,

SDA0, SDA1.

Specifies only during external clock input.

Recommended Operating Conditions

(Vss = 0V reference)

CXP82940/82948/82952/82960

= 4.5V, I

= 0.5mA

= 4.5V, I

= 1.2mA

= 4.5V, I

= 1.8mA

= 4.5V, I

= 3.6mA

= 4.5V, I

= 12.0mA

= 4.5V, I

= 3.0mA

= 4.5V, I

= 4.0mA

= 5.5V, V

= 5.5V

= 5.5V, V

= 0.4V

= 5.5V, V

= 5.5V

= 5.5V, V

= 0.4V

= 5.5V, V

= 0.4V

= 4.5V, V

= 4.0V

= 4.5V

= V

2.5V

= 5.5V

= V

35V

FDP

= V

35V

= 5V

FDP

= 30V

= 5.5V

= 0, 5.5V

= 5.5V, V

= 5.5V

= 4.5V

SCL0

= V

SCL1

= 2.25V

SDA0

= V

SDA1

= 2.25V

4.0

3.5

0.5

0.1

1.5

3.3

µA

PC, PF

PF
(SCL0, SCL1,
SDA0, SDA1)

PA, PB,
PC, PE6,
PE7, PG

EXTAL

TEX

RST

PA to PC

RST

S0 to S11,
S12/T15 to
S19/T8,
T0 to T7

LOL

IHE

ILE

IHT

ILT

ILR

100

0.4

0.6

1.5

0.4

0.6

400

270

±10

120

S0 to S11,
S12/T15 to
S19/T8,
T0 to T7

Open drain
output leakage
current (N-ch Tr
off state)

LOH

C bus switch

connection
impedance
(Output Tr off
state)

SCL0: SCL1
SDA0: SDA1

S12/T15 to
S19/T8,
T0 to T7

S0 to S11

High level
output current

Display output
current

Item

Symbol

Pins

Conditions

Min.

Open drain output
leakage current
(P-CH Tr off state)

Pull-down
resistance

I/O
leakage current

Low level
output current

Input current

Typ.

Max.

Unit

DC Characteristics

Electrical Characteristics

(Ta = 20 to +75°C, Vss = 0V reference)

CXP82940/82948/82952/82960

PA to PC,
PE0 to PE5,
PF, PG,
EXTAL,
XTAL, TEX,
TX, RST

RST specifies the input current when pull-up resistance has been selected; leakage current when no

resistance has been selected.

PA to PC and PG specify the input current when pull-up resistance has been selected, leakage current

when no resistance has been selected.

When incorporated pull-down resistance has been selected through mask option.

When all pins are open.

Power supply
current

Input
capacity

DDS1

DD2

DD1

DDS2

DDS3

STOP mode
V

= 5.5V, termination of 16MHz

and 32kHz crystal oscillation

= 5.5V, 16MHz crystal

oscillation (C

= C

= 15pF)

= 3V, 32kHz crystal

oscillation (C

= C

= 47pF)

2.5

µA

= 5.5V, 10MHz crystal

oscillation (C

= C

= 15pF)

= 3V, 32MHz crystal

oscillation (C

= C

= 47pF)

µA

Clock 1MHz
0V for all pins excluding
measured pins

SLEEP mode

High speed mode operation
(1/2 frequency dividing clock)

100

µA

Symbol

Pins

Conditions

Min.

Typ.

Max.

Unit

Item

CXP82940/82948/82952/82960

sys indicates the three values below according to the upper two bits (CPU clock selected) of the control

clock registor (address: 00FE

sys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")

EXTAL

0.4V

1/fc

Crystal oscillation
Ceramic oscillation

EXTAL

XTAL

External clock

EXTAL

XTAL

74HC04

32kHz clock applied condition
Crystal oscillation

TEX

TEX
EC

0.2V

0.8V

AC Characteristics

(1) Clock timing

System clock frequency

System clock input pulse width

System clock input rise time,
fall time

Event count input clock
pulse width

Event count input clock
rise time, fall time

System clock frequency

Event count input
pulse width

Event count input rise time,
fall time

XTAL
EXTAL

EXTAL

TEX
TX

TEX

MHz

kHz

µs

Item

Symbol

Conditions

Min.

Unit

Fig. 1, Fig. 2

Fig. 1, Fig. 2
External clock drive

Fig. 3

= 2.7 to 5.5V

Fig. 2 (32kHz clock
applied condition)

Fig. 3

sys

Typ.

32.768

Max.

200

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Fig. 2. Clock applied conditions

Fig. 1. Clock timing

Fig. 3. Event count clock timing

CXP82940/82948/82952/82960

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode

Note 1)

sys indicates the three values below according to the upper two bits (CPU clock selected) of the

control clock registor (address: 00FE

sys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")

Note 2) CS, SCK, SI and SO correspond to each pin of CS0, SCK0, SI0 and SO0.

Note 3) The load condition for the SCK output mode, SO output delay time is 50pF + 1TTL.

(2) Serial transfer (CH0)

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Item

SCK

delay time

SCK

float delay time

delay time

float delay time

CS High level width

SCK cycle time

SCK
High, Low level width

SI input setup time
(for SCK

)

SI input hold time
(for SCK

)

SCK

delay time

DCSK

DCSKF

DCSO

DCSOF

WHCS

KCY

SIK

KSI

KSO

SCK0

SO0

CS0

SCK0

SI0

SO0

Input mode

Output mode

Input mode

Output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

Symbol

Min.

1.5

sys + 200

1.5

sys + 200

1.5

sys + 200

1.5

sys + 200

8000/fc

sys + 100

8000/fc 100

sys + 100

200

sys + 100

100

sys + 200

100

Max.

Unit

Condition

CXP82940/82948/82952/82960

Serial transfer (CH1) (SIO mode)

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Item

SCK1 cycle time

KCY

SCK1

Input mode

Ouput mode

Input mode

Ouput mode

SCK1 input mode

SCK1 ouput mode

SCK1 input mode

SCK1 ouput mode

SCK1 input mode

SCK1 ouput mode

sys + 200

16000/fc

sys + 100

8000/fc 50

100

200

sys + 200

100

sys + 200

100

SCK1

SI1

SO1

SIK

KSI

KSO

SCK1
High, Low level width

SI1 input setup time
(for SCK1

)

SI1 input hold time
(for SCK1

)

SCK1

SO1 delay time

Symbol

Condition

Min.

Max.

Unit

Note 1)

sys indicates the three values below according to the upper two bits (CPU clock selected) of the

control clock registor (address: 00FE

sys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")

Note 2) The load condition for the SCK1output mode, SO1 output delay time is 50pF + 1TTL.

Fig. 5. Serial transfer CH1 timing (SIO mode)

SCK1

SI1

SO1

KCY

0.2V

0.8V

SIK

KSI

KSO

Input data

Output data

0.2V

0.8V

0.2V

0.8V

CXP82940/82948/82952/82960

SO1 cycle time

SI1 data setup time

SI1 data hold time

LCY

LSU

LHD

SO1
SI1

SI1

104

µs

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

LCY

is specified only when the lower two bits (SO1 clock selected) of the serial mode register (CH1) (SIOM1:

address 01E2

) is set to 104µs.

Note) The load condition for SO1 is 50pF + 1TTL.

Serial transfer (CH1) (Special mode)

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Fig. 6. Serial transfer CH1 timing (Special mode)

SO1

SI1

LCY

Start bit

Output data bit

LCY

0.5V

0.8V

0.2V

LCY/2

LSU

LHD

Input

data bit

CXP82940/82948/82952/82960

CONV

SAMP

REF

IAN

REF

AN0 to AN7

Ta = 25°C
V

= AV

REF

= 5.0V

= AV

= 0V

= AV

= 4.5 to 5.5V

REF

REFS

µs

REF

1.0

µA

0.6

160/f

ADC

12/f

ADC

0.5

Bits

±3

LSB

5030

4970

4910

Fig. 7. Definition of A/D converter terms

Analog input

Linearity error

Digital conversion value

00 (

= f

/2)

01 (

= f

/4)

11 (

= f

/16)

ADC

= f

ADC

= f

ADC

= f

/16

0 (

/2 selection)

CKS

PCK1, PCK0

ADC

= f

ADC

= f

ADC

= f

1 (

selection)

Conversion time

Sampling time

Reference input voltage

Analog input voltage

Operation mode

SLEEP mode
STOP mode
32kHz operation mode

Linearity error

Zero transition
voltage

Full-scale
transition voltage

Resolution

REF

current

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

(3) A/D converter characteristics

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, AV

REF

= 4.0 to AV

, Vss = AV

= 0V reference)

: Value at which the digital conversion value change

from 00

to 01

and vice versa.

: Value at which the digital conversion value changes

from FE

to FF

and vice versa.

ADC

indicates the below values due to the contents of bit 6

(CKS) of the A/D control register (address: 00F9

) and bits 7

(PCK1) and 6 (PCK0) of the clock control register (address:

00FE

CXP82940/82948/82952/82960

(5) I

C bus timing

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Item

SCL clock frequency

Bus-free time before starting transfer

Hold time for starting transfer

Clock Low level width

Clock High level width

Setup time for repetitive transfers

Data hold time

Data setup time

SDA, SCL rise time

SDA, SCL fall time

Setup time for transfer completion

SLC

BUF

HD; STA

LOW

HIGH

SU; STA

HD; DAT

SU; DAT

SU; STO

SCL

SDA, SCL

SCL

SDA, SCL

4.7

4.0

4.7

4.0

4.7

250

4.7

100

300

kHz

µs

Symbol

Condition

Min.

Max.

Unit

The data hold time must exceed 300ns because the SCL rise time (300ns max.) is not taken into consideration.

Fig.10. I

C bus transfer timing

SU ; STO

SU ; STA

HD ; STA

SU ; DAT

HIGH

HD ; DAT

LOW

HD ; STA

BUF

SDA

SCL

Fig.11. Recommended circuit example for I

C device

device

SDA0
(or SDA1)

SCL0
(or SCL1)

· Pull-up resistors (R

) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1).

· Serial resistance (Rs = 300

or less) of SDA0 (or SDA1) and SCL0 (SCL1) reduces spike noise caused by

CRT flash-over.

CXP82940/82948/82952/82960

Appendix

Fig. 12. Recommended oscillation circuit

EXTAL

XTAL

(i)

TEX

(ii)

Manufacturer

RIVER
ELETEC
CO., LTD.

KINSEKI
LTD.

Model

HC-49/U03

HC-49/U (-S)

fc (MHz)

8.00

10.00

12.00

8.00

10.00

12.00

16.00

470k

(ii)

32.768kHz

16 (12)

16.00

16 (12)

(pF)

Rd (

)

Circuit

example

(i)

Item

Content

Reset pin pull-up resistance

Non-existent

Existent

Non-existent

Existent (Selectable for each pin)

Mask Option Table

High voltage drive output port pull-down resistance

CXP82940/82948/82952/82960

Characteristics Curve

Supply voltage [ V ]

vs. V

(fc = 16MHz, Ta = 25°C, Typical)

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode

SLEEP mode

1/2 dividing mode
1/4 dividing mode

1/16 dividing mode

SLEEP mode

32kHz mode
(instruction)

32kHz
SLEEP mode

Supply current [mA]

30
20

0.5

(500µA)

0.1

(100µA)

0.05

(50µA)

0.01

(10µA)

vs. fc

= 5V, Ta = 25°C, Typical)

Frequency [MHz]

Supply current [mA]

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