CMOS 8-bit Single Chip Microcomputer
Description
The CXP841P24 is a CMOS 8-bit microcomputer
integrating on a single chip an A/D converter, serial
interface, timer/counter, time base timer, capture
timer/counter, and remote control reception circuit
besides the basic configurations of 8-bit CPU, ROM,
RAM, and I/O port.
The CXP841P24 also provides a sleep/stop function
that enables lower power consumption.
This IC is the PROM-incorporated version of the
CXP84124 with built-in mask ROM. This provides the
additional feature of being able to write directly into
the program. Thus, it is most suitable for evaluation
use during system development and for small-quantity
production.
Features
Wide-range instruction system (213 instructions) to cover various types of data
-- 16-bit arithmetic/multiplication and division/boolean bit operation instructions
Minimum instruction cycle
400ns at 10MHz operation
122s at 32kHz operation
Incorporated PROM capacity
24K bytes
Incorporated RAM capacity
624 bytes
Peripheral functions
-- A/D converter
8 bits, 8 channels, successive approximation method
(Conversion time of 32s/10MHz)
-- Serial interface
SIO with 8-bit, 8-stage FIFO incorporated for data use
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit standard SIO, 1 channel
-- Timer
8-bit timer
8-bit timer/counter
19-bit time base timer
16-bit capture timer/counter
32kHz timer/counter
-- Remote control reception circuit
Incorporated noise elimination circuit
Incorporated 8-bit, 6-stage FIFO for measurement data
-- PWM output
14 bits, 1 channel
Interruption
14 factors, 15 vectors, multi-interruption possible
Standby mode
Sleep/stop
Package
80-pin plastic QFP
1
E93217A7X-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXP841P24
80 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
2
CXP841P24
8
2
2
2
2
A
N
0
t
o
A
N
7
P
E
4
/
P
W
M
P
E
2
/
R
M
C
P
B
1
/
C
S
0
P
B
3
/
S
I
0
P
B
4
/
S
O
0
P
B
2
/
S
C
K
0
P
B
6
/
S
I
1
P
B
7
/
S
O
1
P
B
5
/
S
C
K
1
P
E
5
/
T
O
P
B
0
/
C
I
N
T
P
E
1
/
E
C
1
P
E
0
/
E
C
0
A
/
D
C
O
N
V
E
R
T
E
R
AV
ss
AV
RE
F
1
4
B
I
T
P
W
M
G
E
N
E
R
A
T
O
R
R
E
M
O
C
O
N
F
I
F
O
S
E
R
I
A
L
I
N
T
E
R
F
A
C
E
U
N
I
T
0
F
I
F
O
S
E
R
I
A
L
I
N
T
E
R
F
A
C
E
U
N
I
T
1
8
B
I
T
T
I
M
E
R
/
C
O
U
N
T
E
R
0
8
B
I
T
T
I
M
E
R
1
1
6
B
I
T
C
A
P
T
U
R
E
T
I
M
E
R
/
C
O
U
N
T
E
R
2
IN
TE
RR
UP
T C
ON
TR
OL
LE
R
PI0
/IN
T0
PI1
/IN
T1
PI2
/IN
T2
PI3
/IN
T3
PE
3/N
MI
S
P
C
7
0
0
C
P
U
C
O
R
E
P
R
O
M
2
4
K
B
Y
T
E
S
C
L
O
C
K
G
E
N
.
/
S
Y
S
T
E
M
C
O
N
T
R
O
L
R
A
M
6
2
4
B
Y
T
E
S
P
R
E
S
C
A
L
E
R
/
T
I
M
E
B
A
S
E
T
I
M
E
R
EX
TA
L
XT
AL
V
DD
Vs
s
PO
RT
A
7
8
8
4
2
8
P
A
0
t
o
P
A
7
P
B
0
t
o
P
B
6
P
B
7
P
C
0
t
o
P
C
7
P
D
0
t
o
P
D
7
P
E
0
t
o
P
E
3
P
E
4
t
o
P
E
5
P
F
0
t
o
P
F
7
P
G
0
t
o
P
G
7
P
I
0
t
o
P
I
7
RS
T
8
8
8
PO
RT
B
PO
RT
C
PO
RT
D
PO
RT
E
PO
RT
F
PO
RT
G
PO
RT
I
TE
X
TX
P
H
0
t
o
P
H
7
8
PO
RT
H
3
2
k
H
z
T
I
M
E
R
/
C
O
U
N
T
E
R
Vp
p
Block Diagram
3
CXP841P24
Pin Assignment (Top View)
PF3
PF4
PF5
PF6
PF7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PH0
PH1
PH2
PI4
PI3/INT3
PI2/INT2
PI1/INT1
PI0/INT0
PE5TO
PE4/PWM
PE3/NMI
PE2/RMC
PE1/EC1
PE0/EC0
PB7/SO1
PB6/SI1
PB5/SCK1
PB4/SO0
PB3/SI0
PB2/SCK0
PB1/CS0
PB0/CINT
PA7/AN7
PA6/AN6
PA5/AN5
PA4/AN4
PA3/AN3
P
H
3
P
H
4
P
H
5
P
H
6
P
H
7
R
S
T
E
X
T
A
L
X
T
A
L
V
S
S
T
X
T
E
X
A
V
S
S
A
V
R
E
F
P
A
0
/
A
N
0
P
A
1
/
A
N
1
P
A
2
/
A
N
2
P
F
2
P
F
1
P
F
0
P
G
7
P
G
6
P
G
5
P
G
4
V
p
p
V
D
D
P
G
3
P
G
2
P
G
1
P
G
0
P
I
7
P
I
6
P
I
5
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 26 27 28 29 30
40
39
38
37
36
35
34
31 32 33
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
70 69 68 67
63
64
65
66
61
62
71
72
73
74
75
76
77
78
79
80
1
Note) Vpp (Pin 73) must be connected to V
DD
.
4
CXP841P24
Pin Description
Symbol
I/O
Description
I/O/Analog input
PA0/AN0
to
PA7/AN7
(Port A)
8-bit I/O port. I/O can be
set in a unit of single bits.
Incorporation of the
pull-up resistance can be
set through the software
in a unit of 4 bits.
(8 pins)
Analog inputs to A/D converter.
(8 pins)
I/O
PC0 to PC7
(Port C)
8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving
12mA sink current. Incorporation of pull-up resistor can be set through
the software in a unit of 4 bits.
(8 pins)
I/O
PD0 to PD7
(Port D)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-
up resistor can be set through the software in a unit of 4 bits.
(8 pins)
I/O
PF0 to PF7
(Port F)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of
pull-up resistor can be set through the software in a unit of 4 bits.
(8 pins)
Input/Input
Input/Input
Input/Input
Input/Input
Output/Output
Output/Output/
Output
PE0/EC0
PE1/EC1
PE2/RMC
PE3/NMI
PE4/PWM
PE5/TO/ADJ
(Port E)
6-bit port. Lower 4 bits
are for inputs; upper
2 bits are for outputs.
Incorporation of pull-up
resistor can be set
through the software.
(6 pins)
External event inputs for timer/counter.
(2 pins)
Remote control reception circuit input.
Non-maskable interruption request input.
14-bit PWM output.
Rectangular wave output for 16-bit
timer/counter. Output for 32kHz oscillation
frequency demultiplication.
I/O/Input
I/O/Input
I/O/I/O
I/O/Input
I/O/Output
I/O/I/O
I/O/Input
Output/Output
PB0/CINT
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
(Port B)
Lower 7-bit I/O port in
which I/O can be set in a
unit of single bits. Also,
an uppermost bit (PB7)
exclusively for output.
Incorporation of pull-up
resistor can be set
through the software in a
unit of 4 bits.
(8 pins)
External capture input to 16-bit timer/counter.
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).
5
CXP841P24
Symbol
I/O
Description
I/O
PG0 to PG7
(Port G)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-
up resistor can be set through the software in a unit of 4 bits.
(8 pins)
I/O
PH0 to PH7
(Port H)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-
up resistor can be set through the software in a unit of 4 bits.
(8 pins)
I/O/Input
PI0/INT0
to
PI3/INT3
I/O
PI4 to PI7
Input
Crystal connectors for system clock oscillation. When the clock is supplied
externally, input to EXTAL; opposite phase clock should be input to XTAL.
EXTAL
Output
XTAL
Input
Crystal connectors for 32kHz timer/counter clock generation circuit.
Connect a 32kHz crystal oscillator between TEX and TX.
For usage as event input, connect clock oscillation source to TEX, and
open TX.
TEX
Output
TX
Input
Low-level active, system reset.
RST
Input
Reference voltage input for A/D converter.
AV
REF
A/D converter GND.
AVss
Positive power supply.
V
DD
Positive power supply for incorporated PROM writing.
Connect to V
DD
during normal operation.
Vpp
GND
Vss
(Port I)
8-bit I/O ports. I/O can be set in a unit of single
bits. Incorporation of pull-up resistor can be set
through the software in a unit of 4 bits.
(8 pins)
External interruption
request inputs.
6
CXP841P24
Port B
Data bus
RD (Port B)
Port B direction
IP
Port B data
Pull-up resistance
"0" when reset
"0" when reset
Pull-up transistors
approx. 10k
Schmitt input
CINT
CS0
SI0
SI1
8 pins
Hi-Z
Hi-Z
When reset
PA0/AN0
to
PA7/AN7
PB0/CINT
PB1/CS0
PB3/SI0
PB6/SI1
Port B
4 pins
2 pins
Hi-Z
PB2/SCK0
PB5/SCK1
Data bus
RD (Port A)
Port A direction
IP
Port A data
Pull-up resistance
Port A input
selection
Input protection
circuit
"0" when reset
"0" when reset
"0" when reset
Input multiplexer
A/D converter
Pull-up transistors
approx. 10k
Input/Output Circuit Formats for Pins
Port A
Pin
Circuit format
Data bus
RD (Port B)
IP
Port B output
selection
"0" when reset
Pull-up transistors
approx. 10k
Schmitt input
SCK in
Port B data
Port B direction
"0" when reset
Pull-up resistance
"0" when reset
SCK OUT
Output enable
7
CXP841P24
1 pin
Hi-Z
Hi-Z
Pin
When reset
Circuit format
PB4/SO0
PC0 to PC7
8 pins
4 pins
Hi-Z
PE0/EC0
PE1/EC1
PE2/RMC
PE3/NMI
IP
Schmitt input
RD (Port E)
Data bus
EC0
EC1
RMC/NMI
Data bus
RD (Port C)
Port C direction
IP
Port C data
Pull-up resistance
"0" when reset
"0" when reset
1
High current drive
of 12mA possible
2
Pull-up transistors
approx. 10k
2
1
Data bus
RD (Port B)
IP
Port B output
selection
"0" when reset
Pull-up transistors
approx. 10k
Port B data
Port B direction
"0" when reset
Pull-up resistance
SO
Output enable
Port E
Port C
Port B
1 pin
High level
PB7/SO1
Data bus
RD (Port B)
"1" when reset
Pull-up transistors
approx. 200k
Port B output
selection
Port B data
Output enable
SO
Internal reset signal
Port B
8
CXP841P24
1 pin
High level
Pin
When reset
Circuit format
PE5/TO/ADJ
Data bus
Port E output
selection
"0" when reset
Port E data
"1" when reset
RD (Port E)
ADJ signals are frequency division
outputs for 32kHz oscillation frequency
adjustment.ADJ2K provides usage as
buzzer output.
Port E output
selection
"00" when reset
Port E output
selection
Ouput enable
TO
ADJ16K
ADJ2K
MPX
Port E
1 pin
High level
PE4/PWM
Data bus
RD (Port E)
Port E output
selection
PWM
Port E data
"0" when reset
"1" when reset
Port E
36 pins
Hi-Z
PD0 to PD7
PF0 to PF7
PG0 to PG7
PH0 to PH7
PI4 to PI7
Data bus
RD
IP
Port data
"0" when reset
Pull-up transistors
approx. 10k
Port direction
Pull-up resistance
"0" when reset
Port D
Port F
Port G
Port H
Port I
9
CXP841P24
2 pins
Oscillation
Pin
When reset
Circuit format
EXTAL
XTAL
IP
EXTAL
XTAL
Diagram shows circuit
composition during oscillation.
Feedback resistor is removed
during stop.
IP
2 pins
Oscillation
TEX
TX
IP
TEX
Diagram shows circuit
composition during oscillation.
IP
When the operation of the oscillation
circuit is stopped by the software, the
feedback resistor is removed, and
TEX and TX become "Low" level and
"High" level respectively.
TX
1 pin
Low level
RST
Schmitt input
Pull-up resistor
Mask option
OP
IP
4 pins
Hi-Z
Data bus
RD
IP
Port I data
"0" when reset
Pull-up transistors
approx. 10k
Port I direction
Pull-up resistance
"0" when reset
INT0
INT1
INT2
INT3
Port I
PI0/INT0
to
PI3/INT3
10
CXP841P24
Input voltage
Output voltage
High level output current
High level total output current
Low level total output current
Operating temperature
Storage temperature
Allowable power dissipation
1
V
IN
and V
OUT
must not exceed V
DD
+ 0.3V.
2
The high current drive transistor is the N-ch transistor of Port C (PC).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.
V
DD
Vpp
AV
SS
V
IN
V
OUT
I
OH
I
OH
I
OL
I
OLC
I
OL
Topr
Tstg
P
D
Low level output current
Supply voltage
0.3 to +7.0
0.3 to +13.0
0.3 to +0.3
0.3 to +7.0
1
0.3 to +7.0
1
5
50
15
20
100
10 to +75
55 to +150
600
V
V
V
V
V
mA
mA
mA
mA
mA
C
C
mW
Incorporated PROM
Output per pin
Total for all output pins
Value per pin, excluding large current outputs
Value per pin
2
for large current outputs
Total for all output pins
Item
Symbol
Ratings
Unit
Remarks
Absolute Maximum Ratings
(Vss = 0V reference)
11
CXP841P24
High level input
voltage
Low level input
voltage
Operating temperature
Supply voltage
5.5
5.5
5.5
5.5
V
DD
V
DD
V
DD
+ 0.3
0.3V
DD
0.2V
DD
0.4
+75
V
V
V
V
V
V
C
V
V
Item
Symbol
Min.
Max.
Unit
Remarks
4.5
3.5
2.7
2.5
0.7V
DD
0.8V
DD
V
DD
0.4
0
0
0.3
10
V
IH
V
IHS
V
IHEX
V
IL
V
ILS
V
ILEX
Topr
High-speed mode guaranteed operation
range
1
Low-speed mode guaranteed operation
range
1
Guaranteed operation range with TEX clock
Guaranteed data hold range during stop
5
2
Hysteresis input
3
EXTAL
4
2
Hysteresis input
3
EXTAL
4
V
DD
Vpp
Recommended Operating Conditions
(Vss = 0V reference)
1
High-speed mode selects 1/2 frequency demultiplication clock; low-speed mode selects 1/16 frequency
demultiplication clock.
2
Value for each pin of normal input ports (PA, PB3, PB4, PB6, PC, PD, PF to PH, PI4 to PI7).
3
Value of the following pins: RST, CINT, CS0, SCK0, SCK1, EC0, EC1, RMC, NMI, INT0, INT1, INT2,
INT3.
4
Specifies only during external clock input.
5
Vpp and V
DD
should be set to the same voltage.
Vpp = V
DD
12
CXP841P24
V
DD
= 4.5V, I
OH
= 0.5mA
V
DD
= 4.5V, I
OH
= 1.2mA
V
DD
= 4.5V, I
OL
= 1.8mA
V
DD
= 4.5V, I
OL
= 3.6mA
V
DD
= 4.5V, I
OL
= 12.0mA
V
DD
= 5.5V, V
IH
= 5.5V
V
DD
= 5.5V, V
IL
= 0.4V
V
DD
= 5.5V, V
IH
= 5.5V
High level
output current
4.0
3.5
0.5
0.5
0.1
0.1
1.5
10
V
V
V
V
V
A
A
A
A
A
mA
A
A
PC
PA to PD,
PE4, PE5,
PF to PI
EXTAL
TEX
RST
Item
Symbol
Pins
Conditions
Min.
Clock 1MHz
0V for no-measured pins
V
DD
I
DD1
I
IL
I
IZ
I
DD2
I
DDS1
I
DDS2
I
DDS3
C
IN
V
OH
V
OL
I
IHE
I
ILE
I
IHT
I
ILT
I
ILR
Low level
output current
Input current
Typ.
0.4
0.6
1.5
40
40
10
10
400
2.0
10
Max.
Unit
DC Characteristics
Electrical Characteristics
(Ta = 10 to +75C, Vss = 0V reference)
1
Pins PA to PD, and PF to PI specify the input current when pull-up resistance has been selected; leakage
current when no resistance has been selected. (Excludes output PB7)
2
When all pins are open.
V
DD
= 5.5V, 10MHz crystal oscillation
(C
1
= C
2
= 15pF)
V
DD
= 3V, 32kHz crystal oscillation
(C
1
= C
2
= 47pF)
V
DD
= 5.5V, 10MHz crystal oscillation
(C
1
= C
2
= 15pF)
V
DD
= 3V, 32kHz crystal oscillation
(C
1
= C
2
= 47pF)
V
DD
= 5.5V,
t
ermination of 10MHz and
32kHz crystal oscillation
Power supply
current
2
Input capacity
V
DD
= 5.5V,
V
IL
= 0.4V
V
DD
= 4.5V, V
IL
= 4.0V
V
DD
= 5.5V,
V
I
= 0, 5.5V
High-speed mode operation
(1/2 frequency demultiplier clock)
Sleep mode
Stop mode
I/O leakage
current
PA to PD
1
,
PF to PI
1
PE0 to PE3
40
100
8
10
30
18
35
1.1
9
mA
A
mA
A
pF
20
10
A
Pins other
than PB7,
PE4, PE5,
AV
REF
, V
DD
,
V
SS
13
CXP841P24
EXTAL
t
XH
t
XL
t
CF
t
CR
0.4V
V
DD
0.4V
1/fc
Crystal oscillation
Ceramic oscillation
EXTAL
XTAL
External clock
EXTAL
XTAL
74HC04
C
1
C
2
32kHz clock applied condition
Crystal oscillation
TEX
TX
C
1
C
2
Fig. 2. Clock applied condition
Fig. 1. Clock timing
AC Characteristics
(1) Clock timing
(Ta = 10 to +75C, V
DD
= 4.5 to 5.5V, Vss = 0V reference)
1
t
sys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control register (address: 00FE
H
).
t
sys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
System clock frequency
System clock input pulse
width
System clock input
rise time, fall time
Event count input clock
pulse width
Event count input clock
rise time, fall time
System clock frequency
Event count input clock
input pulse width
Event count input clock
rise time, fall time
f
C
t
XL
,
t
XH
t
CR
,
t
CF
t
EH
,
t
EL
t
ER
,
t
EF
f
C
t
TL
,
t
TH
t
TR
,
t
TF
XTAL
EXTAL
EXTAL
EXTAL
EC0
EC1
EC0
EC1
TEX
TX
TEX
TEX
MHz
ns
ns
ns
ms
kHz
s
ms
Item
Symbol
Pin
Conditions
Min.
Unit
Fig. 1, Fig. 2
Fig. 1, Fig. 2
External clock drive
Fig. 1, Fig. 2
External clock drive
Fig. 3
Fig. 3
V
DD
= 2.7 to 5.5V
Fig. 2 (32kHz clock
applied condition)
Fig. 3
Fig. 3
1
37.5
t
sys + 50
1
10
Typ.
32.768
Max.
10
200
20
20
14
CXP841P24
Chip select transfer mode
(SCK0 = output mode)
Chip select transfer mode
(SCK0 = output mode)
Chip select transfer mode
Chip select transfer mode
Chip select transfer mode
(2) Serial transfer (CH0)
(Ta = 10 to +75C, V
DD
= 4.5 to 5.5V, Vss = 0V reference)
Item
CS0
SCK0
delay time
CS0
SCK0
float delay time
CS0
SO0
delay time
CS0
SO0
float delay time
CS0 High level width
SCK0 cycle time
SCK0
High and Low level widths
SI0 input setup time
(for SCK0
)
SI0 input hold time
(for SCK0
)
SCK0
SO0
delay time
t
DCSK
t
DCSKF
t
DCSO
t
DCSOF
t
WHCS
t
KCY
t
KH
t
KL
t
SIK
t
KSI
t
KSO
SCK0
SCK0
SO0
SO0
CS0
SCK0
SCK0
SI0
SI0
SO0
Input mode
Output mode
Input mode
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
ns
ns
ns
ns
ns
Symbol
Pin
Min.
t
sys + 200
t
sys + 200
t
sys + 200
t
sys + 200
t
sys + 200
2
t
sys + 200
16000/fc
t
sys + 100
8000/fc 50
100
200
t
sys + 200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
sys + 200
100
Max.
Unit
Condition
Note 1)
t
sys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (address: 00FE
H
).
t
sys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
TEX
EC0
EC1
t
EH
t
EL
t
EF
t
ER
0.2V
DD
0.8V
DD
t
TH
t
TL
t
TF
t
TR
Fig. 3. Event count clock timing
15
CXP841P24
Fig. 4. Serial transfer CH0 timing
CS0
SCK0
0.2V
DD
0.8V
DD
t
WHCS
t
DCSK
t
DCSKF
0.8V
DD
0.2V
DD
0.8V
DD
t
KCY
t
KL
t
KH
0.8V
DD
0.2V
DD
SI0
t
SIK
Input
data
t
DCSO
t
KSO
t
DCSOF
Output data
0.8V
DD
0.2V
DD
SO0
t
KSI
16
CXP841P24
Fig. 5. Serial transfer CH1 timing
SCK1
SI1
SO1
t
KCY
t
KL
t
KH
0.2V
DD
0.8V
DD
t
SIK
t
KSI
t
KSO
Input data
Output data
0.2V
DD
0.8V
DD
0.2V
DD
0.8V
DD
Serial transfer (CH1)
(Ta = 10 to +75C, V
DD
= 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Min.
Max.
Unit
Condition
t
KCY
t
KH
t
KL
t
SIK
t
KSI
t
KSO
SCK1
SCK1
SI1
SI1
SO1
Input mode
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
1000
16000/fc
400
8000/fc 50
100
200
200
100
200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
SCK1 cycle time
SCK1 High and Low level
widths
SI1 input setup time
(for SCK1
)
SI1 input hold time
(for SCK1
)
SCK1
SO1 delay time
17
CXP841P24
Fig. 6. Definition of A/D converter terms
Analog input
Linearity error
V
FT
V
ZT
00
H
01
H
FE
H
FF
H
D
i
g
i
t
a
l
c
o
n
v
e
r
s
i
o
n
v
a
l
u
e
1
V
ZT
: Value at which the digital conversion value changes
from 00
H
to 01
H
and vice versa.
2
V
FT
: Value at which the digital conversion value changes
from FE
H
to FF
H
and vice versa.
3
f
ADC
indicates the below values due to ADC operation
clock selection.
During PS2 selection, f
ADC
= fc/2
During PS1 selection, f
ADC
= fc
Conversion time
Sampling time
Reference input voltage
Analog input voltage
t
CONV
t
SAMP
V
REF
V
IAN
V
ZT
1
V
FT
2
I
REF
AV
REF
AN0 to AN7
Ta = 25C
V
DD
= 5.0V
V
SS
= AV
SS
= 0V
Operation mode
Sleep mode
Stop mode
32kHz operation mode
Linearity error
Zero transition voltage
Full-scale transition
voltage
Resolution
AV
REF
current
AV
REF
I
REFS
s
s
V
V
V
DD
AV
REF
1.0
mA
10
A
0.6
160/f
ADC
3
12/f
ADC
3
V
DD
0.5
0
Item
Symbol
Pin
Condition
Min.
Typ.
Max.
Unit
Bits
(3) A/D converter characteristics
(Ta = 10 to +75C, V
DD
= 4.5 to 5.5V, AV
REF
= 4.0 to AV
DD
, Vss = AV
SS
= 0V reference)
8
LSB
150
mV
5120
70
5050
10
4930
mV
5
18
CXP841P24
(4) Interruption, reset input
(Ta = 10 to +75C, V
DD
= 4.5 to 5.5V, Vss = 0V reference)
0.2V
DD
0.8V
DD
t
IH
t
IL
INT0
INT1
INT2
INT3
NMI
(NMI specifies only for
the falling edge.)
t
IL
t
IH
Fig 7. Interruption input timing
t
RSL
0.2V
DD
RST
External interruption
High and Low level widths
Reset input Low level width
INT0
INT1
INT2
INT3
NMI
PJ0 to PJ7
RST
1
8/fc
s
s
Item
Symbol
Pin
Condition
Min.
Max.
Unit
t
IH
t
IL
t
RSL
Fig. 8. RST input timing
19
CXP841P24
Appendix
C
1
EXTAL
XTAL
C
2
EXTAL
XTAL
(i) Main clock
EXTAL
XTAL
C
1
C
2
XTAL
(ii) Main clock
EXTAL
XTAL
C
1
C
2
Rd
TEX
TX
(iii) Sub clock
Rd
Rd
Manufacturer
MURATA
MFG
CO., LTD.
RIVER
ELETEC
CORPORATION
KINSEKI
LTD.
Model
CSA4.19MG
CSA8.00MTZ
CST4.19MGW
CST8.00MTW
HC-49/U03
HC-49/U (-S)
P3
fc (MHz)
4.19
8.00
10.00
4.19
8.00
10.00
4.19
8.00
10.00
4.19
8.00
10.00
30
39
330k
(iii)
32.768kHz
30
15
27
30
15
27
0
0
0
C
1
(pF)
C
2
(pF)
Rd (
)
Circuit
example
(i)
CSA10.0MTZ
(ii)
CST10.0MTW
(i)
Those marked with an asterisk (
) signify types with built-in ground capacitance (C
1
, C
2
).
Product List
Optional item
Package
ROM capacity
Reset pin pull-up resistor
80-pin plastic QFP
20K bytes/24K bytes
Existent/non existent
80-pin plastic QFP
PROM 24K bytes
Existent
Mask
CXP841P24Q-1-
Fig. 9. SPC700 series recommended oscillation circuit
20
CXP841P24
Package Outline
Unit: mm
PACKAGE STRUCTURE
SONY CODE
EIAJ CODE
JEDEC CODE
QFP-80P-L01
QFP080-P-1420
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
42/COPPER ALLOY
1.6g
23.9 0.4
20.0 0.1
+ 0.4
1
80
65
64
41
40
25
24
0.8
0.35 0.1
+ 0.15
1
4
.
0
0
.
1
+
0
.
4
1
7
.
9
0
.
4
1
6
.
3
0.1 0.05
+ 0.2
2.75 0.15
+ 0.35
0
.
8
0
.
2
0.15 0.05
+ 0.1
80PIN QFP (PLASTIC)
M
0.2
0.15
0 to 10
DETAIL A
A
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