Description

The CXP85324A/85332A/85340A are a highly

integrated microcomputers composed of a 8-bit
CPU, ROM, RAM, and I/O ports. These chips feature
many other high-performance circuits in a single-chip
CMOS design, including an A/D converter, serial
interface, timer/counter, time-base timer, on-screen
display function, I

C bus interface, PWM output,

remote control reception circuit, HSYNC counter,
power supply frequency counter, and watchdog
timer.

Futhermore, the CXP85324A/85332A/85340A

series provides power-on reset and sleep functions
which enable to lower power consumption.

Features
· A wide instruction set (213 instructions) which covers various types of data

16-bit operation/multiplication and division/Boolean bit operation instructions

· Minimum instruction cycle

1µs at 4MHz (4MHz version)
0.5µs at 8MHz (8MHz version)

· Incorporated ROM capacity

24K bytes (CXP85324A)
32K bytes (CXP85332A)
40K bytes (CXP85340A)

· Incorporated RAM capacity

576 bytes

· Peripheral functions

A/D converter

8-bit, 4-channel successive approximation method
(Conversion time of 40µs at 4MHz and 8MHz)

Serial interface

8-bit clock sync type, 1 channel

Timer

8-bit timer
8-bit timer/counter
19-bit time-base timer

On screen display (OSD) function

18 dots, 256 character types, 15 character colors,

12lines of 21 characters,
black frame output/half blanking, shadow, background
color on full screen/half blanking,
double scanning, jitter elimination circuit

C bus interface

PWM output

14 bits, 1 channel
8 bits, 8 channels

Remote control reception circuit

8-bit pulse measurement circuit, 6-state FIFO

HSYNC counter
Power supply frequency counter
Watchdog timer

· Interruption

14 factors, 14 vectors, multi-interruption possible

· Standby mode

SLEEP

· Package

64-pin plastic SDIP/QFP

· Piggyback/evaluator

CXP85300A 64-pin ceramic PSDIP/PQFP
CXP85390 64-pin ceramic PSDIP (accommodates custom font)

Purchase of Sony's I

C components conveys a license under the Philips I

C Patent Rights to use these components

in an I

C system, provided that the system conforms to the I

C Standard Specifications as defined by Philips.

CXP85324A/85332A/85340A

E93X37B86

CMOS 8-bit Single Chip Microcomputer

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

64 pin SDIP (PIastic)

64 pin QFP (PIastic)

Structure

Silicon gate CMOS IC

CXP85324A/85332A/85340A

I
S

I
A

I
N

I
T

I
M

/
C

I
F

I
M

/
D

I
N

I
T

I
M

I
T

/
3

/
4

I
M

t
o

C R G B

t
o

I
T

I
M

Block Diagram

CXP85324A/85332A/85340A

HSYNC/PA7

VSYNC/PA6

PA5

PA4

PA3

PA2

PA1

PA0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

EC/PD7

RMC/PD6

ACI/PD5

HSI/PD4

SI/PD3

SO/PD2

SCK/PD1

PF0/PWM0

PF1/PWM1

PF2/PWM2

PF3/PWM3

PF4/PWM4/SCL0

PF5/PWM5/SCL1

PF6/PWM6/SDA0

PF7/PWM7/SDA1

EXLC

XLC

PE0/INT0

PE1/INT1

AN0/PE2

AN1/PE3

AN2/PE4

AN3/PE5

PE6/PWM

PE7/TO

RST

EXTAL

XTAL

PD0/INT2

Pin Assignment (Top View) 64-pin SDIP

Note) 1. NC (Pin 63) is always connected to V

2. Vss (Pins 32 and 62) are both connected to GND.

3. MP (Pin 61) is always connected to GND.

CXP85324A/85332A/85340A

Note) 1. NC (Pin 56) is always connected to V

2. Vss (Pins 26 and 58) are both connected to GND.

3. MP (Pin 55) is always connected to GND.

Pin Assignment (Top View) 64-pin QFP

PA1

PA0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

EC/PD7

PF3/PWM3

PF4/PWM4/SCL0

PF5/PWM5/SCL1

PF6/PWM6/SDA0

PF7/PWM7/SDA1

EXLC

XLC

PE0/INT0

PE1/INT1

AN0/PE2

AN1/PE3

AN2/PE4

AN3/PE5

/
V

/
H

/
P

I
/
P

/
P

I
N

/
P

20 21 22 23 24 25 26 27 28 29 30 31 32

(Port A)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)

(Port B)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)

(Port C)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)

(Port D)
8-bit I/O port. I/O
can be set in a unit
of single bits.
12mA sink current
drive possible.
(8 pins)

(Port E)
8-bit port. Lower
6 bits are for inputs;
upper 2 bits are for
outputs.
(8 pins)

(Port F)
8-bit output port.
Large current
(12mA) N-ch open
drain output.
Lower 4 bits are
mid-voltage drive
(12V); upper 4 bits
are 5V drive.
(8 pins)

OSD display 6-bit output pin. (6 pins)

CXP85324A/85332A/85340A

Pin Description

Symbol

PA0 to PA5

PA6/VSYNC

PA7/HSYNC

PB0 to PB7

PC0 to PC7

PD0/INT2

PD1/SCK

PD2/SO

PD3/SI

PD4/HSI

PD5/ACI

PD6/RMC

PD7/EC

PE0/INT0
PE1/INT1

PE2/AN0

PE5/AN3

PE6/PWM

PE7/TO

PF0/PWM0

PF3/PWM3

PF4/PWM4/
SCL0
PF5/PWM5/
SCL1

PF6/PWM6/
SDA0
PF7/PWM7/
SDA1

R, G, B, I, YS, YM

I/O

I/O/Input

I/O

I/O/Input

I/O/I/O

I/O/Output

I/O/Input

Input/Input

Output/Output

Output/Output/
I/O

Output

I/O

Description

OSD display vertical synchronization signal input pin.

OSD display horizontal synchronization signal input pin.

Input pin for external interruption request.
Active when falling edge.

Serial clock I/O pin.

Serial data output pin.

Serial data input pin.

HSYNC counter input pin.

Power supply frequency counter input pin.

Remote control reception circuit input pin.

External event input pin timer/counter.

Input pin for external interruption request.
Active when falling edge.
(2 pins)

Analog input pin for A/D converter.
(4 pins)

14-bit PWM output pin.
(CMOS output)

Timer/counter rectangular wave output pin.

8-bit PWM output pin.
(8 pins)

C bus interface transfer clock I/O pin.

(2 pins)

C bus interface transfer data I/O pin.

(2 pins)

CXP85324A/85332A/85340A

Symbol

EXLC

XLC

EXTAL

XTAL

RST

Vss

Input

Output

Input

Output

I/O

Input

OSD display clock oscillation I/O pin.
Oscillation frequency is determined by the external L and C.

Crystal connection pin for system clock oscillation. When using an external
clock, input to EXTAL pin and leave XTAL pin open.

System reset pin for active at low level. This pin becomes I/O pin, and
outputs low level at the power on with power-on reset function executed.
(Mask option)

Test mode input pin. Always connect to GND.

NC. Under normal operation, connect to V

Positive supply voltage pin.

GND. Both Vss pins should be connected to common GND.

I/O

Description

CXP85324A/85332A/85340A

Data bus

RD
(Ports A, B, C)

Input protection
circuit

Ports A, B, C data

Ports A, B, C direction

"0" when reset

Data bus

RD (Port A)

Schmitt input

Port A direction

Port A data

Input multiplexer

VSYNC
HSYNC

"0" when reset

Data bus

RD (Port D)

Port D direction

Port D data

INT2, SI, HSI, ACI, RMC, EC

Schmitt input

"0" when reset

Large current 12mA

Input/Output Circuit Formats for Pins

Port A

Port B

Port C

Port A

Port D

22 pins

2 pins

6 pins

Hi-Z

When reset

Circuit format

PA0 to PA5
PB0 to PB7
PC0 to PC7

PA6/VSYNC
PA7/HSYNC

PD0/INT2
PD3/SI
PD4/HSI
PD5/ACI

PD6/RMC

PD7/EC

CXP85324A/85332A/85340A

Data bus

RD (Port D)

Port D direction

Port D data

Large current
source 12mA

Schmitt input

SCK only

SCK or SO

Output enable

"0" when reset

Large current 12mA

RD (Port E)

Data bus

Schmitt input

(Interrupt circuit)

Input multiplexer

To A/D converter

RD (Port E)

Data bus

Port E function selection

"0" when reset

TO, PWM

Port E function selection

Port E data

"1" when reset

Port D

Port E

2 pins

4 pins

2 pins

When reset

Circuit format

PE0/INT0
PE1/INT1

Port E

Hi-Z

High level

PE2/AN0

PE5/AN3

PD1/SCK
PD2/SO

PE6/PWM
PE7/TO

CXP85324A/85332A/85340A

SCL, SDA

Port F function selection

Port F data

PWM

C output enable

Schmitt input

SCL, SDA
(I

C circuit)

To internal I

C pins

BUS SW

Large current 12mA

"1" when reset

"0" when reset

PWM

Port F selection

Port F data

12V voltage drive

Large current 12mA

"1" when reset

"0" when reset

Port F

4 pins

6 pins

2 pins

When reset

Circuit format

PF4/PWM4/
SCL0
PF5/PWM5/
SCL1
PF6/PWM6/
SDA0
PF7/PWM7/
SDA1

Hi-Z

Oscillation

halted

PF0/PWM0

PF3/PWM3

EXLC
XLC

R, G, B, I, YS, YM

Writing data to output polarity
register brings output to active

Output polarity

"0" when reset

Oscillator control

EXLC

OSD display clock

XLC

CXP85324A/85332A/85340A

and V

OUT

should not exceed V

+ 0.3V.

The large current output port is Port D (PD) and Port F (PF).

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

better take place under the recommended operating conditions. Exceeding those conditions may

adversely affect the reliability of the LSI.

Supply voltage

Input voltage

Output voltage

Mid-voltage drive output voltage

High level output current

High level total output current

Low level output current

Low level total output current

Operating temperature

Storage temperature

Allowable power dissipation

OUT

OUTP

OLC

Topr

Tstg

0.3 to +7.0

0.3 to +15.0

130

20 to +75

55 to +150

1000

600

°C

PF0 to PF3 pins

Total of all output pins

Ports excluding large current
output (value per pin)

Large current output port
(value per pin)

Total of all output pins

SDIP

QFP

Item

Symbol

Ratings

Unit

Remarks

Absolute Maximum Ratings

(Vss = 0V reference)

Supply voltage

High level
input voltage

Low level
input voltage

Operating temperature

5.5

+ 0.3

0.3V

0.2V

0.4

+75

°C

Item

Symbol

Min.

Max.

Unit

Remarks

4.5

3.5

2.5

0.7V

0.8V

0.4

0.3

IHS

IHEX

ILS

ILEX

Topr

Guaranteed operation range for 1/2 and 1/4
frequency dividing modes.

Guaranteed operation range for 1/16 frequency
dividing mode or SLEEP mode.

Guaranteed data hold range for STOP mode.

EXTAL pin

This device does not enter the STOP mode.

PA, PB, PC, PE2 to PE5, SCL0, SCL1, SDA0, SDA1 pins

INT2, SCK, SI, HSI, ACI, RMC, EC, INT0, INT1, HSYNC, VSYNC, RST pins.

Specifies only during external clock input.

Recommended Operating Conditions

(Vss = 0V reference)

CXP85324A/85332A/85340A

= 4.5V, I

= 0.5mA

= 4.5V, I

= 1.2mA

= 4.5V, I

= 1.8mA

= 4.5V, I

= 3.6mA

= 4.5V, I

= 3.0mA

= 4.5V, I

= 4.0mA

= 5.5V, V

= 5.5V

= 5.5V, V

= 0.4V

= 4.5V, I

= 12.0mA

High level
output voltage

Low level
output voltage

Input current

I/O leakage current

Open drain output
leakage current
(N-ch Tr off)

C bus switch

connection impedance
(Output Tr off)

Supply current

Input capacitance

4.0

3.5

0.6

0.8

µA

120

µA

0.4

0.6

1.5

0.4

0.6

400

±10

µA

0.5

1.5

PA to PD, PE6, PE7,
R, G, B, I, YS, YM

PA to PD, PE6, PE7,
R, G, B, I, YS, YM,
PF0 to PF3, RST

PD, PF

PF4 to PF7
(SCL0, SCL1,
SDA0, SDA1)

EXTAL

RST

PA to PE, HSYNC,
VSYNC, R, G, B, I,
YS, YM, RST

PF0 to PF3

PF4 to PF7

SCL0: SCL1
SDA0: SDA1

= 5.5V, V

= 0.4V

= 5.5V,

= 0, 5.5V

= 5.5V, V

= 12.0V

= 5.5V, V

= 5.5V

= 4.5V

SCL0

= V

SCL1

= 2.25V

SDA0

= V

SDA1

= 2.25V

1/2 frequency dividing
operation mode
V

= 5.5V

4MHz, 8MHz
crystal oscillation
(C

= C

= 22pF)

STOP mode

= 5.5V

termination of 4MHz, 8MHz
crystal oscillation

SLEEP mode
V

= 5.5V

4MHz, 8MHz crystal oscillation
(C

= C

= 22pF)

PA to PD,
PE0 to PE5, SCL,
SDA, EXLC,
EXTAL, RST

1MHz clock
0V for non-measurement pins

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

LOH

DDSL

DDST

IHE

IHL

ILR

DC Characteristics

(Ta = 20 to +75°C, Vss = 0V reference)

Specifies RST pin only when the power-on reset circuit is selected with mask option.

For RST pin, specifies the input current when pull-up resistor is selected, and specifies the leakage current

when non-resistor is selected.

When all output pins open. Specifies only when the OSD oscillation is halted.

Oscillation clock 4MHz version

Oscillation clock 8MHz version

This device does not enter the stop mode.

CXP85324A/85332A/85340A

AC Characteristics

(1) Clock timing

sys indicates three values according to the contents of the clock control register (CLC: 00FE

) upper 2 bits

(CPU clock selection).

sys (ns) = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Oscillation clock 4MHz version

Oscillation clock 8MHz version

System clock frequency

System clock input
pulse width

System clock
rise and fall times

Event count input
clock pulse widtth

Event count input clock
rise and fall times

XTAL
EXTAL

EXTAL

MHz

Item

System

Condition

Min.

Max.

Unit

Fig. 1, Fig. 2

Fig. 1, Fig. 2
External clock drive

Fig 1, Fig 2
External clock drive

Fig. 3

3.5

100

sys + 50

4.5

200

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Fig. 1. Clock timing

EXTAL

0.4V

1/fc

Fig. 2. Clock applied condition

Crystal oscillation
Ceramic oscillation

EXTAL

XTAL

External clock

EXTAL

XTAL

OPEN

Fig. 3. Event count clock timing

0.2V

0.8V

CXP85324A/85332A/85340A

(2) Serial transfer

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Item

SCK cycle time

KCY

SCK

Input mode

Output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

1000

8000/fc

400

4000/fc' 50

100

200

100

200

100

SCK

SIK

KSI

KSO

SCK
high and low level widths

SI input set-up time
(for SCK

)

SI hold time
(for SCK

)

SCK

SO delay time

System

Condition

Min.

Max.

Unit

Note) The load of SCK output mode and SO output delay time is 50pF + 1TTL.

The value of fc' varies as shown below depending on the specification of oscillation clock option.

4MHz version: fc' = fc

8MHz version: fc' = fc/2

Fig. 4. Serial transfer timing

0.2V

0.8V

KCY

SIK

KSI

0.2V

0.8V

KSO

0.2V

0.8V

Output data

Input data

SCK

CXP85324A/85332A/85340A

Resolution

Linearity error

Zero transition
voltage

Full-scale transition
voltage

Conversion time

Sampling time

Analog input voltage

CONV

SAMP

IAN

AN0 to AN3

Ta = 25°C
V

= 5.0V

Vss = 0V

4910

160/fc'

12/fc'

4970

±1

5030

Bits

LSB

µs

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

(3) A/D converter characteristics

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Linearity error

Analog input

i
g

i
t
a

l

c

r
s

i
o

l
u

Fig. 5. Definitions for A/D converter terms

: Digital conversion values change between 00

: Digital conversion values change between 0E

The value of fc' varies as follows depending on the

specification of oscillation clock option.

4MHz version: fc' = fc

8MHz version: fc' = fc/2

CXP85324A/85332A/85340A

External interruption
high and low level widths

Reset input low level width

INT0 to
INT2

RST

8/fc'

µs

Item

Symbol

Condition

Min.

Max.

Unit

RSL

Power supply rise time

Power supply cutt-off time

OFF

Power-on reset

Repeated power-on reset

0.05

Item

Symbol

Condition

Min.

Max.

Unit

(4) Interruption, reset input (Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

(5) Power-on reset

Power-on reset

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

0.2V

0.8V

INT0 to INT2

(falling edge)

Specifies only when power-on reset function is selected.

0.2V

4.5V

OFF

Take care when turning on power.

Fig. 6. Interruption input timing

RSL

0.2V

RST

Fig. 7. RST input timing

Fig. 8. Power-on reset

The value of fc' varies as shown below depending on the specification of oscillation clock option.

4MHz version: fc' = fc

8MHz version: fc' = fc/2

CXP85324A/85332A/85340A

(6) I

C bus timing

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Item

SCL clock frequency

Bus-free time before starting transfer

Hold time for starting transfer

Clock low level width

Clock high level width

Set-up time for repeated transfers

Data hold time

Data set-up time

SDA, SCL rise time

SDA, SCL fall time

Set-up time for transfer completion

SLC

BUF

HD; STA

LOW

HIGH

SU; STA

HD; DAT

SU; DAT

SU; STO

SCL

SDA, SCL

SCL

SDA, SCL

4.7

4.0

4.7

4.0

4.7

250

4.7

100

300

kHz

µs

Symbol

Condition

Min.

Max.

Unit

For the data hold time, the SCL rise time (300ns Max.) is not considered so that 300ns should be exceeded.

Fig. 9. I

C bus transfer data timing

SU; STO

SU; STA

HD; STA

SU; DAT

HIGH

HD; DAT

LOW

HD; STA

BUF

SDA

SCL

Fig. 10. I

C device recommended circuit

device

SDA0
(or SDA1)

SCL0
(or SCL1)

· A pull-up resistor (Rp) must be connected to SDA0 (or SDA1), and SCL0 (or SCL1).

· The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300

or less) can be used to reduce spike

noise caused by CRT flashover.

CXP85324A/85332A/85340A

(7) OSD timing

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Item

OSD clock frequency

HSYNC pulse width

VSYNC pulse width

HSYNC afterwrite
rise and fall times

VSYNC beforewrite
rise and fall times

OSC

HWD

VWD

HCG

VCG

EXLC
XLC

HSYNC

VSYNC

HSYNC

VSYNC

Fig. 12

Fig. 11

1.2

200

1.0

MHz

µs

Symbol

Condiiton

Unit

Min.

Max.

Oscillation clock 4MHz version

Oscillation clock 8MHz version

H indicates 1HSYNC period.

Fig. 11. OSD timing

0.8V

0.2V

HCG

HWD

HSYNC

For OSD I/O polarity register

(OPOL: 01FA

)

bit 7 at "0"

0.8V

0.2V

VCG

VSYNC

For OSD I/O polarity register

(OPOL: 01FA

)

bit 6 at "0"

VWD

Fig. 12. LC oscillation circuit connection

EXLC

XLC

The series resistor for XLC is used to reduce the frequency of occurrence of the undesired radiation.

CXP85324A/85332A/85340A

Appendix

Fig. 13. SPC700 Series recommended oscillation circuit

EXTAL

XTAL

EXTAL

XTAL

(i)

EXTAL

XTAL

(ii)

Manufacturer

MURATA MFG
CO., LTD.

KINSEKI LTD.

Model

CSA4.00MG

CSA4.19MG

CSA8.00MTZ

CST4.00MGW

CST4.19MGW

CST8.00MTW

HC-49/U03

HC-49/U(-S)

fc (MHz)

4.00

4.19

8.00

4.00

4.19

8.00

4.00

4.19

8.00

4.00

4.19

8.00

(pF)

Rd (

)

Circuit

Example

(i)

(ii)

(i)

These models have the on-chip grounding capacitors (C

and C

The series resistor for XTAL can reduce the effect of the noise caused by the electrostatic discharge.

Item

Content

Reset pin pull-up resistor

Power-on reset circuit

Oscillation clock

Non-existent

4MHz

Existent

8MHz

Mask Option Table

RIVER ELETEC
CO., LTD.

CXP85324A/85332A/85340A

Fig. 14. Characteristics curves

fc System clock [MHz]

l
y

r
r
e

t

[
m

]

vs. fc (V

= 5V, Ta = 25°C, Typical)

100

I
n

t
a

[
µ

]

Parameter curve for OSD oscillator L vs. C

(Analytically calculated value)

100

, C

Capacitance [pF]

frequency
mode

1
2

frequency
mode

1
4

frequency
mode

SLEEP mode

5.0MHz

6.5MHz

13.0MHz

Supply voltage [V]

l
y

r
r
e

t

[
m

]

vs. V

(fc = 4MHz, Ta = 25°C, Typical)

frequency
mode

SLEEP mode

0.1

frequency
mode

1
4

frequency
mode

1
2

Supply voltage [V]

l
y

r
r
e

t

[
m

]

vs. V

(fc = 8MHz, Ta = 25°C, Typical)

frequency mode

SLEEP mode

0.1

frequency mode

1
4

frequency mode

1
2

OSC

= C = C

1 //

CXP85324A/85332A/85340A

Package Outline

Unit: mm

PACKAGE STRUCTURE

MOLDING COMPOUND

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

SONY CODE

EIAJ CODE

JEDEC CODE

SDIP-64P-01

42 ALLOY

SOLDER PLATING

EPOXY / PHENOL RESIN

64PIN SDIP (PLASTIC) 750mil

SDIP064-P-0750-A

57.6 0.1

+ 0.4

1.778

.
0

.
1

.
3

0° to 15°

.
5

I
N

.
7

.
1

.
4

I
N

0.5 ± 0.1

0.9 ± 0.15

8.6g

SONY CODE

EIAJ CODE

JEDEC CODE

23.9 ± 0.4

20.0 0.1

1.0

0.4 0.1

+ 0.15

.
0

.
1

0.15 0.05

+ 0.1

2.75 0.15

.
3

0.1 0.05

+ 0.2

.
8

.
2

± 0.12

0.15

+ 0.4

.
9

.
4

+ 0.35

64PIN QFP(PLASTIC)

QFP64PL01

QFP064P1420

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

EPOXY RESIN

SOLDER/PALLADIUM

COPPER /42 ALLOY

PACKAGE STRUCTURE

PLATING

1.5g

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXP85340A

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXP85340A