CXP85632/85640

E95510-PS

CMOS 8-bit Single Chip Microcomputer

Description

The CXP85632/85640 is a CMOS 8-bit micro-

computer which consists of A/D converter, serial

interface, timer/counter, time-base timer, closed

caption decoder, data slicer, on-screen display

function, I

C bus interface, PWM output, remote

control receiver, HSYNC counter and watchdog

timer as well as basic configuration like 8-bit CPU,

ROM, RAM and I/O port.

Also this IC provides power-on reset function and

sleep function which enables to lower power

consumption.

Features
· A wide instruction set (213 instructions) to cover various types of data.

-- 16-bit arithmetic/multiplication and division/boolean bit operation instructions

· Minimum instruction cycle

333ns at 12MHz operation

· Incorporated ROM

32K bytes (CXP85632)
40K bytes (CXP85640)

· Incorporated RAM

1888 bytes
(excluding the closed caption decoder and on-screen display VRAM)

· Peripheral functions

-- A/D converter

8 bits, 6 channels, successive approximation method
(Conversion time of 26.7µs/12MHz)

-- Serial interface

8-bit clock, sync type, 1 channel

-- Timer

8-bit timer, 8-bit timer/counter, 19-bit time-base timer

-- Closed caption decoder

Incorporated decode slicer,
conforming to FCC, 8

13 dots, 192 character types, 15 character colors,

4 lines of 34 characters, italic, underline, vertical scroll,
15 frame background colors/half blanking

-- On-screen display (OSD) function

16 dots, 128 character types, 15 character colors, 4 lines of 24 characters,

8 frame background colors/half blanking, edging per line (half dot), vertical scroll
jitter elimination circuit

-- I

C bus interface

-- PWM output

8 bits, 4 channels

-- Remote control receiver circuit

Incorporated 6-stage FIFO 8-bit pulse measurement counter

-- HSYNC counter

2 channels

-- Watchdog timer

· Interruption

15 factors, 15 vectors, multi-interruption possible

· Standby mode

SLEEP

· Package

64-pin plastic SDIP/QFP

· Piggyback/evaluation chip

CXP85690 64-pin ceramic PSDIP (accommodates custom font)

Purchase of Sony's I

C components conveys a license under the Philips I

C Patent Rights to use these components

in an I

C system, provided that the system conform to the I

C Standard Specifications as defined by Philips.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

64 pin SDIP (PIastic)

64 pin QFP (PIastic)

Structure

Silicon gate CMOS IC

For the availability of this product, please contact the sales office.

CXP85632/85640

VIN

XLC

EXLC

HSYNC

VSYNC

SCK

RMC

HSC0

HSC1

AN0 to AN5

CVss

Cap

Rex

DATA SLICER

CC DECODER

ON SCREEN DISPLAY

SERIAL INTERFACE UNIT

8BIT TIMER/COUNTER 0

REMOCON

HSYNC COUNTER 0

HSYNC COUNTER 1

A/D CONVERTER 6CH

FIFO

INT2
INT1

INT0

SCL1

SCL0

SDA1

SDA0

C BUS

INTERFACE UNIT

8BIT PWM 4CH

WATCHDOG TIMER

PRESCALER/

TIME BASE TIMER

SPC700 CPU CORE

ROM

32K/40K BYTES

CLOCK GENERATOR/

SYSTEM CONTROL

RAM

1888 BYTES

Vss

RST

XTAL

EXTAL

PWM0 to PWM3

PA0 to PA7

PB0 to PB7

PC0 to PC7

PD0 to PD7

PE0 to PE2

PF0 to PF7

INTERRUPT CONTROLLER

PORT A

PORT B

PORT C

PORT D

PORT E

PORT F

8BIT TIMER 1

Block Diagram

CXP85632/85640

Pin Assignment (Top View) 64-pin SDIP

PC3

PC2

PC1

PC0

EC/PD7

RMC/PD6

HS1/PD5

HS0/PD4

SI/PD3

SO/PD2

SCK/PD1

INT2/PD0

HSYNC/PA7

VSYNC/PA6

RST

Vss

XTAL

EXTAL

PA5/AN5

PA4/AN4

PA3/AN3

PA2/AN2

PA1/AN1

PA0/AN0

CVss

Cap

Rex

VIN

INT1/PB7

PB6

PB5

PC4

PC5

PC6

PC7

PF0/PWM0

PF1/PWM1

PF2/PWM2

PF3/PWM3

PF4/SCL0

PF5/SCL1

PF6/SDA0

PF7/SDA1

PE0/TO

PE1

PE2/INT0

Vss

EXLC

XLC

PB0

PB1

PB2

PB3

PB4

Note) 1. NC (Pin 46) must be connected to V

2. Vss (Pins 16 and 48) must be connected to GND.

3. MP (Pin 49) must be connected to GND.

4. Cap (Pin 26) must be connected to CV

via a capacitor.

5. Rex (Pin 27) must be connected to CV

via a resistor of 33k

CXP85632/85640

Pin Assignment (Top View) 64-pin QFP

HS1/PD5

HS0/PD4

SI/PD3

S0/PD2

SCK/PD1

INT2/PD0

HSYNC/PA7

VSYNC/PA6

RST

Vss

XTAL

EXTAL

PA5/AN5

PA4/AN4

PA3/AN3

PA2/AN2

PA1/AN1

PA0/AN0

CVss

PF3/PWM3

PF4/SCL0

PF5/SCL1

PF6/SDA0

PF7/SDA1

PE0/TO

PE1

PE2/INT0

Vss

EXLC

XLC

PD6/RMC

PD7/EC

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PF0/PWM0

PF1/PWM1

PF2/PWM2

Cap

Rex

VIN

INT1/PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

20 21 22 23 24 25 26 27 28 29 30 31 32

Note) 1. NC (Pin 40) must be connected to V

2. Vss (Pins 10 and 42) must be connected to GND.

3. MP (Pin 43) must be connected to GND.

4. Cap (Pin 20 ) must be connected to CV

via a capacitor.

5. Rex (Pin 21) must be connected to CV

via a resistor of 33k

CXP85632/85640

Pin Functions

Pin name

PA0/AN0

PA5/AN5

PA6/VSYNC

PA7/HSYNC

PB0 to PB6

PB7/INT1

PC0 to PC7

PD0/INT2

PD1/SCK

PD2/SO

PD3/SI

PD4/HS0

PD5/HS1

PD6/RMC

PD7/EC

PE0/TO

PE1

PE2/INT0

PF0/PWM0

PF3/PWM3

PF4/SCL0
PF5/SCL1

PF6/SDA0
PF7/SDA1

R, G, B, I, YS, YM

I/O/Analog input

I/O/Input

I/O

I/O/Input

I/O

I/O/Input

I/O/I/O

I/O/Output

I/O/Input

I/O/Output

I/O

I/O/Input

Output/Output

Output/I/O

Output

I/O

Functions

Analog inputs to A/D converter. (6 pins)

OSD display vertical sync signal input.

OSD display horizontal sync signal input.

Input for external interruption request. Active at
the falling edge.

Serial clock I/O.

Serial data output.

Serial data input.

HSYNC counter (CH0) input.

HSYNC counter (CH1) input.

Remote control receiver circuit input.

External event input for timer/counter.

Rectangular wave output for timer/counter.

Input for external interruption request.
Active at the falling edge.

8-bit PWM outputs.
(4 pins)

Transfer clock I/O for I

C bus interface. (2 pins)

Transfer data I/O for I

C bus interface. (2 pins)

(Port A)
8-bit I/O port. I/O
can be set in a unit
of single bits.
(8 pins)

(Port B)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)

(Port C)
8-bit I/O port. I/O can be set in a unit of single bits. (8 pins)

(Port D)
8-bit I/O port. I/O
can be set in a unit
of single bits.
Capable of driving
12mA sync current.
(8 pins)

(Port E)
3-bit I/O port. I/O
can be set in a unit
of single bits.
(3 pins)

(Port F)
8-bit output port
with large current
(12mA) N-ch open
drain output.
Lower 4 bits are
12V drive and upper
4 bits are 5V drive.

OSD display 6-bit outputs. (6 pins)

CXP85632/85640

Pin name

EXLC

XLC

VIN

Cap

Rex

EXTAL

XTAL

RST

Vss

Input

Output

Input

Output

I/O

Input

OSD display clock oscillation I/O.
Oscillator frequency is determined by external L and C.

Input of external composite video signal. Input a 2Vp-p signal via a
capacitor.

Capacitor connection for the data slicer. Connect a capacitor between
Cap and CV

Resistor connection for the data slicer. Connect a 33k

resistor

between Rex and CV

Positive power supply for data slicer.

GND for data slicer.

System clock oscillator crystal connection. When using an external
clock, input to EXTAL pin and leave XTAL pin open.

Low level active system reset. This pin acts as I/O pin and outputs low
level through incorporated power-on reset function when the power
turned on. (Mask option)

Test mode input. Must be connected to GND.

Not connected.
Under normal conditions, connect to V

Positive power supply.

GND. Connect two V

pins to GND.

I/O

Functions

CXP85632/85640

I/O Circuit Format for Pins

Data bus

Port A data

Port A direction

RD (Port A)

VSYNC, HSYNC

Input polarity

Schmitt input

"0" when reset

Port A data

Port A direction

Data bus

RD (Port A)

Port A function selection

"0" when reset

A/D converter

Input multiplexer

"0" when reset

Input
protection
circuit

Port B, C data

Port B, C direction

Data bus

RD (Port B, C)

INT1

"0" when reset

Schmitt input

Port A

Port B

Port C

2 pins

6 pins

16 pins

Hi-Z

When reset

Circuit format

PA0/AN0

PA5/AN5

PB0 to PB6
PB7/INT1
PC0 to PC7

PA6/VSYNC
PA7/HSYNC

CXP85632/85640

Port D data

Port D direction

Data bus

RD (Port D)

INT2, SI, HS0, HS1, RMC, EC

Large current 12mA

Schmitt input

"0" when reset

Port D data

Port D direction

Data bus

RD (Port D)

SCK only

Large current 12mA

SCK, SO

Serial output enable

Schmitt input

"0" when reset

Port E function selection

Port E direction

Port E data

Data bus

INT0

Schmitt input
only for PE2

RD (Port E)

"1" when reset

"1" when reset for PE0, 1

"1" when reset for PE0, 1
"0" when reset for PE2

Port D

Port E

6 pins

2 pins

3 pins

Hi-Z

PE0, PE1:

High

PE2: Hi-Z

When reset

Circuit format

PD1/SCK
PD2/SO

PE0/TO
PE1
PE2/INT0

PD0/INT2
PD3/SI
PD4/HS0
PD5/HS1
PD6/RMC
PD7/EC

CXP85632/85640

SCL, SDA

Port F data

Large current 12mA

C output enable

Schmitt input

SCL, SDA
(I

C circuit)

To internal I

C pins

(To SCL1 for SCL0)

BUS SW

"1" when reset

Port F selection

Port F data

PWM0 to PWM3

Large current 12mA

12V drive voltage

"0" when reset

"1" when reset

Port F

4 pins

6 pins

2 pins

When reset

Circuit format

PF4/SCL0
PF5/SCL1
PF6/SDA0
PF7/SDA1

Hi-Z

Oscillation

halted

PF0/PWM0

PF3/PWM3

EXLC
XLC

R, G, B, I, YS, YM

Output becomes active
by data writing to output
polarity register.

Output polarity

"0" when reset

Oscillator control

EXLC

OSD display clock

XLC

CXP85632/85640

and V

OUT

should not exceed V

+ 0.3V.

The large current output port is Port D (PD) and Port F (PF).

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.

Supply voltage

Input voltage

Output voltage

Medium voltage tolerance output voltage

High level output current

High level total output current

Low level output current

Low level total output current

Operating temperature

Storage temperature

Allowable power dissipation

OUT

OUTP

OLC

Topr

Tstg

0.3 to +7.0

0.3 to +15.0

100

20 to +75

55 to +150

1000

600

°C

PF0 to PF3 pins

Total of all output pins

Excludes large current output
port (value per pin)

Large current output port
(value per pin

)

Total of all output pins

SDIP

QFP

Item

Symbol

Ratings

Unit

Remarks

Absolute Maximum Ratings

(Vss = 0V reference)

5.5

+ 0.3

0.3V

0.2V

0.4

+75

°C

Item

Symbol

Min.

Max.

Unit

Remarks

4.5

3.5

2.5

4.5

0.7V

0.8V

0.4

0.3

This device does not enter in the STOP mode.

PA, PB, PC, PE0, PE1, SCL0, SCL1, SDA0, SDA1 pins.

INT2, SCK, SO, SI, HS0, HS1, RMC, EC, INT1, HSYNC, VSYNC, RST pins.

Specifies only during external clock input.

and V

should be set to the same voltage.

Recommended Operating Conditions

(Vss = 0V reference)

Supply voltage

Data slicer supply
voltage

High level
input voltage

Low level
input voltage

Operating temperature

IHS

IHEX

ILS

ILEX

Topr

Guaranteed operation range for 1/2 or 1/4
frequency dividing mode

Guaranteed operation range for 1/16
frequency dividing or SLEEP mode

Guaranteed data hold range for STOP mode

EXTAL pin

CXP85632/85640

= 4.5V, I

= 0.5mA

= 4.5V, I

= 1.2mA

= 4.5V, I

= 1.8mA

= 4.5V, I

= 3.6mA

= 4.5V, I

= 3.0mA

= 4.5V, I

= 4.0mA

= 5.5V, V

= 5.5V

= 5.5V, V

= 0.4V

= 4.5V, I

= 12.0mA

High level
output voltage

Low level
output voltage

Input current

I/O leakage current

Open drain output
leak current
(N-ch Tr off case)

C bus switch

connection impedance
(Output Tr off case)

Supply current

Input capacitance

4.0

3.5

0.9

5.0

10.0

µA

120

µA

0.4

0.6

1.5

0.4

0.6

400

±10

µA

0.5

1.5

PA to PD, PE, R, G,
B, I, YS, YM

PA to PD, PE, R, G,
B, I, YS, YM,
PF0 to PF3, RST

PD, PF

PF4 to PF7
(SCL0, SCL1,
SDA0, SDA1)

EXTAL

RST

PA to PE, HSYNC,
VSYNC, R, G, B, I,
YS, YM, RST

PF0 to PF3

PF4 to PF7

SCL0: SCL1
SDA0: SDA1

= 5.5V, V

= 0.4V

= 5.5V,

= 0, 5.5V

= 5.5V, V

= 12.0V

= 5.5V, V

= 5.5V

= 4.5V

SCL0

= V

SCL1

= 2.25V

SDA0

= V

SDA1

= 2.25V

STOP mode

= 5.5V,

termination of 12MHz
oscillation

= 5.5V

SLEEP mode
V

= 5.5V,

12MHz crystal oscillation
(C

= C

= 15pF)

PA to PE, SCL, SDA,
EXLC, EXTAL, VIN,
RST

1MHz clock
0V for all pins excluding
measured pins

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

LOH

DDSL

DDST

CVDD

IHE

IHL

ILR

DC Characteristics

(Ta = 20 to +75°C, Vss = 0V reference)

RST pin is specified only when the power-on reset circuit is selected with mask option.

In RST pin, the input current is specified when the pull-up resistor is selected; the leakage current when no
resistor is selected.

When all pins are open. Specifies only when the OSD oscillation stops.

This device does not enter in the STOP mode.

1/2 frequency dividing mode
V

= 5.5V

12MHz crystal oscillation
(C

= C

= 15pF)

CXP85632/85640

AC Characteristics

(1) Clock timing

sys indicates three values according to the contents of the clock control register (CLC: 00FE

) upper

2 bits. (CPU clock selection)

sys (ns) = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

System clock frequency

System clock input
pulse width

System clock
rise and fall times

Event counter input
clock pulse widtth

Event counter input clock
rise and fall times

XTAL
EXTAL

EXTAL

MHz

Item

System

Condition

Min.

Max.

Unit

Fig. 1, Fig. 2

Fig. 1, Fig. 2
External clock drive

Fig 1, Fig 2
External clock drive

Fig. 3

37.5

sys

+ 50

Typ.

12.0

200

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Fig. 1. Clock timing

EXTAL

0.4V

1/fc

Fig. 2. Clock applied condition

Crystal oscillator
Ceramic oscillator

EXTAL

XTAL

External clock

EXTAL

XTAL

OPEN

Fig. 3. Event count clock timing

0.2V

0.8V

CXP85632/85640

(2) Serial transfer

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Item

SCK cycle time

KCY

SCK

Input mode

Output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

1000

8000/fc

400

4000/fc 50

100

200

100

200

100

SCK

SIK

KSI

KSO

SCK
high and low level widths

SI input set-up time
(for SCK

)

SI input hold time
(for SCK

)

SCK

SO delay time

System

Condition

Min.

Max.

Unit

Note) The load condition for the SCK output mode, SO output delay time is 50pF + 1TTL.

Fig. 4. Serial transfer timing

0.2V

0.8V

KCY

SIK

KSI

0.2V

0.8V

KSO

0.2V

0.8V

Output data

Input data

SCK

CXP85632/85640

Resolution

Linearity error

Zero transition
voltage

Full-scale transition
voltage

Conversion time

Sampling time

Analog input voltage

CONV

SAMP

IAN

AN0 to AN5

Ta = 25°C
V

= 5.0V

Vss = 0V

4910

160/f

ADC

12/f

ADC

4970

±1

5030

Bits

LSB

µs

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

(3) A/D converter characteristics

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Linearity error

Analog input

Digital conversion value

Fig. 5. Definitions for A/D converter terms

: Digital conversion values change between 00

: Digital conversion values change between 0E

ADC

indicates the below values due to the bit 6 (CKS) of

A/D control registor (ADC: 00F9

) and the bit 7 (PCK1) and

bit 6 (PCK0) of clock control registor (CLC: 00FE

)

00 (

= f

/2)

01 (

= f

/4)

11 (

= f

/16)

ADC

= f

ADC

= f

ADC

= f

/16

ADC

= f

CKS

PCK1, 0

0 (

/2 selection)

1 (

selection)

ADC

= f

ADC

= f

CXP85632/85640

External interrupt
high and low level widths

Reset input low level width

INT0
INT1
INT2

RST

32/fc

µs

Item

Symbol

Condition

Min.

Max.

Unit

RSL

Power supply rise time

Power supply cutt-off time

OFF

Power-on reset

Repeated power-on reset

0.05

Item

Symbol

Condition

Min.

Max.

Unit

(4) Interrupt, reset input

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

(5) Power-on reset

(Ta = 20 to +75°C, Vss = 0V reference)

0.2V

0.8V

INT0

INT1

INT2

(falling edge)

Specified only when power-on reset function is selected.

0.2V

4.5V

OFF

Take care when turning on power.

Fig. 6. Interrupt input timing

RSL

0.2V

RST

Fig. 7. RST input timing

Fig. 8. Power-on reset

CXP85632/85640

(6) I2C bus timing

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Item

SCL clock frequency

Bus-free time before starting transfer

Hold time for starting transfer

Clock low level width

Clock high level width

Set-up time for repeated transfers

Data hold time

Data set-up time

SDA, SCL rise time

SDA, SCL fall time

Set-up time for transfer completion

SLC

BUF

HD; STA

LOW

HIGH

SU; STA

HD; DAT

SU; DAT

SU; STO

SCL

SDA, SCL

SCL

SDA, SCL

4.7

4.0

4.7

4.0

4.7

250

4.7

100

300

kHz

µs

Symbol

Condition

Min.

Max.

Unit

For data hold time, the SCL rise time is not taken into account so that 300ns must be exceeded.

Fig. 9. I

C bus transfer data timing

SU; STO

SU; STA

HD; STA

SU; DAT

HIGH

HD; DAT

LOW

HD; STA

BUF

SDA

SCL

Fig. 10. I

C device recommended circuit

device

SDA0
(or SDA1)

SCL0
(or SCL1)

· A pull-up resistor must be connected to SDA0 (or SDA1), and SCL0 (or SCL1).

· The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300

or less) can be used to reduce spike

noise caused by CRT flashover.

CXP85632/85640

(7) OSD (On Screen Display) timing

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Item

OSD clock frequency

HSYNC pulse width

HSYNC after-write
rise and fall times

VSYNC before-write
rise and fall times

OSC

HWD

HCG

VCG

EXLC
XLC

HSYNC

VSYNC

Fig. 12

Fig. 11

1.2

16.5

200

1.0

MHz

µs

Symbol

Condiiton

Unit

Min.

Max.

Fig. 11. OSD timing

0.8V

0.2V

HCG

HWD

HSYNC

For OPOL register (01FD

)

bit 7 at "0"

0.8V

0.2V

VCG

VSYNC

For OPOL register (01FD

)

bit 6 at "0"

Fig. 12. LC oscillator circuit connection

EXLC

XLC

The XLC series resistor can reduce the occurrence of undersired radiation.

CXP85632/85640

(8) Data slicer external circuit

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V reference)

Item

VIN pin coupling capacitor

Cap pin capacitor

Rex pin pull-up resistor

Composite video signal input

VIN

Ccap

Rrex

Video In

VIN

Cap

Rex

VIN

0.47

4700

2.0

µF

Vp-p

Symbol

Min.

Unit

Typ.

Max.

Fig. 13. Data slicer external recommeded circuit

B or more of temperature
characteristics is
recommended.

Remarks

Rex

Cap

CVss

Ccap

Video In

VIN

Rrex

5.0V

[Recommended Constant]

= 100

(error: 5%; allowable power dissipation: 1/8 W or more)

= 1M

(error: 5%; allowable power dissipation: 1/8 W or more)

= 820pF (ceramic), B or more of temperature characteristics is recommended.

CXP85632/85640

Fig. 15. Characteristics curves

Supply current [mA]

vs. V

(fc = 12MHz, Ta = 25°C, Typical)

Supply voltage [V]

0.1

100

vs. fc

frequency
dividing mode

SLEEP mode

frequency
dividing mode

1
4

frequency
dividing mode

1
2

SLEEP mode

frequency
dividing mode

1
4

frequency
dividing mode

1
2

Supply current [mA]

System clock [MHz]

Parameter curve for OSD oscillation L vs. C

(theoretically calculated value)

10MHz

12MHz

14MHz

100

Inductance [µ

100

, C

Capacitance [pF]

OSC

= C = C

1 //

= 5V, Ta = 25°C, Typical)

16MHz

CXP85632/85640

Package Outline

Unit: mm

PACKAGE STRUCTURE

MOLDING COMPOUND

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

SONY CODE

EIAJ CODE

JEDEC CODE

SDIP-64P-01

42 ALLOY

SOLDER PLATING

EPOXY / PHENOL RESIN

64PIN SDIP (PLASTIC) 750mil

SDIP064-P-0750-A

57.6 0.1

+ 0.4

1.778

19.05

17.1 0.1

+ 0.3

0° to 15°

0.25 0.05

+ 0.1

0.5 MIN

4.75 0.1

+ 0.4

3 MIN

0.5 ± 0.1

0.9 ± 0.15

8.6g

SONY CODE

EIAJ CODE

JEDEC CODE

23.9 ± 0.4

20.0 0.1

1.0

0.4 0.1

+ 0.15

14.

0.15 0.05

+ 0.1

2.75 0.15

16.

0.1 0.05

+ 0.2

8 ±

± 0.12

0.15

+ 0.4

17.9 ±

0.4

+ 0.35

64PIN QFP(PLASTIC)

QFP64PL01

QFP064P1420

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

EPOXY RESIN

SOLDER/PALLADIUM

COPPER /42 ALLOY

PACKAGE STRUCTURE

PLATING

1.5g

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXP85632

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXP85632