Description

The CXP87352/87360 is a CMOS 8-bit micro-

computer which consists of A/D converter, serial
interface, timer/counter, time base timer, vector
interruption, high precision timing pattern generation
circuit, PWM generator, PWM for tuner, VISS/VASS
circuit, 32kHz timer/event counter, remote control
receiving circuit, general purpose prescaler, HSYNC
counter, VCR vertical sync separation circuit and the
measurement circuit which measure signals of
capstan FG and drum FG/PG and other servo
systems, as well as basic configurations like 8-bit
CPU, ROM, RAM and I/O port. They are integrated
into a single chip.

Also the CXP87352/87360 provides sleep/stop

function which enables to lower power consumption
and ultra-low speed instruction mode in 32kHz
operation.

Features
· A wide instruction set (213 instructions) which cover various types of data

-- 16-bit operation/multiplication and division/boolean bit operation instructions

· Minimum instruction cycle

250ns at 16MHz operation
333ns at 12MHz operation
122µs at 32kHz operation

· Incorporated ROM capacity

52K bytes (CXP87352), 60K bytes (CXP87360)

· Incorporated RAM capacity

2048 bytes

· Peripheral functions

-- A/D converter

8-bit, 12-channel, successive approximation system
(Conversion time 20.0µs/16MHz)

-- Serial Interface

Incorporated buffer RAM (1 to 32 bytes auto transfer) 1-channel
Incorporated 8-bit and 8-stage FIFO for data
(1 to 8 bytes auto transfer) 1-channel

-- Timer

8-bit timer, 8-bit timer/counter, 19-bit time base timer,
32kHz timer/counter

-- High precision timing pattern generator

PPG 19-pin 32-stage programmable

RTG 5-pin 2-channel

-- PWM/DA gate output

PWM 12-bit, 2-channel (Repetitive frequency 62kHz/16MHz)
DA gate pulse output 13-bit, 4-channel

-- Servo input control

Capstan FG, Drum FG/PG, CTL input

-- VSYNC separator
-- FRC capture unit

Incorporated 26-bit and 8-stage FIFO

-- PWM output

14-bit, 1-channel

-- VISS/VASS circuit

Pulse duty auto detection circuit

-- Remote control receiving circuit

8-bit pulse measurement counter with on-chip, 6-stage FIFO

-- General purpose prescaler

7-bit (SYNC1 input frequency divided, FRC capture possible)

-- HSYNC counter

12-bit event counter (Counts SYNC1 input.)

· Interruption

22 factors, 15 vectors, multi-interruption possible

· Standby mode

SLEEP/STOP

· Package

100-pin plastic QFP/LQFP

· Piggyback/evaluation chip

CXP87300 100-pin ceramic QFP/LQFP

CXP87352/87360

E94415A16-PS

CMOS 8-bit Single Chip Microcomputer

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

100 pin QFP (PIastic)

100 pin LQFP (PIastic)

Structure

Silicon gate CMOS IC

CXP87352/87360

PI6/SO1

PA0 to PA7

PB0 to PB7

PC0 to PC7

PD0 to PD7

PE0 to PE1

PE2 to PE7

PF0 to PF3

PF4 to PF7

PG0 to PG7

PI1 to PI7

PJ0 to PJ7

Vss

RST

XTAL

EXTAL

CLOCK

GENERATOR/

SYSTEM CONTROL

RAM

2048 BYTES

SPC700

CPU CORE

ROM

52K/60K BYTES

INTERRUPT CONTROLLER

32kHz

TIMER/COUNTER

FIFO

FRC

CAPTURE UNIT

PROGRAMMABLE

PATTERN

GENERATOR

RAM

AVss

REF

A/D CONVERTER

SERIAL

INTERFACE UNIT

(CH0)

RAM

8 BIT TIMER/COUNTER 0

8 BIT TIMER 1

VSYNC SEPARATOR

14 BIT PWM GENERATOR

12 BIT PWM GENERATOR CH0

SERVO INPUT

CONTROL

CAPSTAN

DRUM

CTL

12 BIT PWM GENERATOR CH1

PE7/DAB1

PE5/DAA1

PE3/PWM1

PE6/DAB0

PE4/DAA0

PE2/PWM0

PI2/PWM

PI1/RMC

PG3/PBCTL

PG2/DPG

PG1/DFG

PG0/CFG

PG7/EXI1

PG6/EXI0

PG5/SYNC1

PG4/SYNC0

PI3/TO/DDO

PE1/EC

PI5/SCK1

PI7/SI1

SCK0

SO0

SI0

CS0

PF0/AN4

PF7/AN11

AN0 to AN3

REALTIME

PULSE

GENERATOR

PE1/INT2

PE0/INT0

PI4/INT1/NMI

PH0 to PH7

TEX

NMI

PRESCALER/

TIME BASE TIMER

VISS/VASS

REMOCON INPUT

FIFO

SERIAL

INTERFACE UNIT

(CH1)

CH0

CH1

PA0/PPO0

PC2/PPO18

PC3/RTO3

PC7/RTO7

FIFO

PE0/CKOUT

PROGRAMMABLE PRESCALER

HSYNC COUNTER

PE1/HCOUT

PI3/ADJ

PORT A

PORT B

PORT C

PORT D

PORT E

PORT F

PORT G

PORT H

PORT I

PORT J

Block Diagram

CXP87352/87360

Pin Configuration 1 (Top View) 100-pin QFP package

PI6/SO1

PI7/SI1

PE0/INT0/XOUT

PE1/EC/INT2

PE2/PWM0

PE3/PWM1

PE4/DAA0

PE5/DAA1

PE6/DAB0

PE7/DAB1

PG0/CFG

PG1/DFG

PF2/DPG

PG3/PBCTL

PG4/SYNC0/PMI

PG5/SYNC1

PG6/EXI0

PG7/EXI1/PMSK

AN0

AN1

AN2

AN3

PF0/AN4

PF1/AN5

PF2/AN6

PF3/AN7

REF

PF4/AN8

PB3/PPO011

PB2/PPO010

PB1/PPO009

PB0/PPO008

PC7/RTO7

PC6/RTO6

PC5/RTO5

PC4/RTO4

PC3/RTO3

PC2/PPO018

PC1/PPO017

PC0/PPO016

PJ7

PJ6

PJ5

PJ4

PJ3

PJ2

PJ1

PJ0

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PB6/PPO014

PB7/PPO015

PA0/PPO000/PPO100

PA1/PPO001/PPO101

PA2/PPO002/PPO102

PA3/PPO003/PPO103

PA4/PPO004/PPO104

PA5/PPO005/PPO105

PA6/PPO006/PPO106

PA7/PPO007/PPO107

Vpp

PK0/OSCO

PI0/PCK/OSCI

PI1/PO

PI2/PWM

PI3/TO

PI4/INT1

PI5/SCK1

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

RST

XTAL

EXTAL

CS0

SI0

SO0

SCK0

PF7/AN11

PF6/AN10

PF5/AN9

Mask

option

32 33

41 42 43 44 45 46 47 48 49 50

88 87 86 85

100 99 98 97 96 95 94

PB5/PPO013/PPO113

PB4/PPO012/PPO112

Note) 1. NC (Pin 90) is always connected to V

2. Vss (Pins 41 and 88) are both connected to GND.

CXP87352/87360

Pin Configuration 2 (Top View) 100-pin LQFP package

PB3/PPO11

PB2/PPO10

PB1/PPO9

PB0/PPO8

PC7/RTO7

PC6/RTO6

PC5/RTO5

PC4/RTO4

PC3/RTO3

PC2/PPO18

PC1/PPO17

PC0/PPO16

PJ7

PJ6

PJ5

PJ4

PJ3

PJ2

PJ1

PJ0

PD7

PD6

PD5

PD4

PD3

PE1/EC/INT2/HCOUT

PE2/PWM0

PE3/PWM1

PE4/DAA0

PE5/DAA1

PE6/DAB0

PE7/DAB1

PG0/CFG

PG1/DFG

PG2/DPG

PG3/PBCTL

PG4/SYNC0

PG5/SYNC1

PG6/EXI0

PG7/EXI1

AN0

AN1

AN2

AN3

PF0/AN4

PF1/AN5

PF2/AN6

PF3/AN7

REF

PB4/PPO12

PB5/PPO13

PB6/PPO14

PB7/PPO15

PA0/PPO0

PA1/PPO1

PA2/PPO2

PA3/PPO3

PA4/PPO4

PA5/PPO5

PA6/PPO6

PA7/PPO7

TEX

PI1/RMC

PI2/PWM

PI3/TO/DDO/ADJ

PI4/INT1/NMI

PI5/SCK1

PI6/SO1

PI7/SI1

PE0/INT0/CKOUT

PD2

PD1

PD0

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

RST

XTAL

EXTAL

CS0

SI0

SO0

SCK0

PF7/AN11

PF6/AN10

PF5/AN9

PF4/AN8

26 27 28 29 30

31 32 33

41 42 43 44 45 46 47 48 49 50

88 87 86 85

100 99 98 97 96 95 94

Note) 1. NC (Pin 88) is always connected to V

2. Vss (Pins 39 and 86) are both connected to GND.

CXP87352/87360

Output/
Real time
output

I/O/
Real time
output

I/O

Input/Input/Output

Input/Input/Input/
Output

Output/Output

Input

Input/Input

Output/Input

I/O

Ouput

Input

(Port A)
8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)

(Port B)
8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)

(Port C)
8-bit I/O port, enables to
specify I/O by bit unit.
Data is gated with PPO or
RTO contents by OR-gate
and they are output.
(8 pins)

(Port D)
8-bit I/O port. Enable to specify I/O by 4-bit unit.
Enables to drive 12mA sink current.
(8 pins)

(Port E)
8-bit port.
Lower 2 bits
are input pins
and upper 6
bits are output
pins.
(8 pins)

Analog input pins to A/D converter. (12 pins)

(Port F)
Lower 4 bits are input port and upper 4 bits are output port.
Lower 4 bits also serve as standby release input pin.
(8 pins)

Serial clock (CH0) I/O pin.

Serial data (CH0) output pin.

Serial data (CH0) input pin.

Serial chip select (CH0) input pin.

External event
input pin for
timer/counter.

Input pin to request
external interruption.
Active when falling edge.

Input pin to request external interruption.
Active when falling edge.

PC3 can be 3-state controlled with RTG.
System clock frequency division output.

PWM output pins.
(2 pins)

DA gate pulse output pins.
(4 pins)

Programmable pattern generator (PPG)
output.
Functions as high precision real time
pulse output port.
(19 pins)
PB0 and PB2 can be 3-state controlled
with PPG.

Real time pulse generator (RTG) output.
Functions as high precision real time
pulse output port. (5 pins)

Symbol

I/O

Description

PA0/PPO0

PA7/PPO7

PB0/PPO8

PB7/PPO15

PC0/PPO16

PC2/PPO18

PC3/RTO3

PC7/RTO7

PD0 to PD7

PE0/INT0/
CKOUT

PE1/EC/INT2/
HCOUT

PE2/PWM0

PE3/PWM1

PE4/DAA0

PE5/DAA1

PE6/DAB0

PE7/DAB1

AN0 to AN3

PF0/AN4

PF3/AN7

PF4/AN8

PF7/AN11

SCK0

SO0

SI0

CS0

Pin Description

Coinsidence
signal output of
HSYNC counter.

CXP87352/87360

PG0/CFG

PG1/DFG

PG2/DPG

PG3/PBCTL

PG4/SYNC0

PG5/SYNC1

PG6/EXI0

PG7/EXI1

PH0 to PH7

PI1/RMC

PI2/PWM

PI3/TO/
DDO/ADJ

PI4/INT1/
NMI

PI5/SCK1

PI6/SO1

PI7/SI1

PJ0 to PJ7

EXTAL

XTAL

TEX

RST

REF

AVss

Vss

Input/Input

Output

I/O/Input

I/O/Output

I/O/Output/
Output/Output

I/O/Input/Input

I/O/I/O

I/O/Output

I/O/Input

I/O

Input

Output

Input

Output

Input

Composite sync signal input pin.

External input pin to FRC capture unit.

(Port G)
8-bit input port.
(8 pins)

(Port H)
8-bit output port ; Medium withstand voltage (12V) and high current
(12mA), N-ch open drain output.
(8 pins)

Remote control receiving circuit input pin.

14-bit PWM output pin.

Timer/counter, CTL duty detection, 32kHz oscillation
adjustment output pin.

Input pin to request external interruption and
non-maskable interruption. Active when falling edge.

Serial clock (CH1) I/O pin.

Serial data (CH1) output pin.

Serial data (CH1) input pin.

(Port I)
7-bit I/O port.
I/O port can be
specified by bit
unit.
(7 pins)

(Port J)
8-bit I/O port. Function as standby release input can be specified by bit
unit. I/O can be specified by bit unit.

Connecting pin of crystal oscillator for system clock. When supplying
the external clock, input the external clock to EXTAL pin and input
opposite phase clock to XTAL pin.

Connecting pin of crystal oscillator for 32kHz timer clock. When used
as event counter, input to TEX pin and leave TX pin open. (Feedback
resistor is not removed.)

System reset pin of active "L" level.

Microprocessor mode input pin. Always connect to GND.

Positive power supply pin of A/D converter.

Reference voltage input pin of A/D converter.

GND pin of A/D converter.

Positive power supply pin.

GND pin. Connect both Vss pins to GND.

Symbol

I/O

Description

Capstan FG input pin.

Drum FG input pin.

Drum PG input pin.

Playback CTL pulse input pin.
External event input pin of timer/counter.

CXP87352/87360

PPO8 or PPO10

Data bus

PB0 or PB2 data

PPO9 or PPO11

Data bus

PB1 or PB3 data

PPG contorl
status register
bit 0
3-state control selection

PPO9 or PPO11

Output becomes active from high impedance
by data writing to port register.

Output becomes active from high
impedance by data writing to port register.

12 pins

2 pins

Hi-Z

When reset

PA0 /PPO0

PA7/PPO7

PB4/PPO12

PB7/PPO15

PB0 /PPO8
PB2/PPO10

Hi-Z

PB1/PPO9
PB3/PPO11

PPO data

Data bus

Output becomes active from high
impedance by data writing to port register.

Port A or Port B

Input/Output Circuit Formats for Pins

Port A

Port B

Circuit format

CXP87352/87360

4 pins

Hi-Z

PF4/AN8

PF7/AN11

A/D
converter

Data bus

RD
(Port F)

Port/AD select

Port F data

Input multiplexer

Port F

8 pins

Hi-Z

PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0
PG5/SYNC1
PG6/EXI0
PG7/EXI1

RD (Port G)

Data bus

Schmitt input

Servo input

Note) For PG4/SYNC0, PG5/SYNC1, CMOS schmitt input and TTL schmitt
input can be selected with the mask option.

Port G

8 pins

Hi-Z

PH0

PH7

Data bus

RD (Port H)

Port H data

Large current
12mA

Medium withstand
voltage 12V

Port H

2 pins

Hi-Z

PI2/PWM
PI3/TO/
DDO/ADJ

PI2: From 14-bit PWM
PI3: From timer/counter,
CTL duty detection circuit,
32kHz timer

MPX

Port I data

Data bus

RD (Port I)

Port I direction

Port I function
select

Port I

When reset

Circuit format

CXP87352/87360

SO0 output enable

SO0 from SIO

3 pins

Hi-Z

PI1/RMC
PI4/INT1/NMI
PI7/SI1

PI5/SCK1
PI6/SO1

2 pins

8 pins

1 pin

Hi-Z

PJ0

PJ7

Standby release

Port J data

Data bus

RD
(Port J)

Port J direction

Edge detection

Data bus

MPX

Port I data

Data bus

RD (Port I)

Port I direction

Port I function
select

MPX

To serial CH1

Note)
PI5 is schmitt input
PI6 is inverter input

From serial CH1

PI1: To remote control circuit
PI4: To interruption circuit
PI7: To serial CH1

Port I data

Data bus

RD (Port I)

Port I direction

Schmitt input

Port J

CS0
SI0

Schmitt input

To SIO

2 pins

SO0

Port I

When reset

Circuit format

CXP87352/87360

2 pins

Oscillation

EXTAL
XTAL

EXTAL

XTAL

· Shows the circuit
composition during
oscillation.

· Feedback resistor is
removed during stop.

2 pins

Oscillation

TEX
TX

TEX

· Shows the circuit
composition during
oscillation.
· Feedback resistor is
removed during 32kHz
oscillation circuit stop
by software.
At this time TEX pin
outputs "L" level and TX
pin outputs "H" level.

32kHz
timer counter

1 pin

Hi-Z

SCK0

SCK0 output enable

Internal serial clock
from SIO

Schmitt input

External serial clock to SIO

1 pin

Hi-Z

CPU mode

1 pin

L level

RST

Schmitt input

Pull-up resistor

Mask option

When reset

Circuit format

CXP87352/87360

and V

should be set to a same voltage.

and V

OUT

should not exceed V

+ 0.3V.

The large current operation transistors are the N-CH transistors of the PD and PH ports.

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

better take place under the recommended operating conditions. Exceeding those conditions may

adversely affect the reliability of the LSI.

Supply voltage

Input voltage

Output voltage

Medium withstand output voltage

High level output current

High level total output current

Low level total output current

Operating temperature

Storage temperature

Allowable power dissipation

OUT

OUTP

OLC

Topr

Tstg

Low level output current

0.3 to +7.0

AVss to +7.0

0.3 to +0.3

0.3 to +7.0

0.3 to +15.0

130

20 to +75

55 to +150

600

380

°C

PH pin

Total of output pins

Other than large current output
pins: per pin

Large current port pin

: per pin

Total of output pins

QFP package type

LQFP package type

Item

Symbol

Rating

Unit

Remarks

Absolute Maximum Ratings

(Vss = 0V)

CXP87352/87360

Analog power supply

High level
input voltage

Low level
input voltage

Operating temperature

Supply voltage

5.5

+ 0.3

+ 0.2

0.3V

0.2V

0.8

0.4

0.2

+75

°C

Item

Symbol

Min.

Max.

Unit

Remarks

3.0

2.7

2.0

3.0

0.7V

0.8V

2.2

0.4

0.2

0.3

IHS

IHTS

IHEX

ILS

ILTS

ILEX

Topr

Guaranteed range during high speed mode
(1/2 dividing clock) operation

Guaranteed range during low speed mode
(1/16 dividing clock) operation

Guaranteed operation range by TEX clock

Guaranteed data hold operation range
during STOP

CMOS schmitt input

and PE0/INT0 pin

CMOS schmitt input

TTL schmitt input

EXTAL pin

and TEX pin

EXTAL pin

and TEX pin

CMOS schmitt input

and PE0/INT0 pin

TTL schmitt input

EXTAL pin

and TEX pin

EXTAL pin

and TEX pin

and V

should be set to a same voltage.

Normal input port (each pin of PC, PD, PF0 to PF3, PG, PI and PJ), MP pin.

Each pin of SCK0, RST, PE1/EC/INT2, PI1/RMC, PI4/INT1/NMI, PI5/SCK1 and PI7/SI1.

Each pin of PG4 and PG5 (When TTL schmitt input is selected with mask option)

It specifies only when the external clock is input.

It specifies only when the external event count clock is input.

Each pin of CS0, SI0, and PG (For PG4 and PG5, when CMOS schmitt input is selected with mask option.)

In case of 4.5 to 5.5V supply voltage (V

In case of 3.0 to 3.6V supply voltage (V

Recommended Operating Conditions

(Vss = 0V)

CXP87352/87360

= 4.5V, I

= 0.5mA

= 4.5V, I

= 1.2mA

= 4.5V, I

= 1.8mA

= 4.5V, I

= 3.6mA

= 4.5V, I

= 12.0mA

= 5.5V, V

= 5.5V

= 5.5V, V

= 0.4V

= 5.5V, V

= 5.5V

High level
output voltage

4.0

3.5

0.5

0.1

1.5

µA

PD, PH

PA to PD,
PE2 to PE7,
PF4 to PF7,
PH (V

only)

PI1 to PI7
PJ, SO0, SCK0

EXTAL

TEX

RST

Item

Symbol

Pins

Conditions

Min.

Other than V

Vss, AV

, and

AVss

Clock 1MHz
0V other than the measured pins

DD1

LOH

DDS1

DD2

DDS2

DDS3

IHE

ILE

IHT

ILT

ILR

Low level
output voltage

Input current

Typ.

0.4

0.6

1.5

400

±10

Max.

Unit

DC Characteristics (V

= 4.5 to 5.5V)

Electrical Characteristics

(Ta = 20 to +75°C, Vss = 0V)

RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current

when non-resistor is selected.

When entire output pins are open.

When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FE

) to "00" and

operating in high speed mode (1/2 dividing clock).

= 5V ± 0.5V

SLEEP mode

= 5V ± 0.5V

Supply
current

Input capacity

= 5.5V,

= 0.4V

= 5.5V,

= 0, 5.5V

= 5.5V

= 12V

16MHz crystal oscillation (C

= C

= 15pF)

STOP mode
(EXTAL and TEX pins oscillation stop)

I/O leakage
current

Open drain
output leakage
current (N-CH
Tr OFF in state)

PA to PG,
PI, PJ, MP
AN0 to AN3,
CS0, SI0, SO0
SCK0, RST

2.0

110

µA

= 3V ± 0.3V

SLEEP mode

= 3V ± 0.3V

32kHz crystal oscillation (C

= C

= 47pF)

CXP87352/87360

= 3.0V, I

= 0.15mA

= 3.0V, I

= 0.5mA

= 3.0V, I

= 1.2mA

= 3.0V, I

= 1.6mA

= 3.0V, I

= 5mA

= 3.6V, V

= 3.6V

= 3.6V, V

= 0.3V

= 3.6V, V

= 3.6V

High level
output voltage

2.7

2.3

0.3

0.1

0.9

µA

PD, PH

PA to PD,
PE2 to PE7,
PF4 to PF7,
PH (V

only)

PI1 to PI7
PJ, SO0, SCK0

EXTAL

TEX

RST

Item

Symbol

Pins

Conditions

Min.

Other than V

Vss, AV

, and

AVss

Clock 1MHz
0V other than the measured pins

DD1

LOH

DDS1

DDS3

IHE

ILE

IHT

ILT

ILR

Low level
output voltage

Input current

Typ.

0.3

0.5

1.0

200

±10

Max.

Unit

DC Characteristics (V

= 3.0 to 3.6V)

(Ta = 20 to +75°C, Vss = 0V)

RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current

when non-resistor is selected.

When entire output pins are open.

When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FE

) to "00" and

operating in high speed mode (1/2 dividing clock).

= 3.3V ± 0.3V

SLEEP mode

= 3.3V ± 0.3V

Supply
current

Input capacity

= 3.6V,

= 0.3V

= 3.6V,

= 0, 3.6V

= 3.6V,

= 12V

12MHz crystal oscillation (C

= C

= 15pF)

STOP mode
(EXTAL and TEX pins oscillation stop)

I/O leakage
current

Open drain
output leakage
current

PA to PG,
PI, PJ, MP
AN0 to AN3,
CS0, SI0, SO0
SCK0, RST

0.8

2.5

µA

CXP87352/87360

Fig. 1,

Fig. 2

Fig. 1,

Fig. 2 (External clock drive)

Fig. 1, Fig. 2
(External clock drive)

Fig. 3

Fig. 2 V

= 2.7 to 5.5V

(32kHz clock applied condition)

Fig. 3

sys indicates three values according to the contents of the clock control register (address; 00FE

) upper 2

bits (CPU clock selection).

sys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

EXTAL

0.4V

1/fc

External clock

EXTAL

XTAL

74HC04

Crystal oscillation
Ceramic oscillation

EXTAL

XTAL

32kHz clock applied condition
crystal oscillation

TEX

AC Characteristics

(1) Clock timing

System clock frequency

System clock input
pulse width

System clock input
rise and fall times

Event count clock input
pulse width

Event count clock input
rise and fall times

System clock frequency

Event count clock input
pulse width

Event count clock input
rise and fall times

XTAL
EXTAL

TEX
TX

TEX

MHz

kHz

µs

Item

Symbol

Pins

Conditions

Unit

Min.

37.5

sys

32.768

Max.

200

(Ta = 20 to +75°C, V

= 3.0 to 5.5V, Vss = 0V)

Fig. 1. Clock timing

Fig. 2. Clock applied condition

TEX
EC

0.2V

0.8V

Fig. 3. Event count clock timing

= 4.5 to 5.5V

CXP87352/87360

Input mode

Output mode

Input mode

Output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode

Note 1)

sys indicates three values according to the contents of the clock control register (address; 00FE

)

upper 2 bits (CPU clock selection).

sys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2) CS, SCK, SI and SO means each pin of CS

CS0, SCK

SCK0, SI

SI0, and SO

SO0 respectively.

Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.

(2) Serial transfer (CH0)

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V)

Item

SCK

delay time

SCK

floating delay time

delay time

floating delay time

CS
high level width

SCK
cycle time

SCK
high and low level widths

SI input setup time
(against SCK

)

SI input hold time
(against SCK

)

SCK

SO delay time

DCSK

DCSKF

DCSO

DCSOF

WHCS

KCY

SIK

KSI

KSO

SCK0

SO0

CS0

SCK0

SI0

SO0

Symbol

Min.

sys + 200

8000/fc

sys + 100

8000/fc 100

sys + 100

200

sys + 100

100

sys + 200

100

Max.

Unit

Condition

CXP87352/87360

Input mode

Output mode

Input mode

Output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode

Note 1)

sys indicates three values according to the contents of the clock control register (address; 00FE

)

upper 2 bits (CPU clock selection).

sys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2) CS, SCK, SI and SO means each pin of CS

CS0, SCK

SCK0, SI

SI0, and SO

SO0 respectively.

Note 3) The load of SCK output mode and SO output delay time is 50pF.

Serial transfer (CH0)

(Ta = 20 to +75°C, V

= 3.0 to 3.6V, Vss = 0V)

Item

SCK

delay time

SCK

floating delay time

delay time

floating delay time

CS
high level width

SCK
cycle time

SCK
high and low level widths

SI input setup time
(against SCK

)

SI input hold time
(against SCK

)

SCK

SO delay time

DCSK

DCSKF

DCSO

DCSOF

WHCS

KCY

SIK

KSI

KSO

SCK0

SO0

CS0

SCK0

SI0

SO0

Symbol

Min.

sys + 250

sys + 200

sys + 250

sys + 200

8000/fc

sys + 100

8000/fc 150

sys + 100

200

sys + 100

100

sys + 250

125

Max.

Unit

Condition

CXP87352/87360

Serial transfer (CH1) (SIO mode)

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V)

Item

Symbol

Min.

Max.

Unit

Condition

SCK1 cycle time

SCK1 high and low
level widths

SI1 input setup time
(against SCK1

)

SI1 input hold time
(against SCK1

)

SCK1

SO1 delay time

KCY

SIK

KSI

KSO

SCK1

SI1

SO1

Input mode

Output mode

Input mode

Output mode

SCK1 input mode

SCK1 output mode

SCK1 input mode

SCK1 output mode

SCK1 input mode

SCK1 output mode

sys + 200

16000/fc

sys + 100

8000/fc 50

100

200

sys + 200

100

sys + 200

100

Note 1)

sys indicates three values according to the contents of the clock control register (address; 00FE

)

upper 2 bits (CPU clock selection).

sys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.

Serial transfer (CH1) (SIO mode)

(Ta = 20 to +75°C, V

= 3.0 to 3.6V, Vss = 0V)

Item

Symbol

Min.

Max.

Unit

Condition

SCK1 cycle time

SCK1 high and low
level widths

SI1 input setup time
(against SCK1

)

SI1 input hold time
(against SCK1

)

SCK1

SO1 delay time

KCY

SIK

KSI

KSO

SCK1

SI1

SO1

Input mode

Output mode

Input mode

Output mode

SCK1 input mode

SCK1 output mode

SCK1 input mode

SCK1 output mode

SCK1 input mode

SCK1 output mode

sys + 200

16000/fc

sys + 100

8000/fc 150

100

200

sys + 200

100

sys + 250

125

Note 1)

sys indicates three values according to the contents of the clock control register (address; 00FE

)

upper 2 bits (CPU clock selection).

sys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF.

CXP87352/87360

SO1 cycle time

SI1 data setup time

SI1 data hold time

LCY

LSU

LHD

SO1
SI1

SI1

Note 1)

104

µs

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Serial transfer (CH1) (Special mode)

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V)

Note 1)

LCY

specifies only serial mode register (CH1) (SIOM1: Address 01FA

) lower 2 bits (SO1 clock

selection) has been set at 104µs.

Note 2) The load of SO1 pin is 50pF + 1TTL.

SO1 cycle time

SI1 data setup time

SI1 data hold time

LCY

LSU

LHD

SO1
SI1

SI1

Note 1)

104

µs

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Serial transfer (CH1) (Special mode)

(Ta = 20 to +75°C, V

= 3.0 to 3.6V, Vss = 0V)

Note 1)

LCY

specifies only serial mode register (CH1) (SIOM1: Address 01FA

) lower 2 bits (SO1 clock

selection) has been set at 104µs.

Note 2) The load of SO1 pin is 50pF.

Fig. 6. Serial transfer CH1 timing (Special mode)

SO1

SI1

LCY

Start bit

Output data bit

LCY

0.5V

0.8V

0.2V

LCY/2

LSU

LHD

Input

data bit

CXP87352/87360

External clock input frequency

External clock input pulse width

External clock input
rising and falling times

Prescaler output delay time
(against PCK

)

Prescaler output
rising and falling times

HCK

HLH

HHL

TLH

THL

SYNC1

HCOUT

External clock input
SYNC1

= 6ns

External clock input
SYNC1

= 6ns

sys + 130

sys + 90

100

200

sys + 220

sys + 150

280

MHz

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

(4) HSYNC counter

Note1)

sys indicates three values according to the contents of the clock control register (address; 00FE

)

upper 2 bits (CPU clock selection).

sys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11").

Note2) The load of HCOUT pin is 50pF.

(Ta = 20 to +75°C, V

= 3.0 to 5.5V, Vss = 0V)

1/f

HCK

0.8V

0.5V

0.2V

HLH

0.8V

0.5V

0.2V

TLH

THL

HHL

SYNC1

HCOUT

Fig. 8. General purpose prescaler timing

CXP87352/87360

Conversion time

Sampling time

Reference input voltage

Analog input voltage

CONV

SAMP

REF

IAN

REF

Ta = 25°C
V

= AV

REF

= 5.0V

= AV

= 0V

Operating mode

SLEEP mode
STOP mode
32kHz operating mode

Linearity error

Absolute error

Resolution

REF

current

REF

REFS

µs

1.0

µA

0.6

160/f

ADC

12/f

ADC

0.5

Item

Symbol

Pins

Conditions

Min.

Typ.

Max.

Unit

Bits

(5) A/D converter characteristics

(Ta = 20 to +75°C, V

= AV

= 4.5 to 5.5V, AV

REF

= 4.0 to AV

, Vss = AV

= 0V)

±1

±2

LSB

Analog input

Linearity error

Digital conversion value

The value of f

ADC

is as follows by selecting ADC

operation clock (MSC: Address 01FF

bit 0).

When PS2 is selected, f

ADC

= fc/2

When PS1 is selected, f

ADC

= fc

Fig. 9. Definitions of A/D converter terms

Conversion time

Sampling time

Reference input voltage

Analog input voltage

CONV

SAMP

REF

IAN

REF

Ta = 25°C
V

= AV

REF

= 5.0V

= AV

= 0V

Operating mode

SLEEP mode
STOP mode
32kHz operating mode

Linearity error

Absolute error

Resolution

REF

current

REF

REFS

µs

0.7

µA

0.4

160/f

ADC

12/f

ADC

0.3

Item

Symbol

Pins

Conditions

Min.

Typ.

Max.

Unit

Bits

(Ta = 20 to +75°C, V

= AV

= 3.0 to 3.6V, AV

REF

= 2.7 to AV

, Vss = AV

= 0V)

±1

±2

LSB

= AV

= 3.0 to 3.6V

REF

AN0 to AN11

REF

= AV

= 4.5 to 5.5V

AN0 to AN11

CXP87352/87360

External interruption
high and low level widths

Reset input low level width

INT0
INT1
INT2
NMI
PJ0 to PJ7

RST

32/fc

µs

Item

Symbol

Pins

Conditions

Min.

Max.

Unit

RSL

(6) Interruption, reset input

(Ta = 20 to +75°C, V

= 3.0 to 5.5V, Vss = 0V)

0.2V

0.8V

INT0

INT1

INT2

NMI

PJ0 to PJ7

(During standby release input)

(Falling edge)

Fig. 10. Interruption input timing

RSL

0.2V

RST

Fig. 11. Reset input timing

(7) Others

(Ta = 20 to +75°C, V

= 3.0 to 5.5V, Vss = 0V)

Item

CFG input
high and low level widths

DFG input
high and low level widths

DPG minimum pulse width

DPG minimum
removal time

PBCTL input
high and low level widths

EXI input
high and low level widths

CFH

CFL

DFH

DFL

DPW

rem

CTH

CTL

EIH

EIL

CFG

DFG

DPG

PBCTL

EXI0
EXI1

Symbol

Pins

Min.

FRC

24 + 200

FRC

16 + 200

FRC

8 + 200

FRC

16 + 200

FRC

8 + 200 +

sys

FRC

8 + 200 +

sys

Max.

Unit

sys = 2000/fc

Conditions

Note)

sys indicates three values according to the contents of the clock control register (address; 00FE

)

upper 2 bits (CPU clock selection).

sys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

FRC

= 1000/fc [ns]

CXP87352/87360

Supplement

Fig. 13. Recommended oscillation circuit

EXTAL

XTAL

(i)

TEX

(ii)

Manufacturer

RIVER
ELETEC
CO., LTD.

KINSEKI LTD.

Model

HC-49/U03

HC-49/U (-S)

fc (MHz)

8.00

10.00

12.00

8.00

10.00

12.00

470K

(ii)

32.768kHz

16 (12)

16.00

16 (12)

(pF)

Rd (

)

Circuit

example

(i)

In PG4/SYNC0 pin and PG5/SYNC1 pin, the input circuit format can be selected to every pin.

However, TTL schmitt can not be selected when the supply voltage (V

) ranges from 3.0V to 5.5V.

Item

Content

Reset pin pull-up resistor

Input circuit format

Non-existent

C-MOS schmitt

Existent

TTL schmitt

Mask option table

16.00

16 (12)

CXP87352/87360

Characteristics Curve

(100µA)

0.1

5.0

1.0

Supply voltage [V]

Supply current [mA]

vs. V

(fc = 16MHz, Ta = 25°C, Typical)

0.05

(50µA)

0.01

(10µA)

0.5

10.0

20.0

1/16 dividing mode

SLEEP mode

32kHz mode
(instruction)

32kHz
SLEEP mode

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode

SLEEP mode

Frequency [MHz]

Supply current [mA]

vs. fc

= 5V, Ta = 25°C, Typical)

1/2 dividing mode

1/4 dividing mode

(100µA)

0.1

5.0

1.0

Supply voltage [V]

Supply current [mA]

vs. V

(fc = 12MHz, Ta = 25°C, Typical)

0.05

(50µA)

0.01

(10µA)

0.5

10.0

20.0

1/16 dividing mode

SLEEP mode

1/2 dividing mode

1/4 dividing mode

Frequency [MHz]

Supply current [mA]

vs. fc

= 3.3V, Ta = 25°C, Typical)

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode

SLEEP mode

CXP87352/87360

Package Outline

Unit: mm

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN

SOLDER PLATING

42/COPPER ALLOY

PACKAGE STRUCTURE

23.9

0.4

QFP-100P-L01

100PIN QFP (PLASTIC)

20.0 0.1

+ 0.4

0.15 0.05

+ 0.1

15.8

0.4

17.9

0.4

14.0

0.1

+ 0.4

2.75 0.15

+ 0.35

0.65

0.13

QFP100-P-1420

1.7g

100

0.3 0.1

+ 0.15

DETAIL A

0° to 10°

0.8

0.2

(16.3)

0.15

0.1 0.05

+ 0.2

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN

SOLDER PLATING

42/COPPER ALLOY

PACKAGE STRUCTURE

23.9

0.4

QFP-100P-L01

100PIN QFP (PLASTIC)

20.0 0.1

+ 0.4

0.15 0.05

+ 0.1

15.8

0.4

17.9

0.4

14.0

0.1

+ 0.4

2.75 0.15

+ 0.35

0.65

0.13

QFP100-P-1420

1.7g

100

0.3 0.1

+ 0.15

DETAIL A

0° to 10°

0.8

0.2

(16.3)

0.15

0.1 0.05

+ 0.2

LEAD SPECIFICATIONS

ITEM

LEAD MATERIAL

COPPER ALLOY

LEAD TREATMENT

Sn-Bi 2.5%

LEAD TREATMENT THICKNESS

5-18

SPEC.

CXP87352/87360

Package Outline

Unit: mm

100PIN LQFP (PLASTIC)

100

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN

SOLDER PLATING

42 / COPPER ALLOY

PACKAGE STRUCTURE

DETAIL A

LQFP-100P-L01

P-LQFP100-14x14-0.5

16.0

0.2

14.0

0.1

0.5

(0.22)

1.5 0.1

+ 0.2

0.5

0.2

(15.0)

0° to 10°

0.1

0.5

0.2

0.1

NOTE: Dimension "

" does not include mold protrusion.

0.7g

0.13 M

b = 0.18 0.03

( 0.18 )

(0.127)

+ 0.08

0.127 0.02

+ 0.05

DETAIL B

100PIN LQFP (PLASTIC)

100

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN

SOLDER PLATING

42 / COPPER ALLOY

PACKAGE STRUCTURE

DETAIL A

LQFP-100P-L01

P-LQFP100-14x14-0.5

16.0

0.2

14.0

0.1

0.5

(0.22)

1.5 0.1

+ 0.2

0.5

0.2

(15.0)

0° to 10°

0.1

0.5

0.2

0.1

NOTE: Dimension "

" does not include mold protrusion.

0.7g

0.13 M

b = 0.18 0.03

( 0.18 )

(0.127)

+ 0.08

0.127

0.02

+ 0.05

DETAIL B

LEAD SPECIFICATIONS

ITEM

LEAD MATERIAL

COPPER ALLOY

LEAD TREATMENT

Sn-Bi 2.5%

LEAD TREATMENT THICKNESS

5-18

SPEC.

Sony Corporation

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXP87352/87360