Description

The CXP87852/87860 is a CMOS 8-bit microcomputer

which consists of A/D converter, serial interface,
timer/counter, time base timer, high precision timing
pattern generation circuit, PWM output, VISS/VASS
circuit, 32kHz timer/counter, remote control reception
circuit, HSYNC counter, VSYNC separator and the
measurement circuit which measures signals of
capstan FG and drum FG/PG and other servo
systems, as well as basic configurations like 8-bit
CPU, ROM, RAM and I/O port. They are integrated
into a single chip.

Also the CXP87852/87860 provides sleep/stop

functions which enable to lower power consumption.

Features
· A wide instruction set (213 instructions) which covers various types of data

-- 16-bit operation/multiplication and division/Boolean bit operation instructions

· Minimum instruction cycle

250ns at 16MHz operation (4.5V to 5.5V)
122µs at 32kHz operation (2.7V to 5.5V)

· Incorporated ROM capacity

52K bytes (CXP87852), 60K bytes (CXP87860)

· Incorporated RAM capacity

2048 bytes

· Peripheral functions

-- A/D converter

8 bits, 12 channels, successive approximation system
(Conversion time of 20.0µs at 16MHz)

-- Serial Interface

Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channel
Incorporated 8-bit and 8-stage FIFO
(Auto transfer for 1 to 8 bytes), 1 channel
Incorporated two-wire 8-bit and 8-stage FIFO
(Auto transfer for 1 to 8 bytes), 1 channel

-- Timer

8-bit timer, 8-bit timer/counter, 19-bit time base timer,
32kHz timer/counter

-- High precision timing pattern generator

PPG: maximum of 19 pins, 32 stages programmable
RTG: 5 pins, 2 channels

-- PWM/DA gate output

PWM: 12 bits, 2 channels (Repetitive frequency of 62kHz at 16MHz)
DA gate pulse output: 13 bits, 4 channels

-- Servo input control

Capstan FG, drum FG/PG, CTL input

-- VSYNC separator
-- FRC capture unit

Incorporated 26-bit and 8-stage FIFO

-- PWM output

14 bits

-- VISS/VASS circuit

Pulse duty auto detection circuit

-- Remote control reception circuit

8-bit pulse measurement counter with on-chip 6-stage FIFO

-- HSYNC counter

12-bit event counter (Counts SYNC1 input.)

· Interruption

23 factors, 15 vectors, multi-interruption possible

· Standby mode

Sleep/stop

· Package

100-pin plastic QFP

· Piggyback/evaluator

CXP87800 100-pin ceramic PQFP

CXP87852/87860

E96215-PS

CMOS 8-bit Single Chip Microcomputer

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

100 pin QFP (PIastic)

Structure

Silicon gate CMOS IC

CXP87852/87860

PBCTL

SCK1

DPG

SO1

PA0 to PA7

PB0 to PB7

PC0 to PC7

PD0 to PD7

PE0 to PE1

PE2 to PE7

PF0 to PF3

PF4 to PF7

PG0 to PG7

PI1 to PI7

PJ0 to PJ7

RST

XTAL

EXTAL

CLOCK

GENERATOR/

SYSTEM CONTROL

RAM

2048 BYTES

SPC700

CPU CORE

ROM

52K/60K BYTES

INTERRUPT CONTROLLER

32kHz

TIMER/COUNTER

FIFO

FRC

CAPTURE UNIT

PROGRAMMABLE

PATTERN

GENERATOR

RAM

AVss

REF

A/D CONVERTER

SERIAL

INTERFACE UNIT

(CH0)

RAM

8 BIT TIMER/COUNTER 0

8 BIT TIMER 1

VSYNC SEPARATOR

14 BIT PWM GENERATOR

12 BIT PWM GENERATOR CH0

SERVO INPUT

CONTROL

CAPSTAN

DRUM

CTL

12 BIT PWM GENERATOR CH1

DAB1

DAA1

PWM1

DAB0

DAA0

PWM0

PWM

RMC

DFG

CFG

EXI1

EXI0

SYNC1

SYNC0

TO/DDO

SI1

SCK0

SO0

SI0

CS0

AN0 to AN11

REALTIME

PULSE

GENERATOR

INT2

INT0

INT1/NMI

PORT A

PORT B

PORT C

PORT D

PORT E

PORT F

PORT G

PORT H

PORT I

PH0 to PH7

TEX

PRESCALER/

TIME BASE TIMER

VISS/VASS

REMOCON INPUT

FIFO

SERIAL

INTERFACE UNIT

(CH1)

CH0

CH1

PORT J

PPO0 to PPO18

RTO3 to RTO7

FIFO

HSYNC COUNTER

HCOUT

ADJ

Vss

SERIAL

INTERFACE UNIT

(CH2)

FIFO

SDA0

SCL1

SCL0

CKOUT

SDA1

Block Diagram

CXP87852/87860

Pin Assignment (Top View)

PB5/PPO13

PB4/PPO12

PB3/PPO11

PB2/PPO10

PB1/PPO9

PB0/PPO8

PC7/RTO7

PC6/RTO6

PC5/RTO5

PC4/RTO4

PC3/RTO3

PC2/PPO18

PC1/PPO17

PC0/PPO16

PJ7

PJ6

PJ5

PJ4

PJ3

PJ2

PJ1

PJ0

PD7

PD6

PD5

PD4

PD3/SDA1

PD2/SDA0

PD1/SCL1

PD0/SCL0

PI6/SO1

PI7/SI1

PE0/INT0/CKOUT

PE1/EC/INT2/HCOUT

PE2/PWM0

PE3/PWM1

PE4/DAA0

PE5/DAA1

PE6/DAB0

PE7/DAB1

PG0/CFG

PG1/DFG

PG2/DPG

PG3/PBCTL

PG4/SYNC0

PG5/SYNC1

PG6/EXI0

PG7/EXI1

AN0

AN1

AN2

AN3

PF0/AN4

PF1/AN5

PF2/AN6

PF3/AN7

REF

PF4/AN8

PB6/PPO14

PB7/PPO15

PA0/PPO0

PA1/PPO1

PA2/PPO2

PA3/PPO3

PA4/PPO4

PA5/PPO5

PA6/PPO6

PA7/PPO7

TEX

PI1/RMC

PI2/PWM

PI3/TO/DDO/ADJ

PI4/INT1/NMI

PI5/SCK1

31 32 33

41 42 43 44 45 46 47 48 49 50

88 87 86 85

100 99 98 97 96 95 94

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

RST

XTAL

EXTAL

CS0

SI0

SO0

SCK0

PF7/AN11

PF6/AN10

PF5/AN9

Note) 1. NC (Pin 90) is always connected to V

2. Vss (Pins 41 and 88) are both connected to GND.

3. MP (Pin 39) is always connected to GND.

CXP87852/87860

Output/
Real-time
output

I/O/
Real-time
output

I/O

Input/Input/Output

Input/Input/Input/
Output

Output/Output

Input

Input/Input

Output/Input

I/O

Ouput

Input

(Port A)
8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)

(Port B)
8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)

(Port C)
8-bit I/O port. I/O can be set
in a unit of single bits.
Data is gated with PPO or
RTO contents by OR-gate
and they are output.
(8 pins)

(Port D)
8-bit I/O port. I/O can be set in a unit of
single bits for upper 4 bits.
Can drive 12mA sink current.
Lower 4-bit output is N-ch open drain.
(8 pins)

(Port E)
8-bit port.
Lower 2 bits
are for inputs;
upper 6 bits
are for outputs.
(8 pins)

Analog inputs to A/D converter. (12 pins)

(Port F)
8-bit port. Lower 4 bits are for inputs; upper 4 bits are for
outputs.
Lower 4 bits also serve as standby release input pin.
(8 pins)

Serial clock (CH0) I/O.

Serial data (CH0) output.

Serial data (CH0) input.

Serial chip select (CH0) input.

External event
input for
timer/counter.

Input to request external
interruption.
Active at the falling edge.

System clock
frequency dividing
output.

PWM outputs.
(2 pins)

DA gate pulse outputs.
(4 pins)

Programmable pattern generator (PPG)
output.
Functions as high precision real-time
pulse output port.
PB0 and PB2 can be 3-state controlled
with PPG.
(19 pins)

Real-time pulse generator (RTG) output.
Functions as high precision real-time
pulse output port. PC3 can be 3-state
controlled with RTG. (5 pins)

Symbol

I/O

Description

PA0/PPO0

PA7/PPO7

PB0/PPO8

PB7/PPO15

PC0/PPO16

PC2/PPO18

PC3/RTO3

PC7/RTO7

PD0/SCL0
PD1/SCL1

PD2/SDA0
PD3/SDA1

PD4 to PD7

PE0/INT0/
CKOUT

PE1/EC/INT2/
HCOUT

PE2/PWM0

PE3/PWM1

PE4/DAA0

PE5/DAA1

PE6/DAB0

PE7/DAB1

AN0 to AN3

PF0/AN4

PF3/AN7

PF4/AN8

PF7/AN11

SCK0

SO0

SI0

CS0

Pin Description

Coinsidence
signal output of
HSYNC counter.

Serial clock (CH2) I/O.
(2 pins)

Serial data (CH2) I/O.
(2 pins)

CXP87852/87860

PG0/CFG

PG1/DFG

PG2/DPG

PG3/PBCTL

PG4/SYNC0

PG5/SYNC1

PG6/EXI0

PG7/EXI1

PH0 to PH7

PI1/RMC

PI2/PWM

PI3/TO/
DDO/ADJ

PI4/INT1/
NMI

PI5/SCK1

PI6/SO1

PI7/SI1

PJ0 to PJ7

EXTAL

XTAL

TEX

RST

REF

AVss

Vss

Input/Input

Output

I/O/Input

I/O/Output

I/O/Output/
Output/Output

I/O/Input/Input

I/O/I/O

I/O/Output

I/O/Input

I/O

Input

Output

Input

Output

Input

Composite sync signal input.
(2 pins)

External input to FRC capture unit.
(2 pins)

(Port G)
8-bit input port.
(8 pins)

(Port H)
8-bit output port. N-ch open drain output of medium drive voltage (12V)
and large current (12mA).
(8 pins)

Remote control reception circuit input.

14-bit PWM output.

Timer/counter, CTL duty detection, 32kHz oscillation
adjustment output.

Input to request external interruption and
non-maskable interruption. Active at the falling edge.

Serial clock (CH1) I/O.

Serial data (CH1) output.

Serial data (CH1) input.

(Port I)
7-bit I/O port.
I/O port can be
set in a unit of
single bits.
(7 pins)

(Port J)
8-bit I/O port. I/O and standby release input function can be set in a
unit of single bits.

Connects a crystal oscillator for system clock. When supplying the
external clock, input the external clock to EXTAL and input the
opposite phase clock to XTAL .

Connects a crystal oscillator for 32kHz timer/counter clock. The 32kHz
crystal oscillator is inserted between TEX and TX. When used as event
counter, connect the clock source to TEX and leave TX open.

System reset; active at Low level.

Test mode input. Always connect to GND.

Positive power supply of A/D converter.

Reference voltage input of A/D converter.

GND of A/D converter.

Positive power supply. Connect V

pin to V

No connected. Connect to V

in normal operation.

GND. Connect both Vss pins to GND.

Symbol

I/O

Description

Capstan FG input.

Drum FG input.

Drum PG input.

Playback CTL pulse input.
External event input for timer/counter.

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