Description

The CXP88216/88220/88224 is a CMOS 8-bit

microcomputer which consists of A/D converter,
serial interface, timer/counter, time base timer, vector
interruption, high precision timing pattern generation
circuits, PWM generator, PWM for tuner, VISS/VASS
circuit, 32kHz timer/event counter, remote control
receiving circuit, FDP controller/driver, VCR vertical
sync separation circuit and the measuring circuit
which measure signals of capstan FG and drum
FG/PG and other servo systems, as well as basic
configurations like 8-bit CPU, ROM, RAM and I/O
port. They are integrated into a single chip.

Also, CXP88216/88220/88224 provides sleep/stop

function which enables to lower power consumption
and ultra-low speed instruction mode in 32kHz
operation.

Features
· A wide instruction set (213 instructions) which cover various types of data

-- 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction

· Minimum instruction cycle

During operation 250ns/16MHz, During operation 122µs/32kHz

· Incorporated ROM capacity

16Kbytes (CXP88216), 20Kbytes (CXP88220), 24Kbytes (CXP88224)

· Incorporated RAM capacity

880bytes

· Peripheral function

-- A/D converter

8-bit, 8-channel, successive approximation system

(Conversion time: 20.0µs/16MHz)

-- Serial I/O with auto transfer mode

Incorporated 8-stage FIFO for data (1 to 8 bytes auto transfer)

-- Timer

8-bit timer/counter, 2-channel, 19-bit time base timer

-- High precision timing pattern generation circuit

PPG 8 pins 32-stage programmable circuit, RTG 5 pins 2-channel

-- PWM/DA gate output

12-bit, 2-channel (Repetitive frequency 62.5kHz/16MHz)

-- Servo input control

Capstan FG, Drum FG/PG, CTL input

-- VSYNC separator
-- FRC capture unit

Incorporated 26-bit and 8-stage FIFO

-- PWM output for tuner

14-bit

-- VISS/VASS circuit

Pulse duty auto detection circuit

-- 32kHz timer/event counter

32kHz oscillation circuit, ultra-low speed instruction mode

-- Remote control receiving circuit

8-bit pulse measuring counter, 6-stage FIFO

-- FDP controller/driver

Max.148 segments can be displayed
Hardware key scanning function (Max.16

3 key matrix available)

-- Tri-state output

PPG 1 pin, RTG 1 pin, output 8 pins

-- Pseudo HSYNC output function
-- High speed head switching circuit

· Interruption

22 factors, 15 vectors, multi-interruption possible

· Standby mode

SLEEP/STOP

· Package

100-pin plastic QFP

· Piggyback/evaluation chip

CXP88100

Structure

Silicon gate CMOS IC

CXP88216/88220/88224

E94626-PS

CMOS 8-bit Single Chip Microcomputer

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

100 pin QFP (Plastic)

CXP88216/88220/88224

PF5/SO1

PA0 to PA7

PB0 to PB7

PC0 to PC7

PD0 to PD7

PE0 to PE1

PE2 to PE7

PF0 to PF3

PF4 to PF7

PG0 to PG7

PI0 to PI7

Vss

RST

XTAL

EXTAL

CLOCK

GENERATOR/

SYSTEM CONTROL

RAM

880 BYTES

SPC700

CPU CORE

ROM

16k/20k/24k BYTES

INTERRUPT CONTROLLER

32kHz

TIMER/COUNTER

FIFO

FRC

CAPTURE UNIT

PROGRAMABLE

PATTERN

GENERATOR

RAM

AVss

REF

A/D CONVERTERCONVERTER

SERIAL

INTERFACE UNIT

(CH0)

FIFO

8 BIT TIMER/COUNTER 0

V SYNC SEPARATOR

14 BIT PWM GENERATOR

12 BIT PWM GENERATOR CH0

SERVO INPUT

CONTROL

CAPSTAN

DRUM

CTL

12 BIT PWM GENERATOR CH1

PE7/DAB1

PE5/DAA0

PE3/PWM1

PE6/DAB0

PE4/DAA0

PE2/PWM0

PI2/PWM

PI1/RMC

PG3/PBCTL/EC1

PG2/DPG

PG1/DFG

PG0/CFG

PG7/EXI1

PG6/EXI0

PG5/SYNC1

PG4/SYNC0/EC2

PI3/TO/DD0

PE1/EC0

PF4/SCK1

PF6/SI1

PI5/SCK0

PI6/SO0

PI7/SI0

PI4/CS0

PF0/AN4

PF7/AN11

AN0 to AN3

REALTIME

PULSE

GENERATOR

PE1/INT2

PE0/INT0

PI4/INT1/NMI

PORT A

PORT B

PORT C

PORT D

PORT E

PORT F

PORT G

PORT H

PORT I

PH0 to PH2

TEX

NMI

PRESCALER/

TIME BASE TIMER

VISS/VASS

REMOCON INPUT

FIFO

SERIAL INTERFACE UNIT

(CH1)

CH0

PPO0 to PPO7

RTO3 to RTO7

8 BIT TIMER/COUNTER1

SELECT

FDP

CONTROLLER

/DRIVER

RAM

S0 to S7

T8/S15
to
T15/S8

T0 to T7

FDP

PSEUDO HSYNC GENERATOR

PA0/HGO

Block Diagram

CXP88216/88220/88224

Pin Configuration (Top View)

PB0

PC7/RTO7

PC6/RTO6

PC5/RTO5

PC4/RTO4

PC3/RTO3

PC2

PC1

PC0

PA7/PPO7

(HAMP) PA6/PPO6

(ROTA) PA5/PPO5

(RF-PLS) PA4/PPO4

PA3/PPO3

PA2/PPO2

PA1/PPO1

PA0/PPO0/HGO

PF7

PF6/SI1

PF5/SO1

PF4/SCK1

PF3/AN7

PF2/AN6

PF1/AN5

PF0/AN4

AN3

AN2

REF

PI6/SO0

PI7/SI0

FDP

PD0/S0

PD1/S1

PD2/S2

PD3/S3

PD4/S4

PD5/S5

PD6/S6

PD7/S7

T15/S8

T14/S9

T13/S10

T12/S11

T11/S12

T10/S13

T9/S14

T8/S15

PE0/INT0 (ENV-DET)

PE1/EC0/INT2

PE2/PWM0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PH0/KR0

PH1/KR1

PH2/KR2

TEX

PI1/RMC

PI2/PWM

PI3/T0/DDO/ADJ

PI4/INT1/NMI/CS0

PI5/SCK0

AN1

AN0

PG7/EXI1

PG6/EXI0

PG5/SYNC1

PG4/SYNC0/EC2

PG3/PBCTL/EC1

PG2/DPG

RST

XTAL

EXTAL

PG1/DFG

PG0/CFG

PE7/DAB1

PE6/DAB0

PE5/DAA1

PE4/DAA0

PE3/PWM1

31 32 33

41 42 43 44 45 46 47 48 49 50

88 87 86 85

100 99 98 97 96 95 94

Note) 1. NC (Pin 90) is always connected to V

2. Vss (Pins 41 and 88) are both connected to GND.

CXP88216/88220/88224

Analog input pins to A/D converter. (8 pins)

(Port F)
8-bit I/O port. Enable
to specify I/O by bit unit.
(8 pins)

Output/Real time
output/Output

I/O/
Real time output

Output/
Real time output

Output

Output/
Real time output

Output

Output/Output

Input/Input

Input/Input/Input

Output/Output

Input

Input/Input

I/O/I/O

I/O/Output

I/O/Input

I/O

(Port A)
8-bit I/O port. Enable to
specify I/O by bit unit.
Data is gated with PPO
content by OR-gate and
they are output.
(8 pins)

8-bit output port. Tri-state can be controlled.
(8 pins)

(Port C)
8-bit I/O port. Enable to
specify I/O by bit unit.
Data is gated with RTO
content by OR-gate and
they are output. (8 pins)

FDP timing signal output pin.

Output pins for FDP timing signal and segment signal.

(Port D)
8-bit output port.
(8 pins)

(Port E)
8-bit port.
Lower 2 bits are input pins
and upper 6 bits are
output pins.
(8 pins)

Serial clock (CH1) I/O pin.

Serial data (CH1) output pin.

Serial data (CH1) input pin.

Trigger pulse
input pin for head
switching output.

External event
input pin for
timer/counter.

Input pin to request
external interruption.
Active when falling edge.

FDP segment signal output pin.

PWM output pins.
(2 pins)

DA gate pulse output pins.
(2 pins)

Programable pattern generator (PPG)
output. Functions as high precision real-
time pulse output port.
(8 pins)

Head switching
output pins.

Pseudo HSYNC
output pin.

Real-time pulse generator (RTG) output.
Functions as high precision real-time pulse
output port.
(5 pins)

Symbol

I/O

Description

PA0/PPO0
/HGO

PA1/PPO1

PA2/PPO2

PA3/PPO3

PA4/PPO4

PA5/PPO5

PA6/PPO6

PA7/PPO7

PB0 to PB7

PC0 to PC2

PC3/PPO3

PC7/PPO15

T0 to T7

T8/S15

T15/S8

PD0/S0

PD7/S7

PE0/INT0

PE1/EC0/
INT2

PE2/PWM0

PE3/PWM1

PE4/DAA0

PE5/DAA1

PE6/DAB0

PE7/DAB1

AN0 to AN3

PF0/AN0

PF3/AN3

PF4/SCK1

PF5/SO1

PF6/SI1

PF7

Pin Description

CXP88216/88220/88224

PG0/CFG

PG1/DFG

PG2/DPG

PG3/
PBCTL/EC1

PG4/
SYNC0/EC2

PG5/SYNC1

PG6/EXI0

PG7/EXI1

PH0/KR0

PH2/KR2

PI1/RMC

PI2/PWM

PI3/TO/
DDO/ADJ

PI4/INT1/
NMI/CS0

PI5/SCK0

PI6/SO0

PI7/SI0

EXTAL

XTAL

TEX

RST

FDP

REF

AVss

Vss

Input/Input

Input/Input/Input

Input/Input

I/O/Input

I/O/Output/Output/
Output

I/O/Input/
Input/Input

I/O/Input

I/O/Output

I/O/Input

Input

Output

Input

Output

Input

Capstan FG input pin.

Drum FG input pin.

Drum PG input pin.

Playback CTL input pin.

Composite sync signal input pins.

External input pins for FRC capture unit.

Key return input signal for key scanning at FDP
segment signal.

External event
input pin for
timer/counter.

(Port G)
8-bit input port.
(8 pins)

(Port H)
3-bit I/O port.
(3 pins)

Remote control receiving circuit input pin.

14-bit PWM output pin.

Timer/counter, CTL duty detection, 32kHz oscillation
adjustment output pin.

Input pin to request external interruption,
non-maskable interruption and for serial chip select
(CH0). Active when falling edge.

Serial clock (CH1) I/O pin.

Serial data (CH1) output pin.

Serial data (CH1) input pin.

(Port I)
8-bit I/O port.
Enable to
specify I/O by
bit unit.
(8 pins)

Connecting pin of crystal oscillator for system clock.
When supplying the external clock, input the external clock to EXTAL
pin and input opposite phase clock to XTAL pin.

Connecting pin of crystal oscillator for 32kHz timer clock.
When used as event counter, input to TEX pin and leave TX pin open.
(Feedback resistor is not removed.)

System reset pin of active "L" level.

Microprocessor mode input pin. Always connect to GND.

FDP voltage supply pin when specifying internal resistor by mask
option.

Positive power supply pin of A/D converter.

Reference voltage input pin of A/D converter.

GND pin of A/D converter.

Positive power supply pin.

GND pin. Connect both Vss pins to GND.

Symbol

I/O

Description

CXP88216/88220/88224

PPO data

Data bus

RD (Port A)

Port A direction

Port A data

Input
protection
circuit

(Every bit)

Port A

1 pin

Hi-Z

When reset

PA0/PPO0/HGO

PA1/PPO1

PA2/PPO2

PA4/PPO4

Port A

3 pins

Hi-Z

PA5/PPO5

PA7/PPO7

Input/Output Circuit Formats for Pins

Port A

Circuit format

Data bus

RD (Port A)

PA0

Data bus

RD (Port A)

PA1 direction

PA0

Input
protection
circuit

(Every bit)

PPO1

PPG control status
register bit 0
Tri-state control selection

PPO1

MPX

PPO0

HOUT

HSEL

HOUTE

HSEL

Output becomes active from high impedance
by data writing to port register.

PPO data

Data bus

Output becomes active from high impedance
by data writing to port register.

Port A data

RD (Port A)

CXP88216/88220/88224

Data bus

Port B data

RD (Port B)

Port B tri-state
control

Port C

1 pin

8 pins

Hi-Z

PB0

PB7

PC3/RTO4

PC0

PC2

Port C

3 pins

1 pin

Hi-Z

PC3/RTO3

Port B

Data bus

RD (Port C)

PC3 direction

PC3

Input
protection
circuit

(Every bit)

Data bus

RD (Port C)

RTO3

Data bus

RD (Port C)

PC4 direction

PC4

Input
protection
circuit

(Every bit)

Data bus

RD (Port C)

RTO4

RTG interruption
control register bit 7
Tri-state control selection

RTO4

Data bus

RD (Port C)

Port C direction

Port C data

Input
protection
circuit

(Every bit)

When reset

Circuit format

CXP88216/88220/88224

RTO data

Data bus

RD (Port C)

Port C direction

Port C data

Input
protection
circuit

(Every bit)

Port D

8 pins

3 pins

Hi-Z

PC5/RTO5

PC7/RTO7

T8/S15

T15/S8

PD0/S0

PD7/S7

8 pins

Hi-Z

T0 to T7

Port C

Output selection control signal
("0" when reset)

Mask option

Timing output data

FDP

Pull-down resistor

High voltage drive
transistor

Output selection control signal
("0" when reset)

Mask option

Timing output data

FDP

Pull-down resistor

High voltage drive
transistor

Segment output data

Output selection control signal
("0" when reset)

Mask option

Data bus

RD (Port D)

Port D data

Segment output data

FDP

Pull-down resistor

High voltage drive
transistor

When reset

Circuit format

CXP88216/88220/88224

Port F data

Data bus

RD (Port F)

Port F direction

MPX

SCK1 output enable

From serial interface

To serial interface

Schmitt input

2 pins

Hi-Z

PE0/INT0
PE1/EC0/INT2

PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1

4 pins

2 pins

Hi-Z

High level

PE6/DAB0
PE7/DAB1

MPX

Data bus

DA gate output

Hi-Z control

Port E data

Port E function
select

RD (Port E)

Data bus

RD (Port E)

DA gate output or
PWM output

Hi-Z control

MPX

Port E data

Port E function
select

RD (Port E)

Data bus

Schmitt input

Port E

PF0/AN4

PF3/AN7

RD (Port F)

Data bus

Input multiplexer

To A/D converter

Port F function select

4 pins

PF4/SCK1

Port F

Port E

Port F

When reset

Circuit format

CXP88216/88220/88224

MPX

Port F data

Data bus

RD (Port F)

Port F direction

Port F output selection

From serial interface

To serial interface

Port F

Port G

8 pins

1 pin

Hi-Z

PF5/SO1

PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL/
EC1
PG4/SYNC0/
EC2
PG5/SYNC1
PG6/EXI0
PG7/EXI1

PF6/SI1

1 pin

Hi-Z

PF7

Port F

To serial interface

Port F data

Data bus

RD (Port F)

Port F direction

RD (Port G)

Data bus

Schmitt input

Note) For PG4/SYNC and PG5/SYNC1, CMOS schmitt input or TTL schmitt input can be
selected with the mask option.

To serial interface

Port F data

Data bus

RD (Port F)

Port F direction

Schmitt input

When reset

Circuit format

CXP88216/88220/88224

MPX

Port I data

Data bus

RD (Port I)

Port I direction

Port I function
select

PI2: From 14-bit PWM,
timer/counter
PI3: From CTL duty detection
circuit, 32kHz timer

Port I

Port H

3 pins

2 pins

Hi-Z

PI2/PWM
PI3/TO/
DDO/ADJ

PH0/KR0

PH2/KR2

PI1/RMC
PI4/INT1/
NMI/CS0
PI7/SI0

3 pins

2 pins

Hi-Z

PI5/SCK0
PI6/SO0

Port I

MPX

Port I data

Data bus

RD (Port I)

Port I direction

Port I function
select

MPX

To SI0

From
serial CH0

Note)
P15 is schmitt input

Schmitt input

Key input signal

Port H data

Data bus

RD (Port H)

Port H direction

Port I data

Data bus

RD (Port I)

Port I direction

PI1: To remote control circuit
PI4: To interruption circuit
PI3: To serial CH0

When reset

Circuit format

CXP88216/88220/88224

and V

should be set to a same voltage.

and V

OUT

should not exceed V

+ 0.3V.

It specifies output current of general-purpose I/O port.

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

better take place under the recommended operating conditions. Exceeding those conditions may

adversely affect the reliability of the LSI.

Supply voltage

Input voltage

Output voltage

Display output voltage

High level output current

High level total
output current

Low level output current

Low level total output current

Operating temperature

Storage temperature

Allowable power dissipation

OUT

ODH1

ODH2

ODH

Topr

Tstg

0.3 to +7.0

AVss to +7.0

0.3 to +0.3

0.3 to +7.0

40 to V

+ 0.3

100

130

20 to +75

55 to +150

600

°C

As P-channel transistor is open drain,
V

is reference.

All pins excluding display outputs
(value per pin)

Display outputs S0 to S7 (value per pin)

Display outputs T0 to T7,
and T8/S15 to T15/S8 (value per pin)

Total for all pins excluding display outputs

Total for all display outputs

Total for all outputs

Item

Symbol

Rating

Unit

Remarks

Absolute Maximum Ratings

(Vss = 0V)

CXP88216/88220/88224

Analog power supply

High level input voltage

Low level input voltage

Operating temperature

Supply voltage

5.5

+ 0.3

0.3V

0.2V

0.8

0.4

+75

°C

Item

Symbol

Min.

Max.

Unit

Remarks

4.5

3.5

2.7

2.5

4.5

0.7V

0.8V

2.2

0.4

0.3

IHS

IHTS

IHEX

ILS

ILTS

ILEX

Topr

Guaranteed range during high speed mode
(1/2 dividing clock) operation

Guaranteed range during low speed mode
(1/16 dividing clock) operation

Guaranteed operation range by TEX clock

Guaranteed data hold operation range
during STOP

CMOS schmitt input

TTL schmitt input

EXTAL pin

TEX pin

CMOS schmitt input

TTL schmitt input

EXTAL pin

TEX pin

and V

should be set to a same voltage.

Normal input port (each pin of PA1 to PA4, PC, PF0 to PF3, PF5, PF7, PH, PI2, PI3 and PI6), MP pin

Each pin of RST, PE0/INT0, PE1/EC0/INT2, PF4/SCK1, PF6/SI1, PI1/RMC, PI4/CS0/NMI/INT1, PI5/SCK0,

PI7/SI1 and PG (For PG4 and PG5, when CMOS schmitt input is selected with mask option)

Each pin of PG4 and PG5 (When TTL schmitt input is selected with mask option)

It specifies only when the external clock is input.

It specifies only when the external event is input.

Recommended Operating Conditions

(Vss = 0V)

CXP88216/88220/88224

= 4.5V, I

= 0.5mA

= 4.5V, I

= 1.2mA

= 4.5V, I

= 1.8mA

= 4.5V, I

= 3.6mA

= 4.5V,

= V

2.5V

= 5.5V,

= V

35V

FDP

= V

35V

= 5V,

FDP

= 30V

= 5.5V, V

= 5.5V

= 5.5V, V

= 0.4V

= 5.5V, V

= 5.5V

= 5.5V,

= 0.4V

= 5.5V, V

= 0, 5.5V

16MHz crystal oscillation (C

= C

= 15pF),

= 5V ± 10%

16MHz crystal oscillation (C

= C

= 15pF),

= 5V ± 10%, SLEEP mode

32kHz crystal oscillation (C

= C

= 47pF),

= 3V ± 10%

32kHz crystal oscillation (C

= C

= 47pF),

= 3V ± 10%, SLEEP mode

= 5.5V, STOP mode

(32kHz, 16MHz oscillation stop)

Clock 1MHz
0V other than the measured pins

High level
output voltage

Low level
output voltage

Display
output current

Open drain
output leakage
current (P-CH
Tr OFF in

Pull-down
resistor

Input
current

I/O leakage
current

Supply
current

Input
capacity

4.0

3.5

0.5

0.1

1.5

µA

PA to PC, PE
PF4 to PF7,
PH,
PI1 to PI7,
RST

only)

S0 to S7

S8/T15 to
S15/T8,
T0 to T7

S0 to S7,
S8/T15 to
S15/T8,
T0 to T7

EXTAL

TEX

RST

PA to PC,
PE to PI,
AN1 to AN3,
MP,
RST

, Vss

Other than
S0 to S15,
T0 to T7,
PA0,
PA5 to PA7
PE2 to PE7
PB, V

, Vss

, AVss

Item

Symbol

Condition

Min.

LOL

IHE

ILE

ILR

DD1

DDS1

DD2

DDS2

DDS3

100

1.2

Typ.

0.4

0.6

270

400

±10

100

Max.

Unit

DC Characteristics

(Ta = 20 to +75°C, Vss = 0V)

CXP88216/88220/88224

RST pin is specified when evaluation mode is in use.

RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current

when non-resistor is selected.

When built-in pull-down resistor is selected with mask option.

When entire output pins are open.

When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 0002FE

) to "00"

and operating in high speed mode (1/2 dividing clock).

sys indicates three values according to the contents of the clock control register (address; 00FE

) upper

2 bits (CPU clock selection).

sys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

EXTAL

XTAL

0.4V

1/fc

External clock

EXTAL

XTAL

74HC04

Crystal oscillation
Ceramic oscillation

EXTAL

XTAL

32kHz clock applying condition
Crystal oscillation

TEX

AC Characteristics

(1) Clock timing

System clock frequency

System clock input pulse width

System clock input rise and
fall times

Event count clock input
pulse width

Event count clock input
rise and fall times

System clock frequency

Event count clock input
pulse width

Event count clock input
rise and fall times

XTAL
EXTAL

EC0, EC1,
EC2

TEX
TX

TEX

MHz

kHz

µs

Item

Symbol

Condition

Unit

Fig. 1, Fig. 2

Fig. 1, Fig. 2
External clock drive

Fig. 3

= 2.7 to 5.5V

Fig. 2 (32kHz clock
applying condition)

Fig. 3

Typ.

32.768

Min.

sys

+ 200

Max.

200

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V)

Fig. 1. Clock timing

Fig. 2. Clock applying condition

CXP88216/88220/88224

Input mode

Output mode

Input mode

Output mode

SCK0 input mode

SCK0 output mode

SCK0 input mode

SCK0 output mode

SCK0 input mode

SCK0 output mode

Chip select transfer mode
(SCK0 = output mode)

Chip select transfer mode

Note 1)

sys indicates three values according to the contents of the clock control register (address; 00FE

)

upper 2 bits (CPU clock selection).

sys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL.

(2) Serial transfer (CH0)

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V)

Item

CS0

SCK0

delay time

CS0

SCK0

floating delay time

CS0

SO0

delay time

CS0

SO0

floating delay time

CS0
high level width

SCK0
cycle time

SCK0
high and low level widths

SI0 input set-up time
(against SCK0

)

SI0 input hold time
(against SCK0

)

SCK0

SO0 delay time

DCSK

DCSKF

DCSO

DCSOF

WHCS

KCY

SIK

KSI

KSO

SCK0

SO0

CS0

SCK0

SI0

SO0

Symbol

Min.

sys + 200

tsys + 200

sys + 200

16000/fc

sys+100

8000/fc 50

100

200

sys + 200

100

sys + 200

100

Max.

Unit

Condition

TEX
EC0
EC1
EC2

0.2V

0.8V

Fig. 3. Event count clock timing

CXP88216/88220/88224

Serial transfer (CH1)

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V)

Item

Symbol

Min.

Max.

Unit

Condition

SCK1 cycle time

SCK1 high and low
level widths

SI1 input set-up time
(against SCK1

)

SI1 input hold time
(against SCK1

)

SCK1

SO1 delay time

KCY

SIK

KSI

KSO

SCK1

SI1

SO1

Input mode

Output mode

Input mode

Output mode

SCK1 input mode

SCK1 output mode

SCK1 input mode

SCK1output mode

SCK1 input mode

SCK1 output mode

1000

16000/fc

400

8000/fc 50

100

200

100

200

100

Note) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.

Fig. 5. Serial transfer CH1 timing

SCK1

SI1

SO1

KCY

0.2V

0.8V

SIK

KSI

KSO

Input data

Output data

0.2V

0.8V

0.2V

0.8V

CXP88216/88220/88224

Conversion time

Sampling time

Reference input voltage

Analog input voltage

CONV

SAMP

REF

IAN

REF

Only for A/D converter
operation
Ta = 25°C
V

= AV

REF

5.0V

Operation mode
AV

REF

= 4.0 to 5.5V

SLEEP mode
STOP mode
32kHz operation mode

Linearity error

Absolute error

Resolution

REF

current

REF

µs

REF

1.0

µA

0.6

160/f

ADC

12/f

ADC

0.5

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Bits

(3) A/D converter characteristics

(Ta = 20 to +75°C, V

= AV

= 4.5 to 5.5V, AV

REF

= 4.0 to AV

, Vss = AVss =

±1

±2

LSB

Analog input

Linearity error

Digital conversion value

Fig. 6. Definitions of A/D converter terms

REF

AN0 to AN7

= AV

= 4.5 to 5.5V

The value of f

ADC

is as follows by selecting ADC

operation clock (MSC: Address 01FE

bit 0).

When PS2 is selected, f

ADC

= fc/2

When PS1 is selected, f

ADC

= fc

CXP88216/88220/88224

External interruption high and
low level widths

Reset input low level width

INT0
INT1
INT2
NMI

RST

32/fc

µs

Item

Symbol

Condition

Min.

Max.

Unit

RSL

(4) Interruption, reset input

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V)

0.2V

0.8V

INT0

INT1

INT2

NMI

(Falling edge)

Fig. 7. Interruption input timing

RSL

0.2V

RST

Fig. 8. Reset input timing

(5) Others

(Ta = 20 to +75°C, V

= 4.5 to 5.5V, Vss = 0V)

Item

CFG input high and
low level widths

DFG input high and
low level widths

DPG minimum pulse width

DPG minimum removal time

PBCTL input high and low
level widths

EXI input high and low level
widths

CFH

CFL

DFH

DFL

DPW

rem

CTH

CTL

EIH

EIL

CFG

DFG

DPG

PBCTL

EXI0
EXI1

Symbol

Min.

FRC

24 + 200

FRC

16 + 200

FRC

8 + 200

FRC

16 + 200

FRC

8 +

sys + 200

FRC

8 +

sys + 200

Max.

Unit

sys = 2000/fc

Condition

Note 1)

sys indicates three values according to the contents of the clock control register (address; 00FE

)

upper 2 bits (CPU clock selection).

sys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2)

FRC

= 1000/fc (ns)

CXP88216/88220/88224

Supplement

Fig.10. Recommended oscillation circuit

EXTAL

XTAL

(i)

TEX

(ii)

Manufacturer

RIVER
ELETEC
CO., LTD.

KINSEKI LTD.

Model

HC-49/U03

HC-49/U (-S)

fc (MHz)

8.00

10.00

12.00

16.00

8.00

10.00

12.00

16.00

32.768kHz

16 (12)

470k

(pF) C

(pF) Rd

(

) Circuit

example

(i)

(ii)

In PG4/SYNC0/EC2 pin and PG5/SYNC1 pin, the input circuit format can be selected every pin.

Item

Content

Reset pin pull-up resistor

High voltage drive output port pull-down resistor

Input circuit format

Non-existent

CMOS schmitt

Existent

TTL schmitt

Mask option table

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXP88224

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CXP88224