1
ICX055AL
E92832F66-ST
1/3-inch CCD Image Sensor for CCIR B/W Camera
Description
The ICX055AL is an interline CCD solid-state
image sensor suitable for CCIR 1/3-inch B/W video
cameras. High sensitivity is achieved through the
adoption of HAD (Hole-Accumulation Diode) sensors.
This chip features a field period readout system,
and an electronic shutter with variable charge-
storage time.
Features
High sensitivity (+3dB compare with ICX045BLA)
and low dark current
Continuous variable-speed shutter
1/50s (Typ.), 1/120s to 1/10000s
Low smear
Excellent antiblooming characteristics
Horizontal register: 5V drive
Reset gate:
5V drive
Device Structure
Optical size:
1/3-inch format
Number of effective pixels: 500 (H)
582 (V) approx. 290K pixels
Number of total pixels:
537 (H)
597 (V) approx. 320K pixels
Interline CCD image sensor
Chip size:
6.00mm (H)
4.96mm (V)
Unit cell size:
9.8m (H)
6.3m (V)
Optical black:
Horizontal (H) direction: Front 7 pixels, Rear 30 pixels
Vertical (V) direction:
Front 14 pixels, Rear 1 pixel
Number of dummy bits:
Horizontal 16
Vertical
1 (even field only)
Substrate material:
Silicon
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
16 pin DIP (Plastic)
Pin 1
V
7
30
1
14
Pin 9
H
Optical black position
(Top View)
For the availability of this product, please contact the sales office.
2
ICX055AL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Note
Note) : Photo sensor
V
OUT
V
SS
V
GG
GND
V
1
V
2
V
3
V
4
V
DD
GND
SUB
V
L
RG
NC
H
1
H
2
Horizontal register
Vertical register
Substrate voltage SUB GND
V
DD
, V
OUT
, V
SS
GND
Supply voltage
V
DD
, V
OUT
, V
SS
SUB
V
1
, V
2
, V
3
, V
4
GND
Vertical clock input voltage
V
1
, V
2
, V
3
, V
4
SUB
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
H
1
, H
2
V
4
H
1
, H
2
, RG, V
GG
GND
H
1
, H
2
, RG, V
GG
SUB
V
L
SUB
V
1
, V
2
, V
3
, V
4
, V
DD
, V
OUT
V
L
RG V
L
V
GG
, Vss, H
1
, H
2
V
L
Storage temperature
Operating temperature
Pin No.
Symbol
Description
Pin No.
Symbol
Description
1
2
3
4
5
6
7
8
V
4
V
3
V
2
V
1
GND
V
GG
V
SS
V
OUT
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
Output amplifier gate bias
Output amplifier source
Signal output
9
10
11
12
13
14
15
16
V
DD
GND
SUB
V
L
RG
NC
H
1
H
2
Output amplifier drain supply
GND
Substrate (Overflow drain)
Protective transistor bias
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
Pin Description
Item
0.3 to +55
0.3 to +18
55 to +10
15 to +20
to +10
to +15
to +17
17 to +17
10 to +15
55 to +10
65 to +0.3
0.3 to +30
0.3 to +24
0.3 to +20
30 to +80
10 to +60
V
V
V
V
V
V
V
V
V
V
V
V
V
V
C
C
1
Ratings
Unit
Remarks
Absolute Maximum Ratings
*
1
+27V (Max.) when clock width<10s, clock duty factor<0.1%.
Block Diagram and Pin Configuration
(Top View)
3
ICX055AL
Item
V
DD
V
GG
V
SS
V
SUB
V
SUB
V
RGL
V
RGL
V
L
14.55
1.75
9.0
3
1.0
3
15.0
2.0
2
15.45
2.25
18.5
+3
4.0
+3
V
V
V
%
V
%
5%
1
1
Symbol
Min.
Typ.
Max.
Unit
Remarks
Bias Conditions
DC Characteristics
Grounded with
680
resistor
Item
Output amplifier drain current
Input current
Input current
I
DD
I
IN1
I
IN2
3
1
10
mA
A
A
3
4
Symbol
Min.
Typ.
Max.
Unit
Remarks
Output amplifier drain voltage
Output amplifier gate voltage
Output amplifier source
Substrate voltage adjustment range
Fluctuation range after substrate voltage adjustment
Reset gate clock voltage adjustment range
Fluctuation range after reset gate clock voltage adjustment
Protective transistor bias
1
Indications of substrate voltage (V
SUB
) reset gate clock voltage (V
RGL
) setting value.
The setting values of substrate voltage and reset gate clock voltage are indicated on the back of the image
sensor by a special code. Adjust substrate voltage (V
SUB
) and reset gate clock voltage (V
RGL
) to the
indicated voltage. Fluctuation range after adjustment is 3%.
V
SUB
code one character indication
V
RGL
code one character indication
V
RGL
code V
SUB
code
Code and optimal setting correspond to each other as follows.
1
V
RGL
code
Optimal setting
1.0 1.5 2.0 2.5 3.0 3.5 4.0
2
3
4
5
6
7
V
SUB
code
Optimal setting
9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0
E
f
G
h
J
K
L
m
N
P
Q
R
S
T
U
V
W
X
Y
Z
<Example> "5L"
V
RGL
= 3.0V
V
SUB
= 12.0V
2
V
L
setting is the V
VL
voltage of the vertical transfer clock waveform.
3
1) Current to each pin when 18V is applied to V
DD
, V
OUT
, Vss and SUB pins, while pins that are not tested
are grounded.
2) Current to each pin when 20V is applied sequentially to V
1
, V
2
, V
3
and V
4
pins, while pins that are
not tested are grounded. However, 20V is applied to SUB pin.
3) Current to each pin when 15V is applied sequentially to RG, H
1
, H
2
and V
GG
pins, while pins that are
not tested are grounded. However, 15V is applied to SUB pin.
4) Current to V
L
pin when 30V is applied to V
1
, V
2
, V
3
, V
4
, V
DD
and V
OUT
pins or when, 24V is applied
to RG pin or when, 20V is applied to V
GG
, Vss, H
1
and H
2
pins, while V
L
pin is grounded. However,
GND and SUB pins are left open.
4
Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are grounded.
18.5
4
ICX055AL
Item
Readout clock voltage
V
VT
V
VH1
, V
VH2
V
VH3
, V
VH4
V
VL1
, V
VL2
,
V
VL3
, V
VL4
V
V
|V
VH1
V
VH2
|
V
VH3
V
VH
V
VH4
V
VH
V
VHH
V
VHL
V
VLH
V
VLL
V
H
V
HL
V
RG
V
RGLH
V
RGLL
V
SUB
14.55
0.05
0.2
9.0
7.8
0.25
0.25
4.75
0.05
4.5
22.5
15.0
0
0
8.5
8.5
5.0
0
5.0
23.5
15.45
0.05
0.05
8.0
9.05
0.1
0.1
0.1
0.5
0.5
0.5
0.5
5.25
0.05
5.5
0.8
24.5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
2
2
2
2
2
2
2
2
2
2
2
3
3
4
4
5
V
VH
= (V
VH1
+ V
VH2
) /2
V
VL
= (V
VL3
+ V
VL4
) /2
V
V
= V
VH
n V
VL
n (n = 1 to 4)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
1
Low-level coupling
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock voltage
Vertical transfer clock
voltage
Symbol
Min.
Typ.
Max.
Unit
Waveform
diagram
Remarks
1
The reset gate clock voltage need not be adjusted when reset gate clock is driven when the specifications
are as given below. In this case, the reset gate clock voltage setting indicated on the back of the image
sensor has not significance.
Item
Reset gate clock
voltage
Symbol
V
RGL
V
RG
0.2
8.5
0
9.0
0.2
9.5
V
V
4
4
Min.
Typ.
Max.
Unit
Waveform
diagram
Remarks
Clock Voltage Conditions
5
ICX055AL
Clock Equivalent Circuit Constant
Item
Capacitance between vertical transfer
clock and GND
C
V1
, C
V3
C
V2
, C
V4
C
V12
, C
V34
C
V23
, C
V41
C
V13
C
V24
C
H1
, C
H2
C
HH
C
RG
C
SUB
R
1
, R
3
R
2
, R
4
R
GND
R
H
R
RG
1500
820
470
230
150
230
47
47
5
320
51
100
15
10
40
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Capacitance between vertical transfer
clocks
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
Reset gate clock series resistor
Symbol
Min.
Typ.
Max.
Unit
Remarks
R
H
R
H
H
2
H
1
C
H1
C
H2
C
HH
V
1
C
V12
V
2
V
4
V
3
C
V34
C
V23
C
V41
C
V13
C
V24
C
V1
C
V2
C
V4
C
V3
R
GND
R
4
R
1
R
3
R
2
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
R
RG
RG
C
RG
Reset gate clock equivalent circuit
Capacitance between horizontal
transfer clock and GND
Capacitance between horizontal
transfer clocks
Capacitance between reset gate clock
and GND
Capacitance between substrate clock
and GND
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