Description
The ICX208AK is an interline CCD solid-state image
sensor suitable for NTSC color video cameras.
Compared with the current product ICX068AK,
sensitivity and saturation signal are improved drastically
through the adoption of Super HAD CCD technology.
High resolution is achieved through the use of Ye,
Cy, Mg, and G complementary color mosaic filters.
This chip features a field period readout system and
an electronic shutter with variable charge-storage time.
The package is a 10mm-square 14-pin DIP (Plastic).
Features
High sensitivity (+4dB compared with ICX068AK)
High saturation signal
(+2.5dB compared with ICX068AK)
Horizontal register:
3.3 to 5.0V drive
Reset gate:
3.3 to 5.0V drive
No voltage adjustment
(Reset gate and substrate bias are not adjusted.)
High resolution, low smear and low dark current
Excellent antiblooming characteristics
Continuous variable-speed shutter
Recommended range of exit pupil distance: 20 to 100mm
Ye, Cy, Mg, and G complementary color mosaic filters on chip
Device Structure
Interline CCD image sensor
Image size:
Diagonal 4.5mm (Type 1/4)
Number of effective pixels:
768 (H)
494 (V) approx. 380K pixels
Total number of pixels:
811 (H)
508 (V) approx. 410K pixels
Chip size:
4.47mm (H)
3.80mm (V)
Unit cell size:
4.75m (H)
5.55m (V)
Optical black:
Horizontal (H) direction: Front 3 pixels, rear 40 pixels
Vertical (V) direction:
Front 12 pixels, rear 2 pixels
Number of dummy bits:
Horizontal 22
Vertical 1 (even fields only)
Substrate material:
Silicon
1
ICX208AK
E97136C99
Diagonal 4.5mm (Type 1/4) CCD Image Sensor for NTSC Color Video Cameras
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
14 pin DIP (Plastic)
Pin 1
V
3
40
2
12
Pin 8
H
Optical black position
(Top View)
Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing
newly developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor.
2
ICX208AK
Block Diagram and Pin Configuration
(Top View)
5
6
7
9
10
11
13
Note)
Note) : Photo sensor
V
O
U
T
G
N
D
V
1
V
2
V
3
V
4
V
D
D
G
N
D
S
U
B
V
L
R
G
H
1
H
2
Horizontal Register
2
3
4
N
C
12
Cy
Cy
Mg
G
Cy
14
Mg
Ye
Ye
Mg
Ye
G
Cy
Cy
G
G
Cy
Mg
Ye
Ye
Mg
Mg
Ye
G
8
1
V
e
r
t
i
c
a
l
R
e
g
i
s
t
e
r
G
Pin No.
1
2
3
4
5
6
7
V
4
V
3
V
2
V
1
NC
GND
V
OUT
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
Signal output
8
9
10
11
12
13
14
V
DD
GND
SUB
V
L
RG
H
1
H
2
Supply voltage
GND
Substrate clock
Protective transistor bias
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
Symbol
Description
Pin No.
Description
Pin Description
Symbol
Absolute Maximum Ratings
1
+24V (Max.) when clock width < 10s, clock duty factor < 0.1%.
Against
SUB
Against GND
Against V
L
Between input clock
pins
Storage temperature
Operating temperature
40 to +8
50 to +15
50 to +0.3
40 to +0.3
0.3 to +18
10 to +18
10 to +6
0.3 to +28
0.3 to +15
to +15
5 to +5
13 to +13
30 to +80
10 to +60
V
V
V
V
V
V
V
V
V
V
V
V
C
C
V
DD
, V
OUT
, RG
SUB
V
1
, V
3
SUB
V
2
, V
4
, V
L
SUB
H
1
, H
2
, GND
SUB
V
DD
, V
OUT
, RG GND
V
1
, V
2
, V
3
, V
4
GND
H
1
, H
2
GND
V
1
, V
3
V
L
V
2
, V
4
, H
1
, H
2
, GND V
L
Voltage difference between vertical clock input pins
H
1
H
2
H
1
, H
2
V
4
Item
Ratings
Unit
Remarks
1
3
ICX208AK
Bias Conditions
Clock Voltage Conditions
Item
Readout clock voltage
V
VT
V
VH1
, V
VH2
V
VH3
, V
VH4
V
VL1
, V
VL2
,
V
VL3
, V
VL4
V
V
V
VH3
V
VH
V
VH4
V
VH
V
VHH
V
VHL
V
VLH
V
VLL
V
H
V
HL
V
RG
V
RGLH
V
RGLL
V
RGL
V
RGLm
V
SUB
14.55
0.05
0.2
8.0
6.3
0.25
0.25
3.0
0.05
3.0
21.0
15.0
0
0
7.0
7.0
3.3
0
3.3
22.0
15.45
0.05
0.05
6.5
8.05
0.1
0.1
0.3
0.3
0.3
0.3
5.25
0.05
5.5
0.4
0.5
23.5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
2
2
2
2
2
2
2
2
2
2
3
3
4
4
4
5
V
VH
= (V
VH1
+ V
VH2
)/2
V
VL
= (V
VL3
+ V
VL4
)/2
V
V
= V
VH
n V
VL
n (n = 1 to 4)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Input through 0.1F
capacitance
Low-level coupling
Low-level coupling
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock voltage
Vertical transfer clock
voltage
Symbol
Min.
Typ.
Max.
Unit
Waveform
diagram
Remarks
DC Characteristics
Item
Supply current
I
DD
4.5
6.5
mA
Symbol
Min.
Typ.
Max.
Unit
Remarks
Item
Supply voltage
Protective transistor bias
Substrate clock
Reset gate clock
V
DD
V
L
SUB
RG
14.55
15.0
1
2
2
15.45
V
Symbol
Min.
Typ.
Max.
Unit
Remarks
1
V
L
setting is the V
VL
voltage of the vertical transfer clock waveform, or the same power supply as the V
L
power supply for the V driver should be used.
2
Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
4
ICX208AK
R
H
R
H
H
2
H
1
C
H1
C
H2
C
HH
V
1
C
V12
V
2
V
4
V
3
C
V34
C
V23
C
V41
C
V13
C
V24
C
V1
C
V2
C
V4
C
V3
R
GND
R
4
R
1
R
3
R
2
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
R
RG
RG
C
RG
Reset gate clock equivalent circuit
Item
Capacitance between vertical transfer
clock and GND
C
V1
, C
V3
C
V2
, C
V4
C
V12
, C
V34
C
V23
, C
V41
C
V13
C
V24
C
H1
, C
H2
C
HH
C
RG
C
SUB
R
1
, R
2
, R
3
, R
4
R
GND
R
H
R
RG
680
470
330
270
82
75
47
47
5
180
82
15
12
39
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Capacitance between vertical transfer
clocks
Capacitance between horizontal
transfer clock and GND
Capacitance between horizontal
transfer clocks
Capacitance between reset gate clock
and GND
Capacitance between substrate clock
and GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
Reset gate clock series resistor
Symbol
Min.
Typ.
Max.
Unit
Remarks
Clock Equivalent Circuit Constant
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