Description
The ICX074AK is a diagonal 8mm (Type 1/2)
interline CCD solid-state image sensor with a
square pixel array which supports VGA format.
Progressive scan allows all pixels signals to be
output independently within approximately 1/60
second. This chip features an electronic shutter with
variable charge-storage time which makes it
possible to realize full-frame still image without a
mechanical shutter. High resolution and high color
reproductivity are achieved through the use of R, G,
B primary color mosaic filters.
Further, high sensitivity and low dark current are
achieved through the adoption of HAD (Hole-
Accumulation Diode) sensors.
This chip is suitable for image input and
processing applications.
Features
Progressive scan allows individual readout of the
image signals from all pixels.
High vertical resolusion (480TV-lines) still picture
without a mechanical shutter.
Square pixel unit cell
VGA format-compatible
R, G, B primary color mosaic filters on chip
High resolution, high color reproductivity, high sensitivity, low dark current
Continuous variable-speed shutter
Low smear
Excellent antiblooming characteristics
Reset gate: 5V drive (bias: no adjustment)
Device Structure
Image size:
Diagonal 8mm (Type 1/2)
Number of effective pixels:
659 (H)
494 (V) approx. 330K pixels
Total number of pixels:
692 (H)
504 (V) approx. 350K pixels
Interline CCD image sensor
Chip size:
8.10mm (H)
6.33mm (V)
Unit cell size:
9.9m (H)
9.9m (V)
Optical black:
Horizontal (H) direction: Front 2 pixels, rear 31 pixels
Vertical (V) direction:
Front 8 pixels, rear 2 pixels
Number of dummy bits:
Horizontal 16
Vertical 5
Substrate material:
Silicon
1
ICX074AK
E95709F99
Diagonal 8mm (Type 1/2) Progressive Scan CCD Image Sensor with Square Pixel for Color Video Cameras
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
22 pin DIP (Cer-DIP)
Pin 1
V
2
31
2
8
Pin 12
H
Optical black position
(Top View)
Wfine CCD is a registered trademark of Sony Corporation.
Represents a CCD adopting progressive scan, primary color filter and square pixel.
2
ICX074AK
Horizontal Register 1
Horizontal Register 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Note)
Note) : Photo sensor
V
O
U
T
2
G
N
D
C
G
G
2
C
G
G
1
V
H
O
L
D
V
1
V
2
H
I
G
1
V
D
D
V
O
G
S
U
B
V
L
R
G
P
O
G
H
1
H
2
V
e
r
t
i
c
a
l
R
e
g
i
s
t
e
r
15
16
17
18
19
20
21
22
H
H
G
1
H
H
G
2
H
I
G
2
V
O
U
T
1
V
3
H
I
S
G
R
G
R
G
R
B
G
B
G
B
G
G
R
G
R
G
R
B
G
B
G
B
G
Block Diagram and Pin Configuration
(Top View)
Pin
No.
Symbol
Description
Description
Pin
No.
Symbol
Pin Description
1
DC bias is applied within the CCD, so that this pin should be grounded externally through a capacitance of
1F or more.
2
Regarding the test pins: apply the same voltage as the supply voltage to HIS, and ground HIG
1
, HIG
2
, and
POG
.
Test pin
2
Test pin
2
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register final
stage accumulation clock
GND
Output amplifier 1 gate
1
decoupling capacitor
Signal output 1
Output amplifier 2 gate
1
decoupling capacitor
Signal output 2
1
2
3
4
5
6
7
8
9
10
11
HIG
1
HIS
V
3
V
2
V
1
VHOLD
GND
C
GG1
V
OUT1
C
GG2
V
OUT2
12
13
14
15
16
17
18
19
20
21
22
V
DD
RG
V
L
SUB
H
1
H
2
HHG
1
HHG
2
HIG
2
POG
VOG
Supply voltage
Reset gate clock
Protective transistor bias
Substrate (overflow drain)
Horizontal register transfer clock
Horizontal register transfer clock
Inter-horizontal register
transfer clock
Inter-horizontal register
transfer clock
Test pin
2
Test pin
2
Vertical register final stage
transfer clock
3
ICX074AK
Item
0.3 to +55
0.3 to +18
55 to +10
15 to +20
to +10
to +15
to +17
17 to +17
10 to +15
55 to +10
65 to +0.3
0.3 to +27.5
0.3 to +22.5
0.3 to +17.5
30 to +80
10 to +60
V
V
V
V
V
V
V
V
V
V
V
V
V
V
C
C
1
Ratings
Unit
Remarks
Absolute Maximum Ratings
1
+27V (Max.) when clock width < 10s, clock duty factor < 0.1%.
Substrate voltage SUB GND
V
DD
, V
OUT1
, V
OUT2
, HIS, C
GG1
, C
GG2
GND
Supply voltage
V
DD
, V
OUT1
, V
OUT2
, HIS, C
GG1
, C
GG2
SUB
V
1
, V
2
, V
3
, VHOLD
,
VOG
GND
Clock input voltage
V
1
, V
2
, V
3
, VHOLD
,
VOG
SUB
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
H
1
, H
2
VOG
H
1
, H
2
GND
H
1
, H
2
SUB
V
L
SUB
V
2
, V
3
, V
DD
, V
OUT1
, V
OUT2
, HIS, HIG
1
, HIG
2
, POG
V
L
RG GND
V
1
, C
GG1
, C
GG2
, H
1
, H
2
, HHG
1
, HHG
2
, VOG
, VHOLD
V
L
Storage temperature
Operating temperature
4
ICX074AK
1
Indications of substrate voltage (V
SUB
) setting value
The setting value of the substrate voltage is indicated on the back of image sensor by a special code.
Adjust the substrate voltage (V
SUB
) to the indicated voltage.
V
SUB
code -- two characters indication
Integer portion
Decimal portion
The integer portion of the code and the actual value correspond to each other as follows.
Item
V
DD
V
SUB
V
L
14.55
9.0
Indicated
voltage 0.1
15.45
18.5
Indicated
voltage + 0.1
15.0
Indicated
voltage
2
V
V
V
1
Symbol
Min.
Typ.
Max.
Unit
Remarks
Bias Conditions
DC Characteristics
Value
9
10 11 12 13 14
15 16 17 18
9
A
C
d
E
f
G
h
J
K
<Example> "A5"
V
SUB
= 10.5V.
2
V
L
setting is the V
VL
voltage of the vertical transfer clock waveform, or the same power supply as the V
L
power supply for the V driver should be used.
3
(1) Current to each pin when 18V is applied to V
DD
, V
OUT1
, V
OUT2,
HIS, RG, C
GG1
, C
GG2
, GND and SUB
pins, while all pins that are not tested are grounded.
(2) Current to each pin when 20V is applied sequentially to V
1
, V
2
and V
3
pins, while all pins that are not
tested are grounded. However, 20V is applied to SUB pin.
(3) Current to each pin when 15V is applied sequentially to RG, H
1
and H
2
pins, while all pins that are not
tested are grounded. However, 15V is applied to SUB pin.
(4) Current to V
L
pin when 25V is applied to V
2
, V
3
, POG
, HIG
1
, HIG
2
, V
DD
, V
OUT1
and V
OUT2
pins or
when, 15V is applied to V
1
, VHOLD
, VOG
, C
GG1
, C
GG2
, H
1
, H
2
, HHG
1
and HHG
2
pins, while V
L
pin is grounded. However, GND and SUB pins are left open.
(5) Current to GND pin when 20V is applied to the RG pin and the GND pin is grounded.
4
Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are grounded.
Supply voltage
Substrate voltage
adjustment range
Substrate voltage
adjustment precision
Protective transistor bias
Item
Supply current
Input current
Input current
I
DD
I
IN1
I
IN2
10
1
10
mA
A
A
3
4
Symbol
Min.
Typ.
Max.
Unit
Remarks
Integer portion of code
5
ICX074AK
Item
V
VT
V
VH02
V
VH1
, V
VH2
, V
VH3
V
VL1
, V
VL2
, V
VL3
V
V
I V
VL1
V
VL3
I
V
VHH
V
VHL
V
VLH
V
VLL
V
H
V
HL
V
RG
V
RGLH
V
RGLL
V
RGH
V
SUB
V
VHOLDH
, V
VOGH
V
VHOLDL
, V
VOGL
V
HHG1H
, V
HHG2H
V
HHG1L
, V
HHG2L
V
HHG1M
, V
HHG2M
14.55
0.05
0.2
8.0
6.8
4.75
0.05
4.5
V
DD
+0.4
21.5
0.05
8.0
4.75
8.0
0.05
15.0
0
0
7.5
7.5
5.0
0
5.0
V
DD
+0.6
22.5
0
7.5
5.0
7.5
0
15.45
0.05
0.05
7.0
8.05
0.1
0.5
0.5
0.5
0.5
5.75
0.05
5.5
0.8
V
DD
+0.8
23.5
0.05
7.0
5.25
7.0
0.05
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
2
2
2
2
2
2
2
2
2
3
3
4
4
4
5
6
6
7
7
7
V
VH
= V
VH02
V
VL
= (V
VL01
+ V
VL03
)/2
V
V
= V
VH
n V
VL
n (n = 1 to 3)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Input through 0.01F
capacitance
Low-level coupling
Readout clock voltage
Vertical transfer clock
voltage
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock voltage
Vertical final stage
accumulation clock voltage
transfer clock voltage
Inter-horizontal register
transfer clock voltage
Symbol
Min.
Typ.
Max.
Unit
Waveform
diagram
Remarks
Clock Voltage Conditions
6
ICX074AK
Clock Equivalent Circuit Constant
Item
C
V1
C
V2
C
V3
C
V12
C
V23
C
V31
C
VHOLD
C
VOG
C
HHG1
C
HHG2
C
H1
C
H2
C
HH
C
RG
C
SUB
R
1
, R
2
, R
3
R
GND
R
H1
R
H2
3300
4700
4700
1000
22
100
19
12
23
19
60
69
40
9
400
10
15
24
30
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Capacitance between vertical transfer
clock and GND
Capacitance between vertical transfer
clocks
Capacitance between vertical final stage
accumulation clock and GND
Capacitance between vertical final stage
transfer clock and GND
Capacitance between inter-horizontal
register transfer clock and GND
Capacitance between horizontal transfer
clock and GND
Capacitance between horizontal transfer
clocks
Capacitance between reset gate clock and
GND
Capacitance between substrate clock and
GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
Symbol
Min.
Typ.
Max.
Unit Remarks
R
H1
R
H2
H
2
C
H1
C
H2
C
HH
V
1
C
V12
V
2
V
3
C
V2
R
GND
R
3
R
1
R
2
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
C
V1
C
v
31
C
v
23
H
1
C
V3
7
ICX074AK
Drive Clock Waveform Conditions
(1) Readout clock waveform
(2) Vertical transfer clock waveform
II
II
100%
90%
10%
0%
V
VT
tr
twh
tf
M
0V
M
2
V
1
V
VH1
V
VH1
V
VHH
V
VHH
V
VH
V
VHL
V
VHL
V
VLH
V
VLH
V
VL1
V
VL1
V
VL01
V
VL
V
VLL
V
VLL
V
3
V
VH3
V
VH3
V
VHH
V
VHH
V
VH
V
VHL
V
VHL
V
VLH
V
VLH
V
VL3
V
VL03
V
VL
V
VLL
V
VLL
V
V1
= V
VH1
V
VL01
V
V2
= V
VH02
V
VL2
V
V3
= V
VH3
V
VL03
V
VH
= V
VH02
V
VL
= (V
VL01
+ V
VL03
)/2
V
2
V
VLH
V
VL2
V
VLL
V
VLH
V
VL2
V
VL
V
VLL
V
VH
V
VHH
V
VH02
V
VHH
V
VH2
V
VHL
V
VH2
V
VHL
8
ICX074AK
(3) Horizontal transfer clock waveform
tr
twh
tf
90%
10%
twl
V
H
V
HL
(4) Reset gate clock waveform
Point A
twl
V
RG
V
RGH
V
RGL
+ 0.5V
V
RGL
V
RGLH
RG waveform
V
RGLL
H
1
waveform
2.5V
twh
tr
tf
V
RGLH
is the maximum value and V
RGLL
is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, V
RGL
is the average value of V
RGLH
and
V
RGLL
.
V
RGL
= (V
RGLH
+ V
RGLL
)/2
Assuming V
RGH
is the minimum value during the interval
t
wh, then:
V
RG
= V
RGH
V
RGL
(5) Substrate clock waveform
90%
100%
10%
0%
V
SUB
tr
twh
tf
M
M
2
V
SUB
9
ICX074AK
(6) Vertical final stage accumulation clock waveform Vertical final stage transfer clock waveform
(7) Inter-horizontal register transfer clock waveform
tf
tr
90%
10%
V
VHOLDL
, V
VOGL
V
VHOLDH
, V
VOGH
VHOLD
, VOG
tf2
tr
10%
V
HHG1L
, V
HHG2L
V
HHG1M
, V
HHG2M
90%
tf1
V
HHG1H
, V
HHG2H
90%
10%
90%
10%
HHG
1
, HHG
2
10
ICX074AK
Readout clock
Vertical transfer
clock
During imaging
During parallel-
serial conversion
Reset gate clock
Substrate clock
Vertical final stage
accumulation/
transfer clock
Inter-horizontal
register transfer
clock
V
T
V
1
,
V
2
, V
3
H
1
H
2
H
1
H
2
RG
SUB
VHOLD
VOG
HHG
1
HHG
2
2.3
24
26
11
1.6
2.5
29
31
13
1.9
26
24
31
29
64
0.5
10
10
0.01
0.01
2
20
20
20
20
17.5
15
0.5
15
0.5
10
10
0.01
0.01
2
20
20
20
20
350
17.5
15
0.5
s
ns
ns
s
ns
s
ns
ns
ns
ns
During
readout
1
2
During drain
charge
H
o
r
i
z
o
n
t
a
l
t
r
a
n
s
f
e
r
c
l
o
c
k
Item
Symbol
twh
twl
tr
tf, tf1, tf2
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Unit
Remarks
Horizontal transfer clock
H
1
, H
2
24
29
ns
3
Item
Symbol
two
Min. Typ. Max.
Unit
Remarks
1
When vertical transfer clock driver CXD1268M is used.
2
tf
tr 2ns, and the cross-point voltage (V
CR
) for the H
1
rising side of the H
1
and H
2
waveforms must be
at least 2.5V.
3
The overlap period for twh and twl of horizontal transfer clocks H
1
and H
2
is two.
Clock Switching Characteristics
11
ICX074AK
Image Sensor Characteristics
(Ta = 25C)
Zone Definition of Video Signal Shading
2
4
494 (V)
5
4
659 (H)
Ignored region
Zone 0
Effective pixel region
Note) All the characteristic data of this image sensor was yielded when the sensor was operated in the 1/60s
interlaced mode.
Measurement System
CCD
C.D.S
S/H
AMP
CCD signal output 1
Signal output 1
[
A]
[
C]
C.D.S
S/H
AMP
CCD signal output 2
Signal output 2
[
B]
[
D]
Note) Adjust the amplifier gain so that the gain between [
A] and [
C], and between [
B] and [
D] equals 1.
Item
G sensitivity
Sensitivity comparison
Saturation signal
Smear
Video signal shading
Uniformity between video
signal channels
Dark signal
Dark signal shading
Lag
Sg
Rr
Rb
Vsat
Sm
SHg
Srg
Sbg
Vdt
Vdt
Lag
200
0.3
0.4
500
300
0.45
0.55
0.002
0.6
0.7
0.007
25
8
8
2
1
0.5
mV
mV
%
%
%
%
mV
mV
%
1
1
1
2
3
4
5
5
6
7
8
Ta = 60C
Zone 0
Ta = 60C
Ta = 60C
Symbol
Min.
Typ.
Max.
Unit
Measurement method
Remarks
R
B
12
ICX074AK
Readout modes
The output methods for the two readout modes indicated below are now described.
Odd field
Even field
1/60s interlaced
1/30s non-interlaced
1. 1/60s interlaced
In this mode, the signals are output in a 1/60s period using the two output pins (V
OUT1
, V
OUT2
).
The signals from two adjacent horizontal lines are simultaneously output from the respective output pins.
The lines output from the output pins are changed over with each field. The V
OUT1
signal after it has passed
through the CDS and other external circuits or the signal produced by adding the V
OUT1
and V
OUT2
signals
accommodate interlaced scanning. In the Odd field, R signal and Gr signal are output from V
OUT1
pin and
Gb signal and B signal are output from V
OUT2
pin. In the Even field, Gb signal and B signal are output from
V
OUT1
pin and R signal and Gr signal are output from V
OUT2
pin.
2. 1/30s non-interlaced
In this mode, the signals are output in a 1/30s period using only one output pin (V
OUT1
).
Unlike the 1/60s interlaced mode described above, the external circuit can be simplified. The imaging
characteristics also differ from those of the other modes. R signal and Gr signal lines and Gb signal and B
signal lines are output sequentially from V
OUT1
pin only.
V
OUT1
V
OUT2
B
R
Gr
Gb
V
OUT1
V
OUT2
B
R
Gr
Gb
V
OUT1
V
OUT2
B
R
Gr
Gb
Composition of color coding and output signal
The color filters of this image sensor are arranged in the layout shown in the figure below.
Gr and Gb denote the G signals on the same line as the R signal and the B signal,
respectively.
Gb
B
Gb
B
R
Gr
R
Gr
Gb
B
Gb
B
R
Gr
R
Gr
13
ICX074AK
Image Sensor Characteristics Measurement Method
Measurement conditions
1) In the following measurements, the substrate voltage is set to the value indicated on the device, and the
device drive conditions are at the typical values of the bias and clock voltage conditions.
2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black (OB) level is used as the reference for the signal output, which is taken as the value of the Gr/Gb
signal output or R/B signal output of signal output 1 in the measurement system.
3) In the following measurements, this image sensor is operated in 1/60s interlaced mode.
Definition of standard imaging conditions
1) Standard imaging condition
I
:
Use a pattern box (luminance 706cd/m
2
, color temperature of 3200K halogen source) as a subject. (Pattern
for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.00mm) as an IR cut filter
and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the
standard sensitivity testing luminous intensity.
2) Standard imaging condition
II
:
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.00mm) as an IR cut filter. The luminous intensity is adjusted
to the value indicated in each testing item by the lens diaphragm.
1. G sensitivity, sensitivity comparison
Set to standard imaging condition
I
. After selecting the electronic shutter mode with a shutter speed of
1/100s, measure the signal outputs (V
Gr
, V
Gb
, V
R
and V
B
) at the center of each Gr, Gb, R and B channel
screens, and substitute the values into the following formula.
V
G
= (V
Gr
+ V
Gb
)/2
Sg = V
G
[mV]
Rr = V
R
/V
G
Rb = V
B
/V
G
2. Saturation signal
Set to standard imaging condition
II
. After adjusting the luminous intensity to 20 times the intensity with the
average value of the Gr signal output, 150mV, measure the minimum values of the Gr, Gb, R and B signal
outputs.
3. Smear
Set to standard imaging condition
II
. With the lens diaphragm at F5.6 to F8, first adjust the average value of
the Gr signal output to 150mV. Measure the average values of the Gr signal output, Gb signal output, R
signal output and B signal output (Gra, Gba, Ra and Ba), and then adjust the luminous intensity to 500 times
the intensity with average value of the Gr signal output, 150mV. After the readout clock is stopped and the
charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value
(Sm1 [mV]) of signal output 1 and the maximum value (Sm2 [mV]) of signal output 2, and substitute the
values into the following formula.
Sm =
100 [%] (1/10V method conversion value)
100
60
1
500
Gra + Gba + Ra + Ba
4
1
10
Sm1 + Sm2
2
14
ICX074AK
4. Video signal shading
Set to standard imaging condition
II
. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so
that the average value of the Gr signal output is 150mV. Then measure the maximum (Grmax [mV]) and
minimum (Grmin [mV]) values of the Gr signal output and substitute the values into the following formula.
SHg = (Grmax Grmin)/150
100 [%]
5. Uniformity between video signal channels
After measuring 4, measure the maximum (Rmax [mV]) and minimum (Rmin [mV]) values of R signal, and
the maximum (Bmax [mV]) and minimum (Bmin [mV]) values of B signal. Substitute the values into the
following formula.
Srg = (Rmax Rmin)/150
100 [%]
Sbg = (Bmax Bmin)/150
100 [%]
6. Dark signal
Measure the average value of the signal output 1 (Vdt [mV]) with the device ambient temperature 60C and
the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
7. Dark signal shading
After measuring 6, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark
signal output 1 and substitute the values into the following formula.
Vdt = Vdmax Vdmin [mV]
8. Lag
Adjust the Gr signal output value generated by strobe light to 150mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following
formula.
Lag = (Vlag/150)
100 [%]
Vlag (lag)
Gr signal output 150mV
Light
FLD
SG
Strobe light
timing
Output
15
ICX074AK
X
H
2
X
H
1
R
G
1
5
V
7
.
5
V
5
V
X
V
2
X
S
G
X
V
1
X
V
3
X
S
U
B
X
V
H
O
L
D
X
H
H
G
1
-
1
X
H
H
G
1
-
2
X
H
H
G
2
-
1
X
H
H
G
2
-
2
X
V
O
G
1
2
3
4
5
6
7
8
9
1
0
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
C
X
D
1
2
6
8
M
C
X
D
1
2
5
0
1
2
3
4
5
6
7
8
9
1
0
2
0
1
9
1
8
1
6
1
5
1
4
1
3
1
2
1
1
1
7
2
2
/
1
6
V
2
2
/
1
6
V
N
.
C
.
N
.
C
.
N
.
C
.
2
2
/
2
0
V
1
0
/
2
0
V
1
/
3
5
V
2
2
/
1
6
V
2
2
/
1
0
V
2
2
/
1
0
V
3
.
3
/
1
6
V
C
C
D
O
U
T
1
C
C
D
O
U
T
2
[
A
]
1
2
3
4
5
6
7
8
9
1
0
1
1
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
I
C
X
0
7
4
(
B
O
T
T
O
M
V
I
E
W
)
HIG
1
HIS
V
3
V
2
GN
D
C
GG
1
V
OU
T1
C
GG
2
V
OU
T2
VO
G
PO
G
HIG
2
HH
G
2
HH
G
1
H
2
H
1
SU
B
V
L
RG
V
DD
1
/
1
0
V
1
/
1
0
V
2
S
K
5
2
3
1
0
0
3
.
9
k
1
0
0
3
.
9
k
2
S
K
5
2
3
3
.
3
/
2
0
V
0
.
0
1
1
M
1
0
0
1
/
2
0
V
1
5
k
4
7
k
1
5
k
3
9
0
.
1
5
6
k
0
.
1
1
/
3
5
V
1
/
3
5
V
2
7
k
2
7
0
k
2
S
C
2
7
8
5
3
1
0
0
k
H
C
0
4
H
C
0
4
0
.
0
1
V
1
VH
OL
D
0
.
1
[
B
]
Drive Circuit
16
ICX074AK
Spectral Sensitivity Characteristics
(Includes lens characteristics, excludes light source characteristics)
Wave Length [nm]
R
e
l
a
t
i
v
e
R
e
s
p
o
n
s
e
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
400
500
600
700
R
G
B
Sensor Readout Clock Timing Chart
1/60s interlaced mode
HD
V1
V3
V2
Odd Field
V1
V3
V2
Even Field
42.5
2.53 2.53
2.94
Unit : s
17
ICX074AK
52
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
3
5
7
7
5
3
1
2
4
6
8
8
6
4
2
49
4
49
3
2
4
8
4
2
49
3
49
4
6
8
6
1
3
7
3
1
5
7
5
26
0
26
1
26
2
26
3
26
4
26
5
27
0
27
5
28
0
28
5
F
L
D
V
D
B
L
K
H
D
V
1
V
2
V
3
C
C
D
O
U
T
1
S
G
C
C
D
O
U
T
2
Drive Timing Chart (Vertical Sync)
1/60s interlaced mode
18
ICX074AK
H
D
B
L
K
C
L
K
V
1
V
2
V
3
V
O
G
V
H
O
L
D
H
H
G
1
H
H
G
2
H
1
H
2
R
G
S
H
P
S
H
D
S
U
B
Drive Timing Chart (Horizontal Sync)
1/60s interlaced mode
19
ICX074AK
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operation as required, and use them.
a) Perform all assembly operations in a clean room (class 1000 or less).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load more
than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited
portions. (This may cause cracks in the package.)
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the
package may fracture, etc., depending on the flatness of the ceramic portions. Therefore, for installation,
use either an elastic load, such as a spring plate, or an adhesive.
Compressive strength
39N
0.9Nm
Upper ceramic
Lower ceramic
29N
Low melting
point glass
29N
Shearing strength
Tensile strength
Torsional strength
20
ICX074AK
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated
voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area,
and indicated values should be transferred to other locations as a precaution.
d) The upper and lower ceramic are joined by low melting point glass. Therefore, care should be taken not
to perform the following actions as this may cause cracks.
Applying repeated bending stress to the outer leads.
Heating the outer leads for an extended period with a soldering iron.
Rapidly cooling or heating the package.
Applying any load or impact to a limited portion of the low melting point glass using tweezers or other
sharp tools.
Prying at the upper or lower ceramic using the low melting point glass as a fulcrum.
Note that the same cautions also apply when removing soldered products from boards.
e) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyano-
acrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives.
(reference)
5) Others
a) Do not expose to strong light (sun rays) for long periods, color filters will be discolored. When high
luminance objects are imaged with the exposure level control by electronic-iris, the luminance of the
image-plane may become excessive and discolor of the color filter will possibly be accelerated. In such a
case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off
mode should be properly arranged. For continuous using under cruel condition exceeding the normal
using condition, consult our company.
b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
21
ICX074AK
Package Outline
Unit: mm
P
A
C
K
A
G
E
S
T
R
U
C
T
U
R
E
0
.
7
3
11
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5
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5
7.5
5
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1
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.
0
0
.
4
15
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0
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15
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4
9
.
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2
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1
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1
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to
9
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0
.
7
1
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0.2
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.
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