Description
The ICX076AK is an interline CCD solid-state
image sensor suitable for NTSC color video
cameras. This device possesses a number of pixels
that is compatible with SIF, and offers excellent cost
performance due to the adoption of an ultra-small
image size and a 10 mm-square 14-pin plastic
package. High sensitivity and low dark current are
achieved through the use of Ye, Cy, Mg, and G
complementary color mosaic filters and through the
adoption of HAD (Hole-Accumulation Diode) sensors.
This chip features a field period readout system
and an electronic shutter with variable charge-
storage time.
Features
High sensitivity and low dark current
Low smear
Excellent antiblooming characteristics
Ye, Cy, Mg, and G complementary color mosaic filters on chip
Horizontal register:
5V drive (drive frequency: 6.75MHz)
Reset gate:
5V drive (no adjustment of bias)
Device Structure
Image size:
Diagonal 3.6mm (Type 1/5)
Number of effective pixels:
362 (H)
492 (V) approx. 180K pixels
Total number of pixels:
381 (H)
506 (V) approx. 190K pixels
Interline CCD image sensor
Chip size:
3.75mm (H)
3.30mm (V)
Unit cell size:
8.10m (H)
4.45m (V)
Optical black:
Horizontal (H) direction: Front 2 pixels, rear 17 pixels
Vertical (V)
direction: Front 12 pixels, rear 2 pixels
Number of dummy bits:
Horizontal 14
Vertical
1 (even fields only)
Substrate material:
Silicon
1
ICX076AK
E95506D99
Diagonal 3.6mm (Type 1/5) CCD Image Sensor for NTSC Color Video Cameras
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Pin 1
V
2
17
2
12
Pin 8
H
Optical black position
(Top View)
14 pin DIP (Plastic)
2
ICX076AK
Symbol
Description
Pin No.
Symbol
Description
1
2
3
4
5
6
7
V
4
V
3
V
2
V
1
C
GG
GND
V
OUT
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Output amplifier gate
1
GND
Signal output
8
9
10
11
12
13
14
V
DD
GND
SUB
V
L
RG
H
1
H
2
Supply voltage
GND
Substrate (overflow drain)
Protective transistor bias
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
: Photo sensor
Note)
V
O
U
T
G
N
D
S
U
B
G
N
D
V
1
V
4
V
3
V
2
V
D
D
R
G
H
1
H
2
V
e
r
t
i
c
a
l
r
e
g
i
s
t
e
r
Horizontal register
Note)
C
G
G
V
L
2
3
4
5
6
7
8
9
10
11
12
13
14
1
Cy
G
Cy
G
Cy
Mg
Ye
Mg
Ye
Mg
Ye
G
Cy
G
Cy
G
Cy
Mg
Ye
Mg
Ye
Mg
Ye
G
Block Diagram and Pin Configuration
(Top View)
Item
0.3 to +55
0.3 to +18
55 to +12
15 to +20
to +12
to +15
to +17
17 to +17
10 to +15
55 to +10
65 to +0.3
0.3 to +27.5
0.3 to +22.5
0.3 to +17.5
30 to +80
10 to +60
V
V
V
V
V
V
V
V
V
V
V
V
V
V
C
C
2
3
Ratings
Unit
Remarks
Absolute Maximum Ratings
2
+27V (Max.) when clock width < 10s, clock duty factor < 0.1%.
3
When C
GG
or GND (Pin 6) are grounded.
0.3 to + 17.5V when C
GG
and GND (Pin 6) are to be disconnected.
Substrate voltage SUB GND
Supply voltage
Clock input
voltage
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
H
1
, H
2
V
4
H
1
, H
2
GND
H
1
, H
2
SUB
V
L
SUB
V
1
, V
3
, V
DD
, V
OUT
V
L
RG GND
V
2
, V
4
, C
GG
, H
1
, H
2
, GND V
L
Storage temperature
Operating temperature
V
DD
, V
OUT
, C
GG
GND
V
DD
, V
OUT
, C
GG
SUB
V
1
, V
2
, V
3
, V
4
GND
V
1
, V
2
, V
3
, V
4
SUB
Pin Description
1
DC bias is applied within the CCD, so that this pin should be grounded externally through a capacitance of
1F or more.
Pin No.
3
ICX076AK
Item
V
DD
V
SUB
V
L
14.25
5.0
Indicated
voltage 0.1
15.0
Indicated
voltage
15.75
12.75
Indicated
voltage + 0.1
V
V
V
1
Symbol
Min.
Typ.
Max.
Unit Remarks
Bias Conditions
2
Supply voltage
Substrate voltage adjustment range
Substrate voltage adjustment precision
Protective transistor bias
1
Indications of substrate voltage (V
SUB
) setting value
The setting value of the substrate voltage is indicated on the back of image sensor by a special code.
Adjust the substrate voltage (V
SUB
) to the indicated voltage.
V
SUB
code one character indication
V
SUB
code
Code and optimal setting correspond to each other as follows.
DC Characteristics
V
SUB
code
5.0
=
5.25
0
5.5
1
5.75
2
6.0
3
6.25
4
6.5
6
6.75
7
7.0
8
7.25
9
7.5
A
7.75
C
8.0
d
8.25
E
V
SUB
code
8.5
f
8.75
G
9.0
h
9.25
J
9.5
K
9.75
L
10.0
m
10.25
N
10.5
P
10.75
R
11.0
S
11.25
U
11.5
V
11.75
W
V
SUB
code
12.0
X
12.25
Y
12.5
Z
12.75
<Example> "L"
V
SUB
= 10.0V
2
V
L
setting is the V
VL
voltage of the vertical transfer clock waveform, or the same power supply as the V
L
power supply for the V driver should be used.
3
1) Current to each pin when 16V is applied to V
DD
, V
OUT
, RG, C
GG
, GND (Pin 6), and SUB pins, while pins
that are not tested are grounded.
2) Current to each pin when 20V is applied sequentially to V
1
, V
2
, V
3
, and V
4
pins, while pins that are
not tested are grounded. However, 20V is applied to SUB pin.
3) Current to each pin when 15V is applied sequentially to H
1
and H
2
pins, while pins that are not tested
are grounded. However, 15V is applied to SUB pin.
4) Current to V
L
pin when 25V is applied to V
1
, V
3
, V
DD
, and V
OUT
pins or when, 15V is applied to V
2
,
V
4
, H
1
, and H
2
pins, while V
L
pin is grounded. However, GND and SUB pins are left open.
5) Current to GND pin when 20V is applied to the RG pin and the GND pin is grounded.
4
Current to SUB pin when 55V is applied to SUB pin, while all pins that are not tested are grounded.
Item
Supply current
Input current
Input current
I
DD
I
IN1
I
IN2
3
5
1
10
mA
A
A
3
4
Symbol
Min.
Typ.
Max.
Unit
Remarks
Optimal setting
Optimal setting
Optimal setting
4
ICX076AK
Item
Readout clock voltage
V
VT
V
VH1
, V
VH2
V
VH3
, V
VH4
V
VL1
, V
VL2
,
V
VL3
, V
VL4
V
V
V
VH3
V
VH
V
VH4
V
VH
V
VHH
V
VHL
V
VLH
V
VLL
V
H
V
HL
V
RG
V
RGLH
V
RGLL
V
RGH
V
SUB
14.25
0.05
0.2
8.5
7.3
0.25
0.25
4.75
0.05
4.5
V
DD
+ 0.3
21.25
15.0
0
0
8.0
8.0
5.0
0
5.0
V
DD
+ 0.6
22.5
15.75
0.05
0.05
7.5
8.55
0.1
0.1
0.3
0.3
0.3
0.3
5.25
0.05
5.5
0.8
V
DD
+ 0.9
23.75
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
2
2
2
2
2
2
2
2
2
2
3
3
4
4
4
5
V
VH
= (V
VH1
+ V
VH2
)/2
V
VL
= (V
VL3
+ V
VL4
)/2
V
V
= V
VH
n V
VL
n
(n = 1 to 4)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Input through 0.01F
capacitance
Low-level coupling
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock voltage
Vertical transfer clock
voltage
Symbol
Min.
Typ.
Max.
Unit
Waveform
diagram
Remarks
Clock Voltage Conditions
5
ICX076AK
Clock Equivalent Circuit Constant
Item
Capacitance between vertical transfer
clock and GND
C
V1
, C
V3
C
V2
, C
V4
C
V12
, C
V34
C
V23
, C
V41
C
V13
, C
V24
C
H1
, C
H2
C
HH
C
RG
C
SUB
R
1
, R
2
, R
3
, R
4
R
GND
R
H
R
RG
520
390
220
150
39
24
18
3
170
100
15
30
39
pF
pF
pF
pF
pF
pF
pF
pF
pF
Capacitance between vertical transfer
clocks
Capacitance between horizontal
transfer clock and GND
Capacitance between horizontal
transfer clocks
Capacitance between reset gate clock
and GND
Capacitance between substrate clock
and GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
Reset gate clock series resistor
Symbol
Min.
Typ.
Max.
Unit
Remarks
R
H
R
H
H
2
H
1
C
H1
C
H2
C
HH
V
1
C
V12
V
2
V
4
V
3
C
V34
C
V23
C
V41
C
V13
C
V24
C
V1
C
V2
C
V4
C
V3
R
GND
R
4
R
1
R
3
R
2
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
Reset gate clock equivalent circuit
C
RG
RG
R
RG
6
ICX076AK
Drive Clock Waveform Conditions
(1) Readout clock waveform
(2) Vertical transfer clock waveform
II
II
100%
90%
10%
0%
V
VT
tr
twh
tf
M
0V
M
2
V
1
V
3
V
2
V
4
V
VHH
V
VH
V
VHL
V
VHH
V
VHL
V
VH1
V
VL1
V
VLH
V
VLL
V
VL
V
VHH
V
VH3
V
VHL
V
VH
V
VHH
V
VHL
V
VL3
V
VL
V
VLL
V
VLH
V
VHH
V
VHH
V
VH
V
VHL
V
VHL
V
VH2
V
VLH
V
VL2
V
VLL
V
VL
V
VHH
V
VHH
V
VHL
V
VH4
V
VHL
V
VH
V
VL
V
VLH
V
VLL
V
VL4
V
VH
= (V
VH1
+ V
VH2
)/2
V
VL
= (V
VL3
+ V
VL4
)/2
V
V
= V
VH
n V
VL
n (n = 1 to 4)
7
ICX076AK
(3) Horizontal transfer clock waveform
tr
twh
tf
90%
10%
twl
V
H
V
HL
(4) Reset gate clock waveform
V
RGLL
V
RGLH
V
RGL
+ 0.5V
V
RGL
twl
V
RG
V
RGH
Point A
RG waveform
H
1
waveform
10%
tr
twh
tf
V
RGLH
is the maximum value and V
RGLL
is the minimum value of the coupling waveform during the period
from Point A in the above diagram until the rising edge of RG. In addition, V
RGL
is the average value of
V
RGLH
and V
RGLL
.
V
RGL
= (V
RGLH
+ V
RGLL
) /2
Assuming V
RGH
is the minimum value during the interval twh, then:
V
RG
= V
RGH
V
RGL
8
ICX076AK
Clock Switching Characteristics
Item
Readout clock
Vertical transfer
clock
Horizontal
transfer clock
Reset gate clock
Substrate clock
V
T
V
1
, V
2
,
V
3
, V
4
H
H
1
H
2
RG
SUB
2.3
55
25
1.5
2.5
67
5.6
34
1.65
55
67
5.6
107
0.5
9
0.007
0.007
8
18
0.5
15
0.5
7
0.007
0.007
5
250
18
0.5
s
ns
ns
s
s
ns
s
During
readout
1
During imaging
During
parallel-serial
conversion
During drain
charge
Symbol
twh
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
twl
tr
tf
Unit
Remarks
1
When vertical transfer clock driver CXD1267 is used. tr and tf are defined by the rise and fall times for 10%
to 90% of the interval between V
VL
and V
VH
.
(5) Substrate clock waveform
90%
100%
10%
0%
V
SUB
tr
twh
tf
M
M
2
V
SUB
9
ICX076AK
8
8
492 (V)
4
4
362 (H)
Zone
II
'
Effective pixel region
Ignored region
Image Sensor Characteristics
(Ta = 25C)
Zone Definition of Video Signal Shading
Measurement System
CCD
C.D.S
LPF1
LPF2
S
H
AMP
CCD signal output
Y signal output
Chroma signal output
(3dB down 4MHz)
(3dB down 1MHz)
S
H
Note) Adjust the amplifier gain so that the gain between [
A] and [
Y], and between [
A] and [
C] equals 1.
[
A]
[
Y]
[
C]
Item
Sensitivity
Saturation signal
Smear
Video signal shading
Uniformity between video
signal channels
Dark signal
Dark signal shading
Flicker Y
Flicker R-Y
Flicker B-Y
Line crawl R
Line crawl G
Line crawl B
Line crawl W
Lag
S
Ysat
Sm
SHy
Sr
Sb
Ydt
Ydt
Fy
Fcr
Fcb
Lcr
Lcg
Lcb
Lcw
Lag
285
700
360
0.007
0.012
25
10
10
2
1
5
5
5
3
3
5
3
0.5
mV
mV
%
%
%
%
mV
mV
%
%
%
%
%
%
%
%
1
2
3
4
5
5
6
7
8
8
8
9
9
9
9
10
Ta = 60C
Zone
II
'
Ta = 60C
Ta = 60C
Symbol
Min.
Typ.
Max.
Unit
Measurement
method
Remarks
10
ICX076AK
Image Sensor Characteristics Measurement Method
Measurement conditions
1) In the following measurements, the substrate voltage is set to the value indicated on the device, and the
device drive conditions are at the typical values of the bias and clock voltage conditions.
2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output, which is taken as the value of Y signal
output or chroma signal output of the measurement system.
Color coding of this image sensor & Composition of luminance (Y) and chroma (color difference) signals
As shown in the left figure, fields are read out. The charge
is mixed by pairs such as A1 and A2 in the A field (pairs
such as B in the B field).
As a result, the sequence of charges output as signals from
the horizontal shift register (Hreg) is, for line A1, (G + Cy),
(Mg + Ye), (G + Cy), and (Mg + Ye).
These signals are processed to form the Y signal and chroma (color difference) signal. The Y signal is formed
by adding adjacent signals, and the chroma signal is formed by subtracting adjacent signals. In other words,
the approximation:
Y = {(G + Cy) + (Mg + Ye)}
1/2
= 1/2 {2B + 3G + 2R}
is used for the Y signal, and the approximation:
R Y = {(Mg + Ye) (G + Cy)}
= {2R G}
is used for the chroma (color difference) signal. For line A2, the signals output from Hreg in sequence are
(Mg + Cy), (G + Ye), (Mg + Cy), (G + Ye).
The Y signal is formed from these signals as follows:
Y = {(G + Ye) + (Mg + Cy)}
1/2
= 1/2 {2B + 3G + 2R}
This is balanced since it is formed in the same way as for line A1. In a like manner, the chroma (color
difference) signal is approximated as follows:
(B Y) = {(G + Ye) (Mg + Cy)}
= {2B G}
In other words, the chroma signal can be retrieved according to the sequence of lines from R Y and (B Y)
in alternation. This is also true for the B field.
Cy
Ye
G
Mg
Cy
Ye
G
Mg
Cy
Ye
G
Mg
Cy
Ye
G
Mg
A1
A2
B
Hreg
Color Coding Diagram
11
ICX076AK
Definition of standard imaging conditions
1) Standard imaging condition
I
:
Use a pattern box (luminance 706cd/m
2
, color temperature of 3200K halogen source) as a subject.
(Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR
cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined
as the standard sensitivity testing luminous intensity.
2) Standard imaging condition
II
:
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted
to the value indicated in each testing item by the lens diaphragm.
1. Sensitivity
Set to standard imaging condition
I
. After selecting the electronic shutter mode with a shutter speed of
1/250s, measure the Y signal (Ys) at the center of the screen and substitute the value into the following
formula.
S = Ys
[mV]
2. Saturation signal
Set to standard imaging condition
II
. After adjusting the luminous intensity to 10 times the intensity with
average value of the Y signal output, 200mV, measure the minimum value of the Y signal.
3. Smear
Set to standard imaging condition
II
. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to
500 times the intensity with the average value of the Y signal output, 200mV. When the readout clock is
stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure
the maximum value (YSm [mV]) of the Y signal output and substitute the value into the following formula.
4. Video signal shading
Set to standard imaging condition
II
. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity
so that the average value of the Y signal output is 200mV. Then measure the maximum (Ymax [mV]) and
minimum (Ymin [mV]) values of the Y signal and substitute the values into the following formula.
SHy = (Ymax Ymin)/200
100 [%]
5. Uniformity between video signal channels
Set to standard imaging condition
II
. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, and then measure the maximum (Crmax, Cbmax [mV]) and minimum (Crmin, Cbmin
[mV]) values of the R Y and B Y channels of the chroma signal and substitute the values into the
following formula.
Sr
= I (Crmax Crmin)/200 I
100 [%]
Sb
= I (Cbmax Cbmin)/200 I
100 [%]
6. Dark signal
Measure the average value of the Y signal output (Ydt [mV]) with the device ambient temperature 60C
and the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
Sm =
100 [%] (1/10V method conversion value)
200
YSm
500
1
10
1
60
250
12
ICX076AK
7. Dark signal shading
After measuring 6, measure the maximum (Ydmax [mV]) and minimum (Ydmin [mV]) values of the Y signal
output and substitute the values into the following formula.
Ydt = Ydmax Ydmin [mV]
8. Flicker
1) Fy
Set to standard imaging condition
II
. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, and then measure the difference in the signal level between fields (
Yf [mV]). Then
substitute the value into the following formula.
Fy = (
Yf/200)
100 [%]
2) Fcr, Fcb
Set to standard imaging condition
II
. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, insert an R or B filter, and then measure both the difference in the signal level between
fields of the chroma signal (
Cr,
Cb) as well as the average value of the chroma signal output (CAr,
CAb). Substitute the values into the following formula.
Fci = (
Ci/CAi)
100 [%] (i = r, b)
9. Line crawls
Set to standard imaging condition
II
. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, and then insert a white subject and R, G, and B filters and measure the difference
between Y signal lines for the same field (
Ylw,
Ylr,
Ylg,
Ylb [mV]). Substitute the values into the
following formula.
Lci = (
Yli/200)
100 [%] (i = w, r, g, b)
10. Lag
Adjust the Y signal output value generated by strobe light to 200mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Ylag). Substitute the value into the following
formula.
Lag = (Ylag/200)
100 [%]
Ylag (lag)
Y signal output 200mV
Light
FLD
SG1
Strobe light
timing
Output
13
ICX076AK
C
C
D
O
U
T
H
1
H
2
C
X
D
1
2
6
7
1
/
1
0
V
0
.
0
1
1
0
0
3
.
9
k
8
V
1
M
2
S
K
5
2
3
I
C
X
0
7
6
(
B
O
T
T
O
M
V
I
E
W
)
H
1
H
2
RG
V
L
SU
B
GN
D
V
DD
V
4
V
3
V
2
V
1
GN
D
C
GG
V
OU
T
2
2
/
1
6
V
3
.
3
/
1
6
V
3
.
3
/
2
0
V
0
.
0
1
1
5
V
V
S
U
B
X
V
2
X
V
1
X
S
G
1
X
V
3
X
S
G
2
X
V
4
R
G
X
S
U
B
2
2
/
2
0
V
1
/
2
0
V
1
0
0
k
0
.
1
1
/
3
5
V
1
0
0
k
0
.
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
1
2
1
3
1
4
1
5
0
0
p
[
A
]
Drive Circuit
14
ICX076AK
700
650
600
550
500
450
400
Wave Length [nm]
R
e
l
a
t
i
v
e
R
e
s
p
o
n
s
e
1.0
0.8
0.6
0.4
0.2
0.0
Ye
Cy
G
Mg
Spectral Sensitivity Characteristics
(excludes lens characteristics and light source characteristics)
Sensor Readout Clock Timing Chart
Unit: s
Odd Field
Even Field
HD
V1
V2
V3
V4
V1
V2
V3
V4
1.6
2.5 2.1
1.3
0.3
38.1
2.5
15
ICX076AK
H
D
V
D
F
L
D
S
G
1
S
G
2
V
1
V
2
V
3
V
4
C
C
D
O
U
T
6
2
4
7
1
3
5
7
5
3
1
9
8
6
4
2
1
0
4
9
1
4
9
2
C
L
P
1
4
9
0
4
9
1
4
9
2
Drive Timing Chart (Vertical Sync)
16
ICX076AK
H
D
S
H
D
H
2
H
1
17
C
L
P
1
V
1
V
2
V
3
V
4
S
U
B
S
H
P
R
G
1
1
10
10
36
2
1
10
20
Drive Timing Chart (Horizontal Sync)
17
ICX076AK
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operation as required, and use them.
a) Perform all assembly operations in a clean room (class 1000 or less).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load more
than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited
portions. (This may cause cracks in the package.)
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the
package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for
installation, use either an elastic load, such as a spring plate, or an adhesive.
Compressive strength
50N
Cover glass
Plastic package
50N
1.2Nm
Torsional strength
18
ICX076AK
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated
voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area,
and indicated values should be transferred to the other locations as a precaution.
d) The notch of the package is used for directional index, and that can not be used for reference of fixing.
In addition, the cover glass and seal resin may overlap with the notch of the package.
e) If the lead bend repeatedly and the metal, etc., clash or rub against the package, the dust may be
generated by the fragments of resin.
f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyano-
acrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference)
5) Others
a) Do not expose to strong light (sun rays) for long periods, color filters will be discolored. When high
luminance objects are imaged with the exposure level control by electronic-iris, the luminance of the
image-plane may become excessive and discolor of the color filter will possibly be accelerated. In such a
case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off
mode should be properly arranged. For continuous using under cruel condition exceeding the normal
using condition, consult our company.
b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
c) The brown stain may be seen on the bottom or side of the package. But this does not affect the CCD
characteristics.
d) This package has 2 kinds of internal structure. However, their package outline, optical size, and strength
are the same.
The cross section of lead frame can be seen on the side of the package for structure A.
Structure A
Structure B
Chip
Metal plate
(lead frame)
Package
Cross section of
lead frame
19
ICX076AK
Package Outline
Unit: mm
P
A
C
K
A
G
E
S
T
R
U
C
T
U
R
E
2.5
7.0
2.5
1
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0.5
5
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4
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7
1
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to
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4
7
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.
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1.7
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2
.
5
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5
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