Description
The ICX084AK is a diagonal 6mm (Type 1/3)
interline CCD solid-state image sensor with a square
pixel array which supports VGA format. Progressive
scan allows all pixels signals to be output
independently within approximately 1/30 second.
This chip features an electronic shutter with variable
charge-storage time which makes it possible to
realize full-frame still image without a mechanical
shutter. High resolution and high color reproductivity
are achieved through the use of R, G, B primary
color mosaic filters. Further, high sensitivity and low
dark current are achieved through the adoption of
HAD (Hole-Accumulation Diode) sensors.
This chip is suitable for applications such as
electronic still cameras, PC input cameras, etc.
Features
Progressive scan allows individual readout of the
image signals from all pixels.
High vertical resolution (480TV-lines) still image
without a mechanical shutter.
Square pixel unit cell
Supports VGA format
Horizontal drive frequency: 12.27MHz
No voltage adjustments
(reset gate and substrate bias are not adjusted.)
R, G, B primary color mosaic filters on chip
High resolution, high color reproductivity, high
sensitivity, low dark current
Continuous variable-speed shutter
1/30 (typ.) to 1/10000s
Low smear
Excellent antiblooming characteristics
Horizontal register: 5V drive
16-pin high precision plastic package (enables dual-
surface standard)
Device Structure
Interline CCD image sensor
Image size:
Diagonal 6mm (Type 1/3)
Number of effective pixels:
659 (H)
494 (V) approx. 330K pixels
Total number of pixels:
692 (H)
504 (V) approx. 350K pixels
Chip size:
5.84mm (H)
4.94mm (V)
Unit cell size:
7.4m (H)
7.4m (V)
Optical black:
Horizontal (H) direction: Front 2 pixels, rear 31 pixels
Vertical (V) direction:
Front 8 pixels, rear 2 pixels
Number of dummy bits:
Horizontal 16
Vertical 5
Substrate material:
Silicon
1
ICX084AK
E95101E99
Diagonal 6mm (Type 1/3) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
16 pin DIP (Plastic)
Pin 1
V
2
31
2
8
Pin 9
H
Optical black position
(Top View)
Wfine CCD is a registered trademark of Sony Corporation.
Represents a CCD adopting progressive scan, primary color filter and square pixel.
2
ICX084AK
Pin No.
Symbol
Description
Pin No.
Symbol
Description
1
2
3
4
5
6
7
8
V
3
V
2
V
1
NC
GND
C
GG
GND
V
OUT
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
Output amplifier gate
1
GND
Signal output
9
10
11
12
13
14
15
16
V
DD
SUBCIR
GND
SUB
V
L
RG
H
1
H
2
Supply voltage
Supply voltage for the substrate
voltage generation
GND
Substrate clock
Protective transistor bias
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
Pin Description
1
2
3
4
5
6
7
8
Note)
Note) : Photo sensor
V
O
U
T
G
N
D
C
G
G
G
N
D
N
C
V
1
V
2
V
3
V
D
D
S
U
B
C
I
R
G
N
D
S
U
B
V
L
R
G
H
1
H
2
Horizontal register
G
B
G
B
R
G
R
G
G
B
G
B
R
G
R
G
G
B
G
B
R
G
R
G
V
e
r
t
i
c
a
l
r
e
g
i
s
t
e
r
10
11
12
13
14
15
16
9
Block Diagram and Pin Configuration
(Top View)
Item
0.3 to +36
0.3 to +18
22 to +9
15 to +16
to +10
to +15
to +16
16 to +16
10 to +15
55 to +10
65 to +0.3
0.3 to +27.5
0.3 to +20.5
0.3 to +17.5
30 to +80
10 to +60
V
V
V
V
V
V
V
V
V
V
V
V
V
V
C
C
2
Ratings
Unit
Remarks
Absolute Maximum Ratings
2
+24V (Max.) when clock width < 10s, clock duty factor < 0.1%.
Substrate clock
SUB GND
V
DD
, V
OUT
, C
GG
, SUBCIR GND
Supply voltage
V
DD
, V
OUT
, C
GG
, SUBCIR
SUB
V
1
, V
2
, V
3
GND
Clock input voltage
V
1
, V
2
, V
3
SUB
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
H
1
, H
2
V
3
H
1
, H
2
GND
H
1
, H
2
SUB
V
L
SUB
V
2
, V
3
V
L
RG GND
V
1
, H
1
, H
2
, GND V
L
Storage temperature
Operating temperature
1
DC bias is applied within the CCD, so that this pin should be grounded externally through a capacitance of
1000pF or more.
3
ICX084AK
Item
V
DD
V
L
SUB
14.55
15.45
15.0
1
2
V
Symbol
Min.
Typ.
Max.
Unit
Remarks
Bias Conditions
DC Characteristics
Supply voltage
Protective transistor bias
Substrate clock
Item
Supply current
I
DD
6
8
mA
Symbol
Min.
Typ.
Max.
Unit
Remarks
Item
Readout clock voltage
V
VT
V
VH02
V
VH1
, V
VH2
, V
VH3
V
VL1
, V
VL2
, V
VL3
V
1
, V
2
, V
3
I V
VL1
V
VL3
I
V
VHH
V
VHL
V
VLH
V
VLL
V
H
V
HL
V
RG
V
RGLH
V
RGLL
V
RGH
V
SUB
14.55
0.05
0.2
8.0
6.8
4.75
0.05
4.5
V
DD
+0.4
21.5
15.0
0
0
7.5
7.5
5.0
0
5.0
V
DD
+0.6
22.5
15.45
0.05
0.05
7.0
8.05
0.1
1.0
2.3
1.0
1.0
5.25
0.05
5.5
0.8
V
DD
+0.8
23.5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
2
2
2
2
2
2
2
2
2
3
3
4
4
4
5
V
VH
= V
VH02
V
VL
= (V
VL1
+ V
VL3
)/2
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Input through 0.01F
capacitance
Low-level coupling
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock voltage
Vertical transfer clock
voltage
Symbol
Min.
Typ.
Max.
Unit
Waveform
diagram
Remarks
Clock Voltage Conditions
1
V
L
setting is the V
VL
voltage of the vertical transfer clock waveform, or the same power supply as the V
L
power supply for the V driver should be used.
2
Set SUBCIR pin to open when applying a DC bias to the substrate clock pin.
4
ICX084AK
Clock Equivalent Circuit Constant
Item
Capacitance between vertical transfer
clock and GND
C
V1
C
V2
C
V3
C
V12
C
V23
C
V31
C
H1
, C
H2
C
HH
C
RG
C
SUB
R
1
, R
2
R
3
R
GND
R
H1
, R
H2
R
RG
560
470
1500
1500
1500
1000
43
39
5
570
20
56
43
10
39
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Capacitance between vertical transfer
clocks
Capacitance between horizontal transfer
clock and GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
Reset gate clock series resistor
Symbol
Min.
Typ.
Max.
Unit
Remarks
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
R
RG
RG
C
RG
Reset gate clock equivalent circuit
R
H1
R
H2
H
2
C
H1
C
H2
C
HH
V
1
C
V12
V
2
V
3
C
V2
R
GND
R
3
R
1
R
2
C
V1
C
v
31
C
v
23
H
1
C
V3
Capacitance between horizontal transfer
clocks
Capacitance between reset gate clock
and GND
Capacitance between substrate clock
and GND
PDF 
ZIP